MHRD_Guide

@(Steam蒸汽动力)[MHRD|Game|How To]

[CH]游戏解决方案

1.解决方案将作为完整的代码呈现，部分结决方案将有理论分析或图解。

2.根据记录板判断，解决方案远非理想。

3.慎重考虑直接参考解决方案

附：我们欢迎错误/错别字。

@[TOC]

[DE]
1.Die Lösung wird als vollständiger Code präsentiert, und einige der Lösungen werden eine theoretische Analyse oder Illustration haben.

2.Laut der Rekordbehörde ist die Lösung alles andere als ideal.

3.Berücksichtigen Sie sorgfältig die direkte Referenzlösung.

PS: Wir freuen uns über Fehler / Tippfehler.

[RU]
1.Решение будет представлено в виде полного кода, а некоторые из решений будут иметь теоретический анализ или иллюстрацию.

2.Согласно авторитету записи, решение далеко не идеальное.

3.Внимательно рассмотрите прямое справочное решение.

PS: Мы рады ошибкам / опечаткам.

Logic Circuits

NAND
NAND, NAND4B, NAND16B

[CH]这个器件是直接给出的，所谓的开局一条狗（NAND），器件全靠连，任务全靠爆。
[CH]给我一个NAND，我就能复制成16bit的指令CPU。
[RU] Решены по умолчанию.
[ENG] Solved by default.

NOT

NOT
NOT

1 2 3 4 5 6 7

Parts: NAND NAND; Wires: in -> NAND.in1, in -> NAND.in2, NAND.out -> out ;

NOT4B
NOT4B

1 2 3 4 5 6 7 8 9 10 11 12 13

Parts: NOT1 NOT, NOT2 NOT, NOT3 NOT, NOT4 NOT; Wires: in[1] -> NOT1.in, in[2] -> NOT2.in, in[3] -> NOT3.in, in[4] -> NOT4.in, NOT1.out -> out[1], NOT2.out -> out[2], NOT3.out -> out[3], NOT4.out -> out[4] ;

NOT16B
[CH]做完4bit NOT，16bit NOT自动就爆出来了。
[RU] Решен Тедом.
[ENG] Solved by Ted.

AnD

AND
AND

1 2 3 4 5 6 7 8

Parts: NAND NAND, NOT NOT; Wires: in1 -> NAND.in1, in2 -> NAND.in2, NAND.out -> NOT.in, NOT.out -> out ;

AND4B
AND4B

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18

Parts: AND1 AND, AND2 AND, AND3 AND, AND4 AND; Wires: in1[1] -> AND1.in1, in1[2] -> AND2.in1, in1[3] -> AND3.in1, in1[4] -> AND4.in1, in2[1] -> AND1.in2, in2[2] -> AND2.in2, in2[3] -> AND3.in2, in2[4] -> AND4.in2, AND1.out -> out[1], AND2.out -> out[2], AND3.out -> out[3], AND4.out -> out[4] ;

AND16B
[CH]做完4bit AND，16bit AND自动就爆出来了。
[RU] Решен Тедом.
[ENG] Solved by Ted.

OR

OR
OR

1 2 3 4 5 6 7 8 9

Parts: NOT1 NOT, NOT2 NOT, NAND NAND; Wires: in1 -> NOT1.in, in2 -> NOT2.in, NOT1.out -> NAND.in1, NOT2.out -> NAND.in2, NAND.out -> out ;

OR4B
[CH]自动就爆出来了，懂我意思就行。
[RU] Решен Тедом.
[ENG] Solved by Ted.

OR16B
[CH]自爆懂行。
[RU] Решен Тедом.
[ENG] Solved by Ted.

OR4W
OR4W

1 2 3 4 5 6 7 8 9 10 11 12

Parts: OR1 OR, OR2 OR, OR3 OR; Wires: in[1] -> OR1.in1, in[2] -> OR1.in2, in[3] -> OR2.in1, in[4] -> OR2.in2, OR1.out -> OR3.in1, OR2.out -> OR3.in2, OR3.out -> out ;

OR16W
[CH]自行。
[RU] Решен Тедом.
[ENG] Solved by Ted.

XOR
XOR

1 2 3 4 5 6 7 8 9 10 11

Parts: NAND NAND, AND AND, OR OR; Wires: in1 -> NAND.in1, in2 -> NAND.in2, in1 -> OR.in1, in2 -> OR.in2, NAND.out -> AND.in1, OR.out -> AND.in2, AND.out -> out ;

XOR4B
[CH]自行。
[RU] Решен Тедом.
[ENG] Solved by Ted.

XOR16B
[CH]自行。
[RU] Решен Тедом.
[ENG] Solved by Ted.

OR4W
OR4W

1 2 3 4 5 6 7 8 9 10 11 12

Parts: OR1 OR, OR2 OR, OR3 OR; Wires: in[1] -> OR1.in1, in[2] -> OR1.in2, in[3] -> OR2.in1, in[4] -> OR2.in2, OR1.out -> OR3.in1, OR2.out -> OR3.in2, OR3.out -> out ;

OR16W
[CH]。
[RU] Решен Тедом.
[ENG] Solved by Ted.

XOR
XOR

1 2 3 4 5 6 7 8 9 10 11

Parts: NAND NAND, AND AND, OR OR; Wires: in1 -> NAND.in1, in2 -> NAND.in2, in1 -> OR.in1, in2 -> OR.in2, NAND.out -> AND.in1, OR.out -> AND.in2, AND.out -> out ;

XOR4B
[CH]
[RU] Решен Тедом.
[ENG] Solved by Ted.

XOR16B
[CH]
[RU] Решен Тедом.
[ENG] Solved by Ted.

Advanced Circuits

MUX

MUX
MUX

1 2 3 4 5 6 7 8 9 10 11 12

Parts: AND1 AND, AND2 AND, NOT NOT, OR OR; Wires: sel -> NOT.in, NOT.out -> AND1.in1, in1 -> AND1.in2, sel -> AND2.in1, in2 -> AND2.in2, AND1.out -> OR.in1, AND2.out -> OR.in2, OR.out -> out ;

MUX4B
MUX4B

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23

Parts: MUX1 MUX, MUX2 MUX, MUX3 MUX, MUX4 MUX; Wires: in1[1] -> MUX1.in1, in2[1] -> MUX1.in2, sel -> MUX1.sel, MUX1.out -> out[1], in1[2] -> MUX2.in1, in2[2] -> MUX2.in2, sel -> MUX2.sel, MUX2.out -> out[2], in1[3] -> MUX3.in1, in2[3] -> MUX3.in2, sel -> MUX3.sel, MUX3.out -> out[3], in1[4] -> MUX4.in1, in2[4] -> MUX4.in2, sel -> MUX4.sel, MUX4.out -> out[4] ;

MUX16B
[CH]
[RU] Решен Тедом.
[ENG] Solved by Ted.

MUX4W16B
[CH]
[RU] Решен Тедом.
[ENG] Solved by Ted.

DEMUX

DEMUX
DEMUX

1 2 3 4 5 6 7 8 9 10 11 12

Parts: AND1 AND, AND2 AND, NOT NOT; Wires: sel -> NOT.in, NOT.out -> AND1.in1, in -> AND1.in2, AND1.out -> out1, sel -> AND2.in1, in -> AND2.in2, AND2.out -> out2 ;

DEMUX4W
DEMUX4W

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Parts: NOT1 NOT, NOT2 NOT, AND11 AND, AND12 AND, AND 21 AND, AND22 AND, AND31 AND, AND32 AND, AND41 AND, AND42 AND; Wires: sel[1] -> NOT1.in, sel[2] -> NOT2.in, in -> AND11.in1, NOT1.out -> AND11.in2, AND11.out -> AND12.in1, NOT2.out -> AND12.in2, AND12.out -> out1, in -> AND21.in1, sel[1] -> AND21.in2, AND21.out -> AND22.in1, NOT2.out -> AND22.in2, AND22.out -> out2, in -> AND31.in1, NOT1.out -> AND31.in2, AND31.out -> AND32.in1, sel[2] -> AND32.in2, AND32.out -> out3, in -> AND41.in1, sel[1] -> AND41.in2, AND41.out -> AND42.in1, sel[2] -> AND42.in2, AND42.out -> out4 ;

ADDER

ADDER

HALFADDER

1 2 3 4 5 6 7 8 9 10 11

Parts: AND AND, XOR XOR; Wires: in1 -> AND.in1, in2 -> AND.in2, AND.out -> carry, in1 -> 大专栏  MHRD_GuideXOR.in1, in2 -> XOR.in2, XOR.out -> out ;

FULLADDER

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17

Parts: OR OR, XOR1 XOR, XOR2 XOR, AND1 AND, AND2 AND; Wires: in1 -> XOR1.in1, in2 -> XOR1.in2, XOR1.out -> XOR2.in1, carryIn -> XOR2.in2, XOR2.out -> out, in1 -> AND1.in1, in2 -> AND1.in2, XOR1.out -> AND2.in1, carryIn -> AND2.in2, AND1.out -> OR.in1, AND2.out -> OR.in2, OR.out -> carryOut ;

ADDER4B

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

Parts: FAD1 FULLADDER, FAD2 FULLADDER, FAD3 FULLADDER, FAD4 FULLADDER; Wires: in1[1] -> FAD1.in1, in2[1] -> FAD1.in2, carryIn -> FAD1.carryIn, FAD1.out -> out[1], in1[2] -> FAD2.in1, in2[2] -> FAD2.in2, FAD1.carryOut -> FAD2.carryIn, FAD2.out -> out[2], in1[3] -> FAD3.in1, in2[3] -> FAD3.in2, FAD2.carryOut -> FAD3.carryIn, FAD3.out -> out[3], in1[4] -> FAD4.in1, in2[4] -> FAD4.in2, FAD3.carryOut -> FAD4.carryIn, FAD4.out -> out[4], FAD4.carryOut -> carryOut ;

ADDER16B
[CH]
[RU] Решен Тедом.
[ENG] Solved by Ted.

ALU

ALU
ALU4B

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35

Parts: MUX1 MUX4B, MUX2 MUX4B, MUX3 MUX4B, MUX4 MUX4B, NOT1 NOT4B, NOT2 NOT4B, NOT3 NOT4B, ZERO NOT, NAND NAND4B, ADD ADDER4B, SET OR4W; Wires: in1 -> NOT1.in, in2 -> NOT2.in, in1 -> MUX4.in1, NOT1.out -> MUX4.in2, opCode[4] -> MUX4.sel, in2 -> MUX3.in1, NOT2.out -> MUX3.in2, opCode[3] -> MUX3.sel, MUX4.out -> ADD.in1, MUX3.out -> ADD.in2, MUX4.out -> NAND.in1, MUX3.out -> NAND.in2, ADD.out -> MUX2.in1, NAND.out -> MUX2.in2, opCode[2] -> MUX2.sel, MUX2.out -> NOT3.in, MUX2.out -> MUX1.in1, NOT3.out -> MUX1.in2, opCode[1] -> MUX1.sel, MUX1.out -> out, MUX1.out[4] -> negative, MUX1.out -> SET.in, SET.out -> ZERO.in, ZERO.out -> zero ;

ALU16B
[CH]
[RU] Решен Тедом.
[ENG] Solved by Ted.

Memory

Memory

DFF

DFF
DFF
[CH]
[RU] Решен по умолчанию.
[ENG] Solved by default.

REGISTER

REGISTER
REGISTER

1 2 3 4 5 6 7 8 9

Parts: MUX MUX, DFF DFF; Wires: in -> MUX.in2, load -> MUX.sel, MUX.out -> DFF.in, DFF.out -> MUX.in1, DFF.out -> out ;

REGISTER4B
REGISTER4B

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19

Parts: REG1 REGISTER, REG2 REGISTER, REG3 REGISTER, REG4 REGISTER; Wires: in[1] -> REG1.in, load -> REG1.load, REG1.out -> out[1], in[2] -> REG2.in, load -> REG2.load, REG2.out -> out[2], in[3] -> REG3.in, load -> REG3.load, REG3.out -> out[3], in[4] -> REG4.in, load -> REG4.load, REG4.out -> out[4] ;

REGISTER16B
[CH]
[RU] Решен Тедом.
[ENG] Solved by Ted.

RAM

RAM

RAM4W16B

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23

Parts: REG1 REGISTER16B, REG2 REGISTER16B, REG3 REGISTER16B, REG4 REGISTER16B, DEMUX DEMUX4W, MUX MUX4W16B; Wires: load -> DEMUX.in, address -> DEMUX.sel, DEMUX.out1 -> REG1.load, DEMUX.out2 -> REG2.load, DEMUX.out3 -> REG3.load, DEMUX.out4 -> REG4.load, in -> REG1.in, in -> REG2.in, in -> REG3.in, in -> REG4.in, REG1.out -> MUX.in1, REG2.out -> MUX.in2, REG3.out -> MUX.in3, REG4.out -> MUX.in4, address -> MUX.sel, MUX.out -> out ;

RAM64KW16B
[CH]
[RU] Решен Тедом.
[ENG] Solved by Ted.

COUNTER

COUNTER

COUNTER4B

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17

Parts: LOAD MUX4B, RESET MUX4B, REG REGISTER4B, ADD ADDER4B; Wires: REG.out -> ADD.in1, 1 -> ADD.in2[1], ADD.out -> LOAD.in1, in -> LOAD.in2, load -> LOAD.sel, LOAD.out -> RESET.in1, 0000 -> RESET.in2, reset -> RESET.sel, RESET.out -> REG.in, 1 -> REG.load, REG.out -> out ;

COUNTER16B
[CH]
[RU] Решен Тедом.
[ENG] Solved by Ted.

Decoder

Decoder
DECODER

[CH]来来，上专车。

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27

Parts: MUX1 MUX, MUX2 MUX, MUX3 MUX, MUX7 MUX, DEMUX DEMUX4W; Wires: instr[16] -> MUX1.sel, instr[16] -> MUX2.sel, instr[16] -> MUX3.sel, instr[16] -> MUX7.sel, instr[6] -> MUX7.in1, 1 -> MUX2.in2, instr[14:15] -> DEMUX.sel, 1 -> DEMUX.in, DEMUX.out2 -> MUX1.in1, DEMUX.out3 -> MUX2.in1, DEMUX.out4 -> MUX3.in1, instr[16] -> cToM, MUX1.out -> loadA, MUX2.out -> loadM, MUX3.out -> loadD, instr[13] -> op1, instr[11:12] -> op2, instr[7:10] -> opCode, MUX7.out -> jmpIfZ, instr[1:15] -> constant ;

CPU

CPU
CPU

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39

Parts: decoder DECODER, mReg REGISTER16B, aReg REGISTER16B, pc COUNTER16B, alu ALU16B, mrMUX MUX16B, aluMUX MUX16B, aluMUX4W MUX4W16B, pcAND AND; Wires: instr -> decoder.instr, decoder.loadD -> write, decoder.opCode -> alu.opCode, decoder.op1 -> aluMUX.sel, aReg.out -> aluMUX.in1, decoder.constant[1:5] -> aluMUX.in2[1:5], aluMUX.out -> alu.in1, decoder.op2 -> aluMUX4W.sel, decoder.constant[1:5] -> aluMUX4W.in1[1:5], aRreg -> aluMUX4W.in2, mReg -> aluMUX4W.in3, data -> aluMUX4W.in4, aluMUX4W.out -> alu.in2, decoder.cToM -> mrMUX.sel, decoder.constant -> mrMUX.in2[1:15], alu.out -> mrMUX.in1, mrMUX.out -> mReg.in, decoder.loadM -> mReg.load, decoder.loadA -> aReg.load, alu.out -> aReg.in, alu.zero -> pcAND.in1, decoder.jmpIfZ -> pcAND.in2, pcAND.out -> pc.load, mReg,out -> pc.in, alu.out -> result, mReg.out -> dataAddr, pc.out -> instrAddr, reset -> pc.reset ;

成就/Достижения/Achievements

[CH]
所有成就都可以在游戏中获得，不需要任何特殊操作。

[DE]
Alle Erfolge können während des Spiels erzielt werden und erfordern keine spezielle Manipulation.

[RU]
Все достижения могут быть получены в процессе прохождения и не требуют каких-то специальных манипуляций.

[ENG]
All achievements can be obtained during the game and don’t require any special manipulation.