CACHE COHERENCE AND THE MESI PROTOCOL

COMPUTER ORGANIZATION AND ARCHITECTURE DESIGNING FOR PERFORMANCE NINTH EDITION

In contemporary multiprocessor systems, it is customary to have one or two levels
of cache associated with each processor. This organization is essential to achieve
reasonable performance. It does, however, create a problem known as the cache

coherence problem. The essence of the problem is this: Multiple copies of the same
data can exist in different caches simultaneously, and if processors are allowed
to update their own copies freely, an inconsistent view of memory can result. In
Chapter 4 we defined two common write policies:

• Write back: Write operations are usually made only to the cache. Main mem-
ory is only updated when the corresponding cache line is flushed from the
cache.
• Write through: All write operations are made to main memory as well as to
the cache, ensuring that main memory is always valid.

It is clear that a write-back policy can result in inconsistency. If two caches
contain the same line, and the line is updated in one cache, the other cache will
unknowingly have an invalid value. Subsequent reads to that invalid line produce
invalid results. Even with the write-through policy, inconsistency can occur unless
other caches monitor the memory traffic or receive some direct notification of the
update.
In this section, we will briefly survey various approaches to the cache coher-
ence problem and then focus on the approach that is most widely used: the MESI
(modified/exclusive/shared/invalid) protocol. A version of this protocol is used on
both the Pentium 4 and Power PC implementations.
For any cache coherence protocol, the objective is to let recently used local
variables get into the appropriate cache and stay there through numerous reads and
write, while using the protocol to maintain consistency of shared variables that might
be in multiple caches at the same time. Cache coherence approaches have generally
been divided into software and hardware approaches. Some implementations adopt
a strategy that involves both software and hardware elements. Nevertheless, the
classification into software and hardware approaches is still instructive and is com-
monly used in surveying cache coherence strategies.