$stop and $finish in verilog
$stop - Pauses the simulation, so you can resume it by using fg command in linux. In this case lincense will not be released and process also is not killed, consuming memory.
$finish - Simulation is finished, so releasing of license and killing the process will be done.
$finish;
Finishes a simulation and exits the simulation process.
$stop;
Halts a simulation and enters an interactive debug mode.
$stop : Undesired termination of the simulation. All the system activities are suspended.
$finish : Used to relieve the compiler.
$finish
exits the simulation and gives control back to the operating system.
$stop
suspends the simulation and put interactive mode.
s a simulator in an
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