VGA IP核的制作

今天看了本《系统晶片设计-使用NIOS》这本书，看到VGA IP核的设计不错，特移植到Cyclone III上来，试验一下效果。

顶层代码：binary_VGA.v

 module    binary_VGA (    iDATA,    oDATA,    iADDR,iWR,
                         iRD, iCS, iRST_N, iCLK,
                         VGA_R,    VGA_G,    VGA_B,
                         VGA_HS,    VGA_VS,    VGA_SYNC,
                         VGA_BLANK,    VGA_CLK    );
 
 output    [:]    oDATA;
 input    [:]    iDATA;
 input    [:]    iADDR;
 input            iWR,iRD,iCS;
 input            iCLK,iRST_N;
 
 output    [:]    VGA_R;
 output    [:]    VGA_G;
 output    [:]    VGA_B;
 output            VGA_HS;
 output            VGA_VS;
 output            VGA_SYNC;
 output            VGA_BLANK;
 output            VGA_CLK;
 
 wire            iCLK_25;
 reg        [:]    RGB_EN;
 reg        [:]    oDATA;
 wire    [:]    mVGA_ADDR;
 reg    [:]    oRed;
 reg    [:]    oGreen;
 reg    [:]    oBlue;
 parameter    RAM_SIZE    =    'h4B000;
 
 always@(posedge iCLK or negedge iRST_N)
 begin
     if(!iRST_N)
     begin
         RGB_EN    <=    ;
         oDATA    <=    ;
     end
     else
     begin
         if(iCS)
         begin
             if(iWR)
             begin
                 case(iADDR)
                 RAM_SIZE+ :    RGB_EN    <=    iDATA[:];
                 endcase
             end
             else if(iRD)
             begin
                 case(iADDR)
                 RAM_SIZE+ :    oDATA    <=    RGB_EN    ;
                 endcase
             end
         end
     end
 end
 
 ram_binary_VGA     u1    (    //    Write In Side
                     .data(iDATA[:]),
                     .wren(iWR && (iADDR < RAM_SIZE) && iCS),
                     .wraddress({iADDR[:],~iADDR[:]}),
                     .wrclock(iCLK),
                     //    Read Out Side
                     .rdaddress(mVGA_ADDR[:]),
                     .rdclock(VGA_CLK),
                     .q(ROM_DATA));
 
 tff t0(.clk(iCLK),.t('b1),.q(iCLK_25));                    
 
 reg        [:]        ADDR_d;
 reg        [:]        ADDR_dd;
 wire    [:]        ROM_DATA;
 
 always@(posedge VGA_CLK or negedge iRST_N)
 begin
     if(!iRST_N)
     begin
         oRed    <=    ;
         oGreen    <=    ;
         oBlue    <=    ;
         ADDR_d    <=    ;
         ADDR_dd    <=    ;
     end
     else
     begin
         ADDR_d    <=    mVGA_ADDR[:];
         ADDR_dd    <=    ~ADDR_d;
         oRed    <=    ROM_DATA[ADDR_dd]?    'b1111111111:10'b00000000;
         oGreen    <=    ROM_DATA[ADDR_dd]?    'b1111111111:10'b00000000;
         oBlue    <=    ROM_DATA[ADDR_dd]?    'b1111111111:10'b00000000;
     end
 end
 
 VGA_ctr        u0    (    //    Host Side
                     .i_RGB_EN(RGB_EN),
                     .oAddress(mVGA_ADDR),
                     .iRed    (oRed),
                     .iGreen    (oGreen),
                     .iBlue    (oBlue),
                     //    VGA Side
                     .oVGA_R(VGA_R),
                     .oVGA_G(VGA_G),
                     .oVGA_B(VGA_B),
                     .oVGA_H_SYNC(VGA_HS),
                     .oVGA_V_SYNC(VGA_VS),
                     .oVGA_SYNC(VGA_SYNC),
                     .oVGA_BLANK(VGA_BLANK),
                     .oVGA_CLOCK(VGA_CLK),
                     //    Control Signal
                     .iCLK_25(iCLK_25),
                     .iRST_N(iRST_N)    );
 
 endmodule

binary_VGA

VGA_ctl.v 如下：

 module    VGA_ctr(i_RGB_EN,iRed,iGreen,iBlue,
             oVGA_R,oVGA_G,oVGA_B,oVGA_H_SYNC,
             oVGA_V_SYNC,oVGA_SYNC,oVGA_BLANK,oVGA_CLOCK,
             iCLK_25, iRST_N, oAddress);
 
 input                iCLK_25;
 input                iRST_N;
 input        [:]    i_RGB_EN;
 input        [:]    iRed,iGreen,iBlue;
 
 output        [:]    oAddress;
 
 output        [:]    oVGA_R,oVGA_G,oVGA_B;
 output                oVGA_H_SYNC,oVGA_V_SYNC;
 output                oVGA_SYNC;
 output                oVGA_BLANK;
 output                oVGA_CLOCK;
 
 //    H_Sync Generator, Ref. 25 MHz Clock
 parameter    H_SYNC_CYC    =    ;
 parameter    H_SYNC_TOTAL=    ;
 
 reg        [:]        H_Cont;
 reg            oVGA_H_SYNC;
 always@(posedge iCLK_25 or negedge iRST_N)
 begin
     if(!iRST_N)
     begin
         H_Cont        <=    ;
         oVGA_H_SYNC    <=    ;
     end
     else
     begin
         //    H_Sync Counter
         if( H_Cont < H_SYNC_TOTAL)  //H_SYNC_TOTAL=800
         H_Cont    <=    H_Cont+;
         else
         H_Cont    <=    ;
         //    H_Sync Generator
         if( H_Cont < H_SYNC_CYC ) //H_SYNC_CYC =96
         oVGA_H_SYNC    <=    ;
         else
         oVGA_H_SYNC    <=    ;
     end
 end
 
 parameter    V_SYNC_TOTAL=    ;
 parameter    V_SYNC_CYC    =    ;
  reg        [:]        V_Cont;
 reg            oVGA_V_SYNC;
 
 //    V_Sync Generator, Ref. H_Sync
 always@(posedge iCLK_25 or negedge iRST_N)
 begin
     if(!iRST_N)
     begin
         V_Cont        <=    ;
         oVGA_V_SYNC    <=    ;
     end
     else
     begin
         //    When H_Sync Re-start
         if(H_Cont==)
         begin
             //    V_Sync Counter
             if( V_Cont < V_SYNC_TOTAL ) //V_SYNC_TOTAL =525
             V_Cont    <=    V_Cont+;
             else
             V_Cont    <=    ;
             //    V_Sync Generator
             if(    V_Cont < V_SYNC_CYC ) // V_SYNC_CYC =2
             oVGA_V_SYNC    <=    ;
             else
             oVGA_V_SYNC    <=    ;
         end
     end
 end
 
 parameter    H_SYNC_BACK    =    +;
 parameter    V_SYNC_BACK    =    +;
 parameter    X_START        =    H_SYNC_CYC+H_SYNC_BACK+;
 parameter    Y_START        =    V_SYNC_CYC+V_SYNC_BACK;
 parameter    H_SYNC_ACT    =    ;
 parameter    V_SYNC_ACT    =    ;
 reg        [:]    oVGA_R,oVGA_G,oVGA_B;
 always@(H_Cont or V_Cont or i_RGB_EN or iRed or
         iGreen or iBlue )
 begin
     if(H_Cont>=X_START+     && H_Cont<X_START+H_SYNC_ACT+ &&
         V_Cont>=Y_START     && V_Cont<Y_START+V_SYNC_ACT)
     begin
        if (i_RGB_EN[]==)
         oVGA_R=iRed    ;
         else
         oVGA_R=;
         if (i_RGB_EN[]==)
         oVGA_G=iGreen    ;
         else
         oVGA_G=;
         if (i_RGB_EN[]==)
         oVGA_B=iBlue    ;
         else
         oVGA_B=;
     end
     else
     begin
         oVGA_R=;oVGA_G=;oVGA_B=;
     end
 end
 
 assign    oVGA_BLANK    =    oVGA_H_SYNC & oVGA_V_SYNC;
 assign    oVGA_SYNC    =    'b0;
 assign    oVGA_CLOCK    =    ~iCLK_25;
 
  reg [:]   oCoord_X,oCoord_Y;
  reg    [:]    oAddress;
 always@(posedge iCLK_25 or negedge iRST_N)
 begin
     if(!iRST_N)
     begin
         oCoord_X    <=    ;
         oCoord_Y    <=    ;
         oAddress    <=    ;
     end
     else
     begin
         if(    H_Cont>=X_START && H_Cont<X_START+H_SYNC_ACT &&
             V_Cont>=Y_START && V_Cont<Y_START+V_SYNC_ACT )
         begin
             oCoord_X    <=    H_Cont-X_START;
             oCoord_Y    <=    V_Cont-Y_START;
             oAddress    <=    oCoord_Y*H_SYNC_ACT+oCoord_X-;
         end
     end
 end
 
 endmodule
 
 //    VGA Side
 
 //    Internal Registers and Wires

VGA_tel

ram_binary_VGA的调用见下图：

关于VGA_init.mif的调用，

接下来选择View-Address Radix 选择Decimal；选择View-Memory Radix 选择Binary；选择视窗Edit--Custom Fill Cells，出现如下框图：

完后，添加IP核，

添加入进去IP核即可。注意：SOPC可以自动寻找IP核目录，只限于工程文件夹的子目录，如果在子目录中再添加目录，不可以寻找，必须在sopc中指定相应的目录。

VGAtest实验

pingpong兵乓球实验