基于BASYS2的VHDL程序——分频和数码管静态显示程序

转载请注明出处：http://www.cnblogs.com/connorzx/p/3633860.html

分频是基于计数器程序。由于FPGA的并行处理能力，根本不需要单片机式的中断指令，用起来很方便。

数码管是靠段选和片选控制的。即所有数目管公用一套八段LED选择端，每个管的亮灭靠片选控制。只要刷新频率够高，就能出现连续的效果。

代码如下：

  library IEEE;
  use IEEE.STD_LOGIC_1164.ALL;
  use IEEE.STD_LOGIC_ARITH.ALL;
  use IEEE.STD_LOGIC_UNSIGNED.ALL;

  entity digit_node is
      Port (
             clk : in  STD_LOGIC;
               an :  out  STD_LOGIC_VECTOR ( downto );
            seg : out  STD_LOGIC_VECTOR ( downto ));

 end digit_node;

 architecture Behavioral of digit_node is
 signal cnt:  INTEGER;
 signal sclk: STD_LOGIC;
 signal sw:STD_LOGIC_VECTOR ( downto );
 begin
 an<="";
 process(clk)
 begin
 if(clk'event and clk='') then
     if(cnt=) then
         cnt<=;
         sclk<=not sclk;
     else
         cnt<=cnt+;
     end if;
 end if;
 end process;
 process(sclk)
 begin
 if(sclk'event and sclk='') then
     sw<=sw+;
 case sw is
     when x""=>seg<=b"";
     when x""=>seg<=b"";
     when x""=>seg<=b"";
     when x""=>seg<=b"";
     when x""=>seg<=b"";
     when x""=>seg<=b"";
     when x""=>seg<=b"";
     when x""=>seg<=b"";
     when x""=>seg<=b"";
     when x""=>seg<=b"";
     when x"a"=>seg<=b"";
     when x"b"=>seg<=b"";
     when x"c"=>seg<=b"";
     when x"d"=>seg<=b"";
     when x"e"=>seg<=b"";
     when x"f"=>seg<=b"";
     when others=>seg<=b"";
 end case;
 end if;
 end process;

 end Behavioral;

约束文件如下：

 NET "clk"   LOC="B8";
 NET "an<0>" LOC="K14";
 NET "an<1>" LOC="M13";
 NET "an<2>" LOC="J12";
 NET "an<3>" LOC="F12";
 #NET "seg<7>" LOC="N13";
 NET "seg<6>" LOC="L14";
 NET "seg<5>" LOC="H12";
 NET "seg<4>" LOC="N14";
 NET "seg<3>" LOC="N11";
 NET "seg<2>" LOC="P12";
 NET "seg<1>" LOC="L13";
 NET "seg<0>" LOC="M12";