【iCore1S 双核心板_FPGA】例程五：Signal Tapll 实验——逻辑分析仪

核心代码：

//--------------------Module_Signal_TapII-------------------//
module Signal_TapII(
    input CLK_12M,
    output FPGA_LEDR,
    output FPGA_LEDG,
    output FPGA_LEDB
    );
//--------------------------rst_n--------------------------//
    reg [:]cnt_rst = 'd0;
    reg rst_n = 'd0;

    always @(posedge CLK_12M)
        begin
            if (cnt_rst == 'd10)
                begin
                    rst_n <= 'd1;
                    cnt_rst <= 'd10;
                end
            else cnt_rst <= cnt_rst + 'd1;
        end

//--------------------------led_clk--------------------------//
    reg led_clk;
    reg [:]cnt_led;

    always @(posedge CLK_12M or negedge rst_n)
        if (!rst_n)
            begin
                led_clk <= 'd0;
                cnt_led <= 'd0;
            end
        else if(cnt_led == 'd8000000)
            begin
                cnt_led <= 'd0;
                led_clk <= ~led_clk;
            end
        else cnt_led <= cnt_led + 'd1;

//---------------------------led---------------------------//
    reg [:]led;

    always @(posedge led_clk or negedge rst_n)
        if (!rst_n)
            begin
                led <= 'd1;
            end
        else
            begin
                if (led[])
                    begin
                        led <= 'd1;
                    end
                else
                    begin
                        led <= led << 'd1;
                    end
            end

    assign {FPGA_LEDR,FPGA_LEDG,FPGA_LEDB} = ~led;
//--------------------------endmodule-------------------------//
endmodule

实验方法及指导书:

链接：http://pan.baidu.com/s/1mhRklZE 密码：rbmk