重学Veriliog(2)——高级编程语句

1.判断

1.1 if ... else ...

• 有优先级
• 在组合逻辑电路中，需要避免产生Latch(避免结构不完整)
• Latch容易引起竞争冒险，同时静态时序分析工具也不好分析穿过Latch的路径？

1.2 case

• 无优先级
• 使用default，防止latch

1.3 casex和casez

• casez将分支中所有的z看作不“care”的值

casez (encoder)
    'b1???: high_lvl = 3;
    'b01??: high_lvl = 2;
    'b001?: high_lvl = 1;
    'b0001: high_lvl = 0;
    default : high_lvl = ;
endcase

• casex将分支中所有的z和x看作不“care”的值

casez (encoder)
    'b1xxx: high_lvl = 3;
    'b01xx: high_lvl = 2;
    'b001x: high_lvl = 1;
    'b0001: high_lvl = 0;
    default : high_lvl = ;
endcase

2.循环

2.1 forever

initial
begin
clk = ;
forver # clk = ~clk;
end

生成了50 的时钟

2.2 repeat

if (rotate == )
    repeat()
        begin
            tmp = data[];
            data = {data << ,tmp};
        end

重复8次

2.3 while

 initial
 begin
     count = ;
     while (count < )
     begin
         $ display ("Count = %d" , count);
         count = count + ;
     end
 end

2.4 for

 integer i;
 always @(inp or cnt)
 begin
     result[:] = ;
     result[:] = inp;
     if (cnt == )
     begin
     for (i = ; i  <= ; i=i+)
         begin
             result[i]=result[i - ];
         end
     result[:] = ;
     end
 end