【FPGA】Verilog实现交通信号灯

更新：

其余各部分代码已公布。

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大二数字电路的课程设计中，有一份日常作业使用Xilinx FPGA实现简易交通信号灯，但很可惜当时时间有限，没能最终完成。正好在这一学期选修SOPC设计课程，同样采用了Xilinx FPGA，故打算重新完成交通信号灯的相关内容。

本项目采用Digilent公司生产的BASYS3开发板，基于Xilinx FPGA，该板子目前可以在马云家买到，不过价格偏贵，在校学生可在digilent官网申请以更低价格买入。

大致的框架如下，只是个构思，还很不完善，后续会进行修改。比如现在我目前并没有把计时功能完全从State模块中摘出来，只是用Timer实例化了一个1s计时器在里面，并且用count计数。

TOP代码

module BASYS_BIGPROJECT_Top
(
input clk,
output wire[:]Trans_light,
output wire[:]Num_choose,
output wire[:]Num_data
);

wire [:]state_connect;
wire [:]count_connect;
//wire [6:0]Num_data_connect;
BASYS_BIGPROJECT_State state(
    .clk(clk),
    .state(state_connect),
    .count(count_connect)
    );

BASYS_BIGPROJECT_Display display(
    .clk(clk),
    .count(count_connect),
    .state(state_connect),
    .Trans_light(Trans_light),
    .Num_choose(Num_choose),
    .Num_data(Num_data)
    );

endmodule

State代码

module BASYS_BIGPROJECT_State(
input clk,
output [:]state,
output [:]count
    );

reg [:]reg_state = ;
reg [:]reg_count = ;
wire cnt_connect;

Freq_divider clk_1s(
    .clk(clk),
    .rst(),
    .count(cnt_connect)
    );

//states for lights
parameter MR_BG = 'b00;
parameter MR_BY = 'b01;
parameter MG_BR = 'b11;
parameter MY_BR = 'b10;

//green led for 4s, yellow led for 2s
always@(posedge cnt_connect)
begin
    case(reg_state)
    MR_BG:begin //main red, branch green
        if(reg_count<) begin
            reg_state <= MR_BG;
            reg_count <= reg_count + ;
        end
        else begin
            reg_state <= MR_BY;
            reg_count <= 'b000;
        end
    end
    MR_BY:begin //main red, branch yellow
        if(reg_count<) begin
            reg_state <= MR_BY;
            reg_count <= reg_count + ;
        end
        else begin
            reg_state <= MG_BR;
            reg_count <= 'b000;
        end
    end
    MG_BR:begin //main green, branch red
        if(reg_count<) begin
            reg_state <= MG_BR;
            reg_count <= reg_count + ;
        end
        else begin
            reg_state <= MY_BR;
            reg_count <= 'b000;
        end
    end
    MY_BR:begin //main yellow, branch red
        if(reg_count<) begin
            reg_state <= MY_BR;
            reg_count <= reg_count + ;
        end
        else begin
            reg_state <= MR_BG;
            reg_count <= 'b000;
        end
    end
    endcase
end
assign state = reg_state;
assign count = reg_count;

endmodule

Display代码

module BASYS_BIGPROJECT_Display
(
input clk,
input [:]state,
input [:]count,
output [:]Trans_light,
output [:]Num_choose,
output [:]Num_data
);

reg [:]reg_light = ;
reg [:]reg_Num_digit = ;
reg [:]reg_Num_choose = 'b1110;
wire [:]Num_data_connect;
wire refresh;

reg [:]Data_Main = ;
reg [:]Data_Branch = ;
//divider for refresh
Freq_divider #()play(
    .clk(clk),
    .rst('b0),
    .count(refresh)
);
//Decode the digit
Digital_decode decoder(
    .clk(clk),
    .data(reg_Num_digit),
    .Trans_num(Num_data_connect)
    );

//switch the light
always @(posedge clk)
begin
    case(state)
        'b00:begin
            reg_light <= 'b100001;
            Data_Main <=  - count;
            Data_Branch <=  - count;
        end
        'b01:begin
            reg_light <= 'b100010;
            Data_Main <=  - count;
            Data_Branch <=  - count;
        end
        'b11:begin
            reg_light <= 'b001100;
            Data_Main <=  - count;
            Data_Branch <=  - count;
        end
        'b10:begin
            reg_light <= 'b010100;
            Data_Main <=  - count;
            Data_Branch <=  - count;
        end
    endcase
end

//Scanned display for digit
always @(posedge refresh)
begin
    if(reg_Num_choose == 'b1110)
    begin
        reg_Num_choose <= 'b1011;
        reg_Num_digit <= Data_Main;
    end
    else
    begin
        reg_Num_choose <= 'b1110;
        reg_Num_digit <= Data_Branch;
    end
end

assign Trans_light = reg_light;
assign Num_choose = reg_Num_choose;
assign Num_data = Num_data_connect;
endmodule

Tools代码

module Freq_divider
#(parameter N = )
(
input clk,
input rst,
output [N-:]freq_div,
output count
);
reg [N-:]regN = ;
always@(posedge clk)
begin
    if(rst)
        regN <= ;
    else
        regN <= regN+;
end
assign freq_div = regN;
assign count = (regN == **N-)?'b1:1'b0;
endmodule

module Digital_decode
(
input clk,
input [:]data,
output [:]Trans_num
);

reg [:]reg_Trans_num = ;

always@(posedge clk)
begin
   case(data)
       'd0: reg_Trans_num <= 8'b0000_0011;
       'd1: reg_Trans_num <= 8'b1001_1111;
       'd2: reg_Trans_num <= 8'b0010_0101;
       'd3: reg_Trans_num <= 8'b0000_1101;
       'd4: reg_Trans_num <= 8'b1001_1001;
       'd5: reg_Trans_num <= 8'b0100_1001;
       'd6: reg_Trans_num <= 8'b0100_0001;
       'd7: reg_Trans_num <= 8'b0001_1111;
       'd8: reg_Trans_num <= 8'b0000_0001;
       'd9: reg_Trans_num <= 8'b0000_1001;
       default: reg_Trans_num <= 'b0001_0001;
   endcase
end
assign Trans_num = reg_Trans_num;
endmodule