VHDL_ADC之cic_diffcell

 library IEEE;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;

 library edclib;
 use edclib.pkg_xxxlib.all;　　-- package from company

 8 --! pipelined comb-chain for cic_filter
 entity cic_diffcell is
 generic
 (
     Width        : natural := ;        --! width
     M           : natural :=             --! difference fifo depth
 );
 port
 (
     RST         : in  std_logic;                            --! Async Reset
     C        : in  std_logic;                            --! Clock
     R         : in  std_logic;                            --! needed to clear  registers during sw-reset
     CEI         : in  std_logic;                            --! new data on input
     DIN        : in  std_logic_vector(Width- downto );    --! data in
     CEO         : out std_logic;                            --! new data on output
     DOUT    : out std_logic_vector(Width- downto )    --! data out
 );
 end cic_diffcell;

27 --! pipelined comb-chain for cic_filter
 architecture asic of cic_diffcell is
 type data_type is array (natural range <>) of std_logic_vector( Width- downto );    --! set of registers
 signal reg    : data_type(M downto );                        --! delay register (index 0 means DIN)
 signal diff    : std_logic_vector( Width- downto );            --! subtraction

 begin

 reg() <= din when r='' else (Width- => '', others => '');

37 --! stage delay
 gdel: for i in  to M generate
     UDEL : REGDCE generic map(Width) port map(RST,C,CEI,reg(i-),reg(i));
 end generate;

42 --subtract
 diff <= std_logic_vector( signed(din) - signed(reg(m)) ) when r='' else (others => ''); 

45 --Output-Reg (Sysclk delay)
 UOREG: REGDCE generic map(Width) port map(RST,C,CEI, diff, DOUT);

48 --CE-chain
 UCE: FFD port map(RST,C,CEI,CEO); 

 end asic;