E203的Makefile默认是调用 iverilog编译rtl,我们可以做如下修改,使其支持vcs编译。

1. 首先修改e200_opensource/tb/tb_top.v, 增加dump波形的两行代码,这样如果指定DUMPWAVE不等于0,就会打印dump出波形文件。

  initial begin
$value$plusargs("DUMPWAVE=%d",dumpwave);
if(dumpwave != 0)begin
// To add your waveform generation function
$fsdbDumpfile("dump.fsdb");
$fsdbDumpvars("+all");
end
end

2.修改e200_opensource/vsim/bin/run.makefile, 把SIM_TOOL,SIM_OPTIONS,WAVE_TOOL,WAVE_OPTIONS这些选项为vcs和verdi

RUN_DIR      := ${PWD}

TESTCASE     := ${RUN_DIR}/../../riscv-tools/riscv-tests/isa/generated/rv32ui-p-addi
DUMPWAVE := 1 VSRC_DIR := ${RUN_DIR}/../install/rtl
VTB_DIR := ${RUN_DIR}/../install/tb
TESTNAME := $(notdir $(patsubst %.dump,%,${TESTCASE}.dump))
TEST_RUNDIR := ${TESTNAME} RTL_V_FILES := $(wildcard ${VSRC_DIR}/*/*.v)
TB_V_FILES := $(wildcard ${VTB_DIR}/*.v) # The following portion is depending on the EDA tools you are using, Please add them by yourself according to your EDA vendors SIM_TOOL := vcs #To-ADD: to add the simulatoin tool
#SIM_TOOL := iverilog # this is a free solution here to use iverilog to compile the code SIM_OPTIONS := -full64 -line +vcsd +vpi -r +plusarg_save -Mupdate +cli+3 +error+10 +v2k +ntb_exit_on_error=10 -negdelay +neg_tchk +memcbk +sdrverbose -timescale=1ns/100ps +warn=all +warn=noTFIPC +warn=noWSUM -sverilog -l vcs.log -LDFLAGS -rdynamic -P ${NOVAS_HOME}/share/PLI/VCS/linux64/novas_new_dumper.tab ${NOVAS_HOME}/share/PLI/VCS/linux64/pli.a +incdir+${VSRC_DIR}/core/+${VSRC_DIR}/perips/
#To-ADD: to add the simulatoin tool options #SIM_OPTIONS := -o vvp.exec -I "${VSRC_DIR}/core/" -I "${VSRC_DIR}/perips/" -D DISABLE_SV_ASSERTION=1 -g2005
# This is a free solution here to use iverilog to compile the code. Please NOTE!!!!
#
# Note:
# Here we add a macro "DISABLE_SV_ASSERTION" to disable the system-verilog coded
# assertion in the RTL code because iverilog cannot support that syntax, if you
# use other EDA tools which support the systemverilog, you should not add this macro "DISABLE_SV_ASSERTION".
#
# Here we didnt add macro "ENABLE_TB_FORCE"
# that macro was used to enable the random interrupt and bus-error insertion to make
# more intensive test in e200_opensource/tb/tb_top.v.
# Although the test become more intensive, the drawback is it makes the regression
# simulation running very slower, so by default now it is turned off.
# If you want to turn on them without caring the the regression speed,
# you can just add macro `ENABLE_TB_FORCE` here in command line. SIM_EXEC := ../simv #To-ADD: to add the simulatoin executable
#SIM_EXEC := vvp ${RUN_DIR}/vvp.exec -none # The free vvp is tooooo slow to run, so just comment it out, and replaced with the fake way below
#SIM_EXEC := echo "Test Result Summary: PASS" # This is a fake run to just direct print PASS info to the log, the user need to actually replace it to the real EDA command WAV_TOOL := verdi #To-ADD: to add the waveform tool
WAV_OPTIONS := -2001 -sv -top tb_top +incdir+${VSRC_DIR}/core/+${VSRC_DIR}/perips/ #To-ADD: to add the waveform tool options
WAV_PFIX := #To-ADD: to add the waveform file postfix all: run compile.flg: ${RTL_V_FILES} ${TB_V_FILES}
@-rm -rf compile.flg
${SIM_TOOL} ${SIM_OPTIONS} ${RTL_V_FILES} ${TB_V_FILES} ;
touch compile.flg compile: compile.flg wave:
# gvim -p ${TESTCASE}.spike.log ${TESTCASE}.dump &
${WAV_TOOL} ${WAV_OPTIONS} ${RTL_V_FILES} ${TB_V_FILES} & run: compile
rm -rf ${TEST_RUNDIR}
mkdir ${TEST_RUNDIR}
cd ${TEST_RUNDIR}; ${SIM_EXEC} +DUMPWAVE=${DUMPWAVE} +TESTCASE=${TESTCASE} |& tee ${TESTNAME}.log; cd ${RUN_DIR}; .PHONY: run clean all

3. cd e200_opensource/vsim, 执行make install CORE=e203,

执行make install,则会在e200_opensource/vsim目录下,创建install目录,并把testbench文件和rtl文件copy到install目录,并把testbench文件tb_top.v中的e200,替换为core_name,E200替换为CORE_NAME,也就是e203。

SIM_DIR     := ${PWD}
RUN_DIR := ${PWD}/run
TESTNAME := rv32ui-p-add
TESTCASE := ${RUN_DIR}/../../riscv-tools/riscv-tests/isa/generated/${TESTNAME}
DUMPWAVE := 1
CORE := e203
CFG := ${CORE}_config E201 := e201
E203 := e203
E205 := e205
E205F := e205f
E205FD := e205fd
E225FD := e225fd CORE_NAME = $(shell echo $(CORE) | tr a-z A-Z)
core_name = $(shell echo $(CORE) | tr A-Z a-z) all: run_test install:
mkdir -p ${SIM_DIR}/install/tb
cp ${SIM_DIR}/../tb/tb_top.v ${SIM_DIR}/install/tb/ -rf
sed -i "s/e200/${core_name}/g" ${SIM_DIR}/install/tb/tb_top.v
sed -i "s/E200/${CORE_NAME}/g" ${SIM_DIR}/install/tb/tb_top.v
cp ${SIM_DIR}/../rtl/${core_name} ${SIM_DIR}/install/rtl -rf ${RUN_DIR}:
mkdir -p ${RUN_DIR}
rm -f ${RUN_DIR}/Makefile
ln -s ${SIM_DIR}/bin/run.makefile ${RUN_DIR}/Makefile compile: ${RUN_DIR}
make compile RUN_DIR=${RUN_DIR} -C ${RUN_DIR} wave: ${RUN_DIR}
make wave TESTCASE=${TESTCASE} RUN_DIR=${RUN_DIR} -C ${RUN_DIR} run_test: compile
make run DUMPWAVE=${DUMPWAVE} TESTCASE=${TESTCASE} RUN_DIR=${RUN_DIR} -C ${RUN_DIR} SELF_TESTS := $(patsubst %.dump,%,$(wildcard ${RUN_DIR}/../../riscv-tools/riscv-tests/isa/generated/rv32uc-p*.dump))
ifeq ($(core_name),${E203})
SELF_TESTS += $(patsubst %.dump,%,$(wildcard ${RUN_DIR}/../../riscv-tools/riscv-tests/isa/generated/rv32um-p*.dump))
SELF_TESTS += $(patsubst %.dump,%,$(wildcard ${RUN_DIR}/../../riscv-tools/riscv-tests/isa/generated/rv32ua-p*.dump))
endif
ifeq ($(core_name),${E205})
SELF_TESTS += $(patsubst %.dump,%,$(wildcard ${RUN_DIR}/../../riscv-tools/riscv-tests/isa/generated/rv32um-p*.dump))
SELF_TESTS += $(patsubst %.dump,%,$(wildcard ${RUN_DIR}/../../riscv-tools/riscv-tests/isa/generated/rv32ua-p*.dump))
endif
ifeq ($(core_name),${E205F})
SELF_TESTS += $(patsubst %.dump,%,$(wildcard ${RUN_DIR}/../../riscv-tools/riscv-tests/isa/generated/rv32um-p*.dump))
SELF_TESTS += $(patsubst %.dump,%,$(wildcard ${RUN_DIR}/../../riscv-tools/riscv-tests/isa/generated/rv32ua-p*.dump))
SELF_TESTS += $(patsubst %.dump,%,$(wildcard ${RUN_DIR}/../../riscv-tools/riscv-tests/isa/generated/rv32uf-p*.dump))
endif
ifeq ($(core_name),${E205FD})
SELF_TESTS += $(patsubst %.dump,%,$(wildcard ${RUN_DIR}/../../riscv-tools/riscv-tests/isa/generated/rv32um-p*.dump))
SELF_TESTS += $(patsubst %.dump,%,$(wildcard ${RUN_DIR}/../../riscv-tools/riscv-tests/isa/generated/rv32ua-p*.dump))
SELF_TESTS += $(patsubst %.dump,%,$(wildcard ${RUN_DIR}/../../riscv-tools/riscv-tests/isa/generated/rv32ud-p*.dump))
SELF_TESTS += $(patsubst %.dump,%,$(wildcard ${RUN_DIR}/../../riscv-tools/riscv-tests/isa/generated/rv32uf-p*.dump))
endif
ifeq ($(core_name),${E225FD})
SELF_TESTS += $(patsubst %.dump,%,$(wildcard ${RUN_DIR}/../../riscv-tools/riscv-tests/isa/generated/rv32um-p*.dump))
SELF_TESTS += $(patsubst %.dump,%,$(wildcard ${RUN_DIR}/../../riscv-tools/riscv-tests/isa/generated/rv32ua-p*.dump))
SELF_TESTS += $(patsubst %.dump,%,$(wildcard ${RUN_DIR}/../../riscv-tools/riscv-tests/isa/generated/rv32ud-p*.dump))
SELF_TESTS += $(patsubst %.dump,%,$(wildcard ${RUN_DIR}/../../riscv-tools/riscv-tests/isa/generated/rv32uf-p*.dump))
endif SELF_TESTS += $(patsubst %.dump,%,$(wildcard ${RUN_DIR}/../../riscv-tools/riscv-tests/isa/generated/rv32ui-p*.dump))
SELF_TESTS += $(patsubst %.dump,%,$(wildcard ${RUN_DIR}/../../riscv-tools/riscv-tests/isa/generated/rv32mi-p*.dump)) regress_prepare:
make compile
@-rm -rf ${RUN_DIR}/rv32*.log
regress_run:
$(foreach tst,$(SELF_TESTS), make run_test DUMPWAVE=0 TESTCASE=$(tst);)
regress_collect:
@-rm -rf ${RUN_DIR}/regress.res
@find ${RUN_DIR} -name "rv32*.log" -exec bin/find_test_fail.csh {} >> ${RUN_DIR}/regress.res \;
@cat ${RUN_DIR}/regress.res
regress: regress_prepare regress_run regress_collect clean:
rm -rf run
rm -rf install .PHONY: compile run install clean all run_test regress regress_prepare regress_run regress_collect

4. 在目录e200_opensource/vsim执行make compile

这是会执行以下的flow,会创建run目录,并链接run/Makefile到bin/run.makefile,这个时候执行make compile

${RUN_DIR}:
mkdir -p ${RUN_DIR}
rm -f ${RUN_DIR}/Makefile
ln -s ${SIM_DIR}/bin/run.makefile ${RUN_DIR}/Makefile compile: ${RUN_DIR}
make compile RUN_DIR=${RUN_DIR} -C ${RUN_DIR}

就是在run目录下执行Makefile文件中的make all,编译rtl代码和testbench文件。

all: run

compile.flg: ${RTL_V_FILES} ${TB_V_FILES}
@-rm -rf compile.flg
${SIM_TOOL} ${SIM_OPTIONS} ${RTL_V_FILES} ${TB_V_FILES} ;
touch compile.flg

5. 在e200_opensource/vsim目录里下执行make run_test, 则会调用以下flow,默认会run testcase rv32ui-p-add

run_test: compile
make run DUMPWAVE=${DUMPWAVE} TESTCASE=${TESTCASE} RUN_DIR=${RUN_DIR} -C ${RUN_DIR}
	cd ${TEST_RUNDIR}; ${SIM_EXEC} +DUMPWAVE=${DUMPWAVE} +TESTCASE=${TESTCASE} |& tee ${TESTNAME}.log; cd ${RUN_DIR};

此时run目录下会有rv32ui-p-add目录,里面会有波形文件和log文件。

6. 在e200_opensource/vsim目录里下执行 make run_test TESTNAME=rv32ui-p-and, 此时run目录下会有rv32ui-p-and目录,里面会有波形文件和log文件。

7. 在e200_opensource/vsim目录里下执行 make wave,则会在verdi中打开rtl文件,然后打开相应test的波形文件,就可以就行调试程序了。

8.我们对Makefile进行一点改动,用make debug TESTNAME=rv32ui-p-and 就可以同时打开design和波形了。

e200_opensource/vsim/Makefile, 增加debug部分。

wave: ${RUN_DIR}
make wave TESTCASE=${TESTCASE} RUN_DIR=${RUN_DIR} -C ${RUN_DIR} debug: ${RUN_DIR}
make debug TESTCASE=${TESTCASE} RUN_DIR=${RUN_DIR} -C ${RUN_DIR} run_test: compile
make run DUMPWAVE=${DUMPWAVE} TESTCASE=${TESTCASE} RUN_DIR=${RUN_DIR} -C ${RUN_DIR}

e200_opensource/vsim/run/Makefile, 增加debug部分。

RUN_DIR      := ${PWD}

TESTCASE     := ${RUN_DIR}/../../riscv-tools/riscv-tests/isa/generated/rv32ui-p-addi
DUMPWAVE := 1 VSRC_DIR := ${RUN_DIR}/../install/rtl
VTB_DIR := ${RUN_DIR}/../install/tb
TESTNAME := $(notdir $(patsubst %.dump,%,${TESTCASE}.dump))
TEST_RUNDIR := ${TESTNAME} RTL_V_FILES := $(wildcard ${VSRC_DIR}/*/*.v)
TB_V_FILES := $(wildcard ${VTB_DIR}/*.v)
WAVE_FILE := ${RUN_DIR}/${TESTNAME}/dump.fsdb
# The following portion is depending on the EDA tools you are using, Please add them by yourself according to your EDA vendors SIM_TOOL := vcs #To-ADD: to add the simulatoin tool
#SIM_TOOL := iverilog # this is a free solution here to use iverilog to compile the code SIM_OPTIONS := -full64 -line +vcsd +vpi -r +plusarg_save -Mupdate +cli+3 +error+10 +v2k +ntb_exit_on_error=10 -negdelay +neg_tchk +memcbk +sdrverbose -timescale=1ns/100ps +warn=all +warn=noTFIPC +warn=noWSUM -sverilog -l vcs.log -LDFLAGS -rdynamic -P ${NOVAS_HOME}/share/PLI/VCS/linux64/novas_new_dumper.tab ${NOVAS_HOME}/share/PLI/VCS/linux64/pli.a +incdir+${VSRC_DIR}/core/+${VSRC_DIR}/perips/
#To-ADD: to add the simulatoin tool options #SIM_OPTIONS := -o vvp.exec -I "${VSRC_DIR}/core/" -I "${VSRC_DIR}/perips/" -D DISABLE_SV_ASSERTION=1 -g2005
# This is a free solution here to use iverilog to compile the code. Please NOTE!!!!
#
# Note:
# Here we add a macro "DISABLE_SV_ASSERTION" to disable the system-verilog coded
# assertion in the RTL code because iverilog cannot support that syntax, if you
# use other EDA tools which support the systemverilog, you should not add this macro "DISABLE_SV_ASSERTION".
#
# Here we didnt add macro "ENABLE_TB_FORCE"
# that macro was used to enable the random interrupt and bus-error insertion to make
# more intensive test in e200_opensource/tb/tb_top.v.
# Although the test become more intensive, the drawback is it makes the regression
# simulation running very slower, so by default now it is turned off.
# If you want to turn on them without caring the the regression speed,
# you can just add macro `ENABLE_TB_FORCE` here in command line. SIM_EXEC := ../simv #To-ADD: to add the simulatoin executable
#SIM_EXEC := vvp ${RUN_DIR}/vvp.exec -none # The free vvp is tooooo slow to run, so just comment it out, and replaced with the fake way below
#SIM_EXEC := echo "Test Result Summary: PASS" # This is a fake run to just direct print PASS info to the log, the user need to actually replace it to the real EDA command WAV_TOOL := verdi #To-ADD: to add the waveform tool
WAV_OPTIONS := -2001 -sv -top tb_top +incdir+${VSRC_DIR}/core/+${VSRC_DIR}/perips/ #To-ADD: to add the waveform tool options
WAV_PFIX := #To-ADD: to add the waveform file postfix all: run compile.flg: ${RTL_V_FILES} ${TB_V_FILES}
@-rm -rf compile.flg
${SIM_TOOL} ${SIM_OPTIONS} ${RTL_V_FILES} ${TB_V_FILES} ;
touch compile.flg compile: compile.flg wave:
# gvim -p ${TESTCASE}.spike.log ${TESTCASE}.dump &
${WAV_TOOL} ${WAV_OPTIONS} ${RTL_V_FILES} ${TB_V_FILES} &
debug:
${WAV_TOOL} ${WAV_OPTIONS} ${RTL_V_FILES} ${TB_V_FILES} -ssf ${WAVE_FILE}
run: compile
rm -rf ${TEST_RUNDIR}
mkdir ${TEST_RUNDIR}
cd ${TEST_RUNDIR}; ${SIM_EXEC} +DUMPWAVE=${DUMPWAVE} +TESTCASE=${TESTCASE} |& tee ${TESTNAME}.log; cd ${RUN_DIR}; .PHONY: run clean all

9. 在e200_opensource/vsim目录里下执行make regress_run CORE=e203, 则会运行所有的testcase,进行回归测试。

10.  在e200_opensource/vsim目录里下执行make regress_collect CORE=e203, 则会比较所有的testcase结果,如果test pass,则打印PASS,失败,则打印FAIL

11. 在e200_opensource/vsim目录里下执行make clean, 则会删除install和run目录。

在vcs中编译及运行测试E203例子的更多相关文章

  1. 在PLSQL中编译复杂的java(转)

    原文地址:在PLSQL中编译复杂的java PLSQL中可以编译运行JAVA程序. 一个简单的例子: create or replace and compile java source named x ...

  2. [原]在Fedora中编译Libevent测试实例

    在我的昨天的博文<[原]我在Windows环境下的首个Libevent测试实例>中介绍了在Windows环境下如何编译一个echo server例子.今天我又试了一下在Linux环境中编译 ...

  3. Debian中编译内核

    转载: http://blog.163.com/libo_5/blog/static/156968520101016102051580/ http://hi.baidu.com/wg_wang/ite ...

  4. android在ubuntu中编译为.apk资料

    android在ubuntu中编译为.apk文件 今天我在ubuntu环境之下将android程序编译为.apk文件,特将其过程写下来: 1. 在windows环境下使用MyEclipse编辑好and ...

  5. Java--自定义Class并且在内存中编译,加载,实例化

    本文的目的: 使用者在程序运行期间,可以动态的写Java Class,不需要生成任何.Class文件就可以完全在内存中编译,加载,实例化. 1.需要用到的组件介绍 1)JavaCompiler:用于编 ...

  6. 在VS2012中编译WinXP兼容的程序

    VS2012默认是不兼容Windows XP的,编译链接出来的程序只能在Windows Vista及以上版本的操作系统上运行.可是有时需要在Windows XP上运行,又不得不用VS2012(例如用了 ...

  7. 在CentOS 6.4中编译安装gcc 4.8.1

    在CentOS 6.4中编译安装gcc 4.8.1 分类: C/C++ Linux/Unix2013-11-28 21:02 1877人阅读 评论(0) 收藏 举报 原文链接:http://www.c ...

  8. eclipse中编译时enum出现cannot be resolved to a type错误

    eclipse中编译时enum出现cannot be resolved to a type错误 通常是因为eclise使用的jdk版本的问题...默认是使用的是jdk1.5 应该去选择成jdk1.6或 ...

  9. 我教女朋友学编程html系列(5) html中table的用法和例子

    女朋友不是学计算机的,但是现在从事计算机行业,做技术支持,她想学习编程,因此我打算每天教她一点点,日积月累,带她学习编程,如果其他初学者感兴趣,可以跟着学. 为了将table介绍的简单.生动,具有实战 ...

随机推荐

  1. 一起学SpringMVC之入门篇

    本文属于SpringMVC的入门篇,属于基础知识,仅供学习分享使用,如有不足之处,还请指正. 什么是SpringMVC ? SpringMVC是一个基于Spring的MVC框架,继承了Spring的优 ...

  2. thymeleaf Exception processing template "xxx": Exception parsing document: template="xxx", line 6 - column 3报错解决的几种方法

    我是在SpringBoot项目使用Thymeleaf作为模板引擎时报的错误 controller代码非常简单,如下所示: @RequestMapping("/abc") publi ...

  3. C#控制内插字符串的格式

    C#6.0推出了内插字符串 结果展示: 内插表达式字段宽度和对齐方式: 结果展示:(+/-代表右对齐.左对齐,数字表示显示宽度)

  4. HBuilderx 模拟器调试设置

    模拟器名称    连接默认端口夜神安卓模拟器夜神安卓模拟器     62001逍遥安卓模拟器逍遥安卓模拟器     21503BlueStacks(蓝叠安卓模拟器)BlueStacks(蓝叠安卓模拟器 ...

  5. Android进阶之绘制-自定义View完全掌握(三)

    自定义View系列的第三篇博客,我们来学习如何实现自定义下拉框. 今天的程序,我们来实现这样的一个效果. 布局非常简单,我们直接开始编码. 修改activity_main.xml文件的代码. < ...

  6. Violet音乐社区设计文档

    目录 Violet音乐社区设计文档 一.引言 1.1 编写目的 1.2 开发背景 二.用例图设计 2.1游客实例设计 2.2 管理员实例设计 2.3 普通用户实例设计 三.类图设计 3.1 歌手类 3 ...

  7. grant localhost and % for mysql

  8. window2012安装oracle报INS-13001 环境不满足最低要求

    在windows server 2012R2安装Oracle客户端或者服务端时,会弹窗报错INS-13001 环境不满足最低要求此时可以进行以下操作进行解决 在解压后的Oracle安装文件目录中,找到 ...

  9. 实际场景:UI、原型与实际不符;研发怼你,你要怎么办?-Dotest软件测试

    实际公司场景:UI.原型与实际不符:你提交的问题(bug),开发又开始怼你,遇到这种情况,你会怎么办?怎么沟通?(如下图) 解释:大部分公司都是这样,区别在于差异性有多大:做出来的东西大部分与设计.原 ...

  10. springmvc的文件上传和JWT图形验证码

    相关pom依赖 <dependency> <groupId>commons-fileupload</groupId> <artifactId>commo ...