PatentTips - Hamming distance comparison

BACKGROUND INFORMATION

In a typical data processing environment, data may be transmitted in multiple packets, e.g., words, from one element, e.g., cache, to another element, e.g., processor, over a bus, e.g., parallel bus. A hamming distance may refer to the number of non-matching bits, i.e., the number of bits that changed state, in two consecutively transmitted data packets. For example, a first 16-bit data word may be sent from a cache to a processor comprising of all 1's followed by a second data word of all 0's. In the above example, the hamming distance would be 16 representing that each bit in the consecutively transmitted data packets changed state. The hamming distance may be represented by a particular voltage which may then be compared to a threshold voltage level. If the hamming distance is above or below the threshold voltage, an activity may occur. Hamming distance comparison may be used in many applications including image processing and bus inversion.

Bus inversion may refer to transmitting the complement value of the data bits instead of the true value of the data bits when the number of bits to be switched is greater than half of the number of bits in the transmitted packet, e.g., word. Each time a bit changes state, a bus driver associated with that bit may be asserted to switch the state of the bit. Switching, however, consumes a significant amount of power. Consequently, it would be desirable to minimize switching activity. Bus inversion may be one method of minimizing at least in part switching activity. Bus inversion may minimize at least in part switching activity by transmitting the complement value of the data bits instead of the true value of the data bits when the number of bits to be switched is greater than half of the number of bits in the transmitted packet, e.g., word.

For example, a first data word may be sent from a cache to a processor with the binary value of 1111111111111111 followed by a second data word with the binary value of 0000000001111111. As illustrated, more than half of the bits in the second data word have changed in value with respect to the first data word. Instead of transmitting the true value of 0000000001111111 thereby switching nine bits, the value of 1111111110000000 may be transmitted thereby only switching seven bits. In conjunction with transmitting the complemented values, an extra bit commonly referred to as the inversion bit may be transmitted which indicates whether or not to invert the values of the transmitted data values

One method of performing hamming distance comparison to perform bus inversion uses a hamming distance comparator as illustrated in FIG. 1. The hamming distance comparator of FIG. 1 may implement a Capacitor Threshold Logic (CTL) gate as discussed further below. CTL may refer to a dynamic circuit which requires a periodic refresh or precharge cycle, but unlike conventional dynamic Complementary Metal Oxide Semiconductor (CMOS) gates, the circuit may be operated in synchronous as well as in asynchronous mode.

Referring to FIG. 1, a hamming distance comparator 100 may be used to determine whether to invert the bus or not, i.e., implement bus inversion. Hamming distance comparator 100 may comprise a bus 101 coupled between one element, e.g., cache, and another element, e.g., processor, in a data processing system. Hamming distance comparator 100 may further comprise a plurality of latches 102A-D that may be used to maintain one of two states of a particular bit in a transmitted data packet. Latches 102A-D may collectively or individually be referred to as latches 102 or latch 102. For example, if the bits 1011 were transmitted on bus 101, then latch 102A may maintain the state, e.g., binary value of 1, for the least significant bit. Latch102B may maintain the state, e.g., binary value of 1, for the bit adjacent to the least significant bit. Latch 102C may maintain the state, e.g., binary value of 0, for the bit second from the least significant bit. Latch 102D may maintain the state, e.g., binary value of 1, for the most significant bit. Exclusive-OR (XOR) gates 103A-D may each be connected to an input and an output of a corresponding latch 102A-D, respectively, in order to capture the present value and the past value of a particular bit. XOR gates 103A-D may collectively or individually be referred to as XOR gates 103 or XOR gate 103, respectively. By capturing the present and past value of a particular bit, XOR gate 103 may determine whether the value for that bit position changed in value from a first data transfer to a second data transfer. XOR gate 103 may logically output a "1" when the inputs to XOR gate 103 differ in state. Hence, when the value for a bit position changes, e.g., 0 to binary value of 1, then the corresponding XOR gate 103 may output a "1." When the value for a bit position does not change state, then the corresponding XOR gate 103 may output a "0."

Hamming distance comparator 100 may further comprise a CTL gate 110. CTL gate 110 may comprise CTL switches 104A-D coupled to XOR gates103A-D, respectively. CTL switches 104A-D may collectively or individually be referred to as CTL switches 104 or CTL switch 104, respectively. CTL gate 110 may further comprise capacitors 105A-D coupled to CTL switches 104A-D, respectively. Capacitors 105A-D may collectively or individually be referred to as capacitors 105 or CTL capacitor 105, respectively. CTL gate 110 may further comprise a CTL comparator 107 coupled to each CTL capacitor 105A-D via a common line 106. CTL comparator 107 may be configured to change the state of the inversion bit used to indicate whether or not to transmit the complemented bit values in the received data packet based on the voltage level of common line 106. If the voltage level of common line 106 exceeds a threshold voltage established by CTL comparator 107, then CTL comparator 107 may be configured to change the state of the inversion bit to indicate to transmit the complemented bit values in the received data packet. If the voltage level of common line 106 falls below the threshold voltage established by CTL comparator 107, then CTL comparator 107 may be configured to not change the state of the inversion bit to indicate to transmit the true bit values in the received data packet. CTL gate 110 may further comprise a threshold column 108 coupled to common line106. Threshold column 108 may be configured to adjust or shift the threshold voltage level, e.g., decrease threshold voltage level, established by CTL comparator 107 during a reset state. The amount of the adjustment or shift of the threshold voltage level may determine the number of CTL capacitors105 that have to be charged up in order to activate CTL comparator 107 as described below.

Hamming distance comparator 100 may operate in two states commonly referred to as a reset state and an evaluation state. During the reset state, each CTL capacitor 105 may be discharged while a value of a bit on bus 101 is latched by the appropriate latch 102. During the evaluation state, CTL switch 104 may be configured to pass the value outputted by the associated XOR gate 103 to the associated CTL capacitor 105. As stated above, XOR gate 103 may logically output a "1" when the inputs to XOR gate 103 differ in state. Hence, when the value for a bit position changes, e.g., 0 to binary value of 1, then the corresponding XOR gate 103 may output a "1." When the value for a bit position does not change state, then the corresponding XOR gate 103 may output a "0." Upon CTL switch 104 passing the value outputted by the associated XOR gate 103 to the associated CTL capacitor 105, CTL capacitor 105 may charge up if the corresponding XOR gate 103 outputted a "1." When CTL capacitor 105 charges up, the voltage of common line 106 increases. If XOR gate 103 outputs a "0", then the associated CTL switch 104 passes a "0" to the associated CTL capacitor 105 thereby remaining discharged and not increasing the voltage of common line 106.

If the voltage level of common line 106 increases to above a predetermined threshold level, then CTL comparator 107 may change the state of the inversion bit to indicate to transmit the complemented bit values in the received data packet. In other words, if the number of bits that changed state in two consecutively transmitted data packets, i.e., the hamming distance, is greater than a certain number, then CTL comparator 107 may change the state of the inversion bit to indicate to transmit the complemented bit values in the received data packet. If the voltage level of common line 106 did not increase to above a predetermined threshold level, then CTL comparator 107 may not change the state of the inversion bit and hence indicate to send the true values in the received data packet. In other words, if the number of bits that changed state in two consecutively transmitted data packets, i.e., the hamming distance, is not greater than a certain number, then CTL comparator 107 may not change the state of the inversion bit and hence indicate to send the true values in the received data packet.

While the above hamming distance comparator implements hamming distance comparison to perform bus inversion, the hamming distance comparator comprises several levels of logic including latches and XOR gates. By having several levels of logic including latches and XOR gates, the complexity of the hamming distance comparator increases which increases costs and decreases performance.

It would therefore be desirable to perform hamming distance comparison without implementing explicit latches or Exclusive Or (XOR) gates using capacitive threshold logic.

SUMMARY

The problems outlined above may at least in part be solved in some embodiments by having each evaluation circuit in a hamming distance comparator be configured to evaluate a particular bit in a data packet received by the hamming distance comparator. Each evaluation circuit may comprise a first and a second capacitor configured to store a true and a complement value of the bit evaluated during a reset state. During an evaluation state, one of the first or second capacitors may be switched if the state of the bit evaluated in the received data packet changed in a second subsequent received data packet. By switching one of the first or second capacitors, a net change in potential may be provided on a common line coupled to the first and second capacitors. If the state of the bit evaluated in the received data packet did not change state in a second subsequent received data packet, then there is no switching of the first and second capacitors. When there is no switching of the first and second capacitors, there is not a net change in potential provided on the common line. If enough of the evaluation circuits produce a net change in the voltage of the common line so that the voltage of the common line shifts across a threshold voltage, then a Capacitor Threshold Logic (CTL) comparator may be asserted. That is, if the hamming distance which may refer to the number of bits that changed state in two consecutive data packets received by the hamming distance comparator is greater than a particular number, then the CTL comparator may be asserted.

In one embodiment of the present invention, a method for performing hamming distance comparison may comprise the step of a hamming distance comparator receiving a first packet of data comprising a plurality of bits of data, e.g., binary values of 11100. The hamming distance comparator may comprise a plurality of evaluation circuits where each evaluation circuit may be configured to evaluate a particular bit in a particular bit position in the data packet received by the hamming distance comparator. Each evaluation circuit may comprise a first and a second capacitor. During a reset state, a first value may be stored at the first capacitor and a second value may be stored at the second capacitor where the second value is a complement of the first value. For example, if the evaluation circuit received a "0", then a "0" may be stored at the first capacitor and a "binary value of 1" may be stored at the second capacitor during the reset state. If the evaluation circuit received a "binary value of 1", then a "binary value of 1" may be stored at the first capacitor and a "0" may be stored at the second capacitor during the reset state.

The hamming distance comparator may then receive a second packet of data comprising a plurality of bits of data, e.g., binary values of 00000. As stated above, each evaluation circuit may evaluate a particular bit in a particular bit position in the data packet received by the hamming distance comparator.

A determination may then be made by the evaluation circuit as to whether the value at the bit evaluated in the second data packet differs with the first value where the bit evaluated in the second data packet corresponds to the same bit position as the bit in the first data packet with the first value. That is, a determination may be made by the evaluation circuit as to whether the bit evaluated in the first data packet changed state with respect to the bit in the same bit position in the second data packet received by the hamming distance comparator.

If the bit evaluated in the first data packet changed state with respect to the state of the bit in the same bit position in the second data packet received by the hamming distance comparator, then one of the first or second capacitors may switch thereby producing a net change, e.g., increase or decrease, in potential on a common line coupled to the first and second capacitors.

If the bit evaluated in the first data packet did not change state with respect to the state of the bit in the same bit position in the second data packet received by the hamming distance comparator, then one of the first or second capacitors may not switch thereby not producing a net change, e.g., increase or decrease, in potential on the common line.

Upon each evaluation circuit evaluating whether a bit in the first data packet changed state with respect to the bit in the same bit position in the second data packet received by the hamming distance comparator, a determination may be made as to whether there is a net change in potential on the common line that shifts across, e.g., exceeds or falls below, a threshold. That is, a determination may be made as to whether the hamming distance, i.e., the number of non-matching bits in two consecutively received data packets, exceeds a particular number.

If there is a net change in potential on the common line that shifts across a threshold, then a comparator is activated. If there is not a net change in potential on the common line that shifts across a threshold, then the comparator is not activated.

DETAILED DESCRIPTION

Although the present invention is described with reference to specific embodiments of a hamming distance comparator performing hamming distance comparison to implement bus inversion, it is noted that the hamming distance comparator of the present invention may perform hamming distance comparison used in other applications, e.g., image processing. It is further noted that a person of ordinary skill in the art would be capable of implementing the hamming distance comparator of the present invention to perform hamming distance comparison in other applications, e.g., image processing. It is further noted that embodiments implementing the hamming distance comparator of the present invention to perform hamming distance comparison in other applications, e.g., image processing, would fall within the scope of the present invention.

FIG. 2—Processor System

      may alternatively be implemented as a bifurcated instruction and data cache.

            and preferably has a storage capacity equal to or greater than L2 cache 204.

          associated with any levels of cache. It is further noted that FIG. 2 is illustrative and is not meant to imply architectural limitations.

 is described further below in conjunction with FIGS. 3-5.

Furthermore, as stated in the Background Information section, the hamming distance comparator as illustrated in FIG. 1, implementing hamming distance comparison to perform bus inversion, comprises several levels of logic including latches and XOR gates. By having several levels of logic including latches and XOR gates, the complexity of the hamming distance comparator increases which increases costs and decreases performance. It would therefore be desirable to perform hamming distance comparison without implementing explicit latches or Exclusive Or (XOR) gates using capacitive threshold logic. An embodiment of a system using a hamming distance comparator to perform hamming distance comparison without implementing explicit latches or XOR gates is described below in conjunction with FIGS. 3-5. It is noted that even though the following discusses using the hamming distance comparator of the present invention to perform hamming distance comparison to implement bus inversion that the hamming distance comparator of the present invention may perform hamming distance comparison to be used in other applications, e.g., image processing. It is further noted that a person of ordinary skill in the art would be capable of applying the principles of the present invention of performing hamming distance comparison using the hamming distance comparator of the present invention in other applications, e.g., image processing.

FIG. 3—System for Implementing Bus Inversion

                  (FIG. 2). It is noted that those of ordinary skill in the art will appreciate that different elements in FIG. 3 may be used to implement bus inversion. It is further noted that FIG. 3 is illustrative and not meant to imply any architectural limitations.

         via a driver (not shown) in the output buffer (not shown) of latch 304.

FIG. 4—Hamming Distance Comparator

              during the reset state.

     determining whether the state of a bit in a particular bit position changed state with respect to the state of the bit in the same bit position in the previously received data packet is provided further below in conjunction with FIG. 5.

               thereby not toggling the state of its output used as an inversion bit.

FIG. 5—Evaluation Circuit

  changed state with respect to the state of the bit in the same bit position in a previously received data packet.

   received the bits 11100 in a data packet, then bit "1" in the most significant bit position may be received by evaluation circuit 401A. Bit "1" in the second to the most significant bit position may be received by evaluation circuit 401B. Bit "1" in the third to the most significant bit position may be received by evaluation circuit 401C. Bit "0" in the second to the least significant bit position may be received by evaluation circuit 401D and so forth.

          substantially concurrently, the state of the input data bit may be maintained during the reset phase as explained in greater detail further below.

                     to indicate if a bit evaluated had changed state. It is further noted that it would be understood to a person of ordinary skill in the art that alternative embodiments implementing other combinations of logic circuitry such as transmission gates, inverters, full keepers, transistors, etc., in addition to the two CTL capacitor 519, 520, may be used to perform the functions representative of the present inventive principles. It is further noted that embodiments implementing such combinations of logic would fall within the scope of the present invention.

      and transistors 511, 512.

         is charged up to a potential substantially equal to VDD.

         of CTL capacitor 520approaches zero.

    of CTL capacitor 520.

    to node 524.

    was substantially VDD, then the following may occur during the evaluation state.

            evaluating that particular bit position.

              evaluating that particular bit position.

   of CTL capacitor520 was substantially zero, then the following may occur during the evaluation state.

            evaluating that particular bit position.

             evaluating that particular bit position.

       when the state of a bit in a particular bit position changes state would fall within the scope of the present invention.

FIG. 6—Method for Producing a Net Change in Potential on a Common Line

   (FIG. 4) if a bit changed state with respect to the state of the bit in a previously received data packet thereby enabling hamming distance comparison to be performed as described in FIG. 7.

       changed state.

        during the reset state.

    received the bits 00000 in a data packet, then bit "0" in the most significant bit position may be received by evaluation circuit 401A. Bit "0" in the second to the most significant bit position may be received by evaluation circuit 401B. Bit "0" in the third to the most significant bit position maybe received by evaluation circuit 401C and so forth.

  as to whether the bit evaluated in the first data packet changed state with respect to the bit in the same bit position in the second data packet received by hamming distance comparator 301.

  as described above.

  as described above.

 evaluating whether a bit in the first data packet changed state with respect to the bit in the same bit position in the second data packet received by hamming distance comparator 301, a hamming distance comparison may be performed as described below.

 may be executed in a different order presented and that the order presented in the discussion of FIG. 6 is illustrative. It is further noted that certain steps in FIG. 6 may be executed almost concurrently.

FIG. 7—Method for Performing Hamming Distance Comparison

 for performing hamming distance comparison to implement bus inversion. It is noted that hamming distance comparison of the present invention may be implemented in other applications, e.g., image processing. It is further noted that embodiments performing hamming distance comparison of the present invention in other applications, e.g., image processing, would fall within the scope of the present invention.

  that shifts across, e.g., exceeds or falls below, a threshold. That is, a determination may be made as to whether the hamming distance, i.e., the number of non-matching bits in two consecutively received data packets, exceeds a particular number.

   instead of the values received for each of the bits of the second data packet, e.g., binary values of 00000, since the hamming distance exceeded a particular number as described above. If the first data packet comprised the binary values of 11100, then by transmitting the complement binary values of 11111 instead of the true binary values of 00000 only two switches may be switched instead of three. Hence, switching activity may be minimized at least in part by transmitting the complement values of the received data bits instead of the true value of the data bits when the hamming distance exceeds a particular number.

   instead of the complement values for each of the bits of the second data packet since the hamming distance did not exceed a particular number as described above. If the first data packet comprised the binary values of 11100, then by transmitting the true binary values of 11111 instead of the complement binary values of 00000 only two switches may be switched instead of three. Hence, switching activity may be minimized at least in part by transmitting the true values of the received data bits instead of the complement value of the data bits when the hamming distance does not exceed a particular number.

 may be executed in a different order presented and that the order presented in the discussion of FIG. 7 is illustrative. It is further noted that certain steps in FIG. 7 may be executed almost concurrently.

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