基于FPGA的VGA显示设计（一）
前言
FPGA主要运用于芯片验证、通信、图像处理。显示VGA接口的显示器是最基本的要求了。
原理
首先需要了解 ：
（1）VGA接口协议：VGA端子_维基百科 、VGA视频传输标准_百度
| 引脚1 | RED | 红色视频 | |
|---|---|---|---|
| 引脚2 | GREEN | 绿色视频 | |
| 引脚3 | BLUE | 蓝色视频 | |
| 引脚4 | ID2/RES | 过去为屏幕ID比特2；自DDC2起保留 | |
| 引脚5 | GND | 接地（水平同步） | |
| 引脚6 | RED_RTN | 红色接回 | |
| 引脚7 | GREEN_RTN | 绿色接回 | |
| 引脚8 | BLUE_RTN | 蓝色接回 | |
| 引脚9 | KEY/PWR | 过去为key；现为 +5V DC | |
| 引脚10 | GND | 接地（垂直同步，DDC） | |
| 引脚11 | ID0/RES | 过去为屏幕ID比特0；自E-DDC起保留 | |
| 引脚12 | ID1/SDA | 过去为屏幕ID比特1；自DDC2起为I²C数据 | |
| 引脚13 | HSync | 水平同步 | |
| 引脚14 | VSync | 垂直同步 | |
| 引脚15 | ID3/SCL | 过去为屏幕ID比特3；自DDC2起为I²C时钟 | |
| 图表中详叙了较新的15针VESA DDC2连接头。图标中的针脚编号是显卡常见的母接头；在公接头上的针脚相当于图例的左右镜像。 | |||
最主要的几根线：
（2）VGA时序
各种分辨率的显示器时序参数：http://tinyvga.com/vga-timing
a、扫描轨迹
扫描从屏幕左上方开始，从左至右，从上到下，进行扫描。
每扫描完一行，电子束（CRT）回到屏幕的左边下一行起始位置，在此期间对电子束进行消隐，每行结束时，用行同步信号进行同步。
扫描完所有行，用场同步信号进行场同步，并使扫描回到屏幕的左上方，同时进行消隐，预备下一行的扫描。
b、行场扫描（工业标准为负，大部分显示器HS、VS可正可负，显示器自动调整，此处为正极性）
c、HS时序深入分析
可见时序的循环，可被划分为a，b，c，d4个时期。这四个时期定义如下：
A~B：行消隐期 即同步，相当于还原扫描坐标吧
B~C：行消隐后肩 相当于准备开始扫描吧
C~D：行显示期 扫描中，数据有效区域
D~E：行消隐前肩 完成扫描，相当于准备同步
d、VS时序深入分析
可见时序的循环，可被划分为a，b，c，d4个时期。这四个时期定义如下：
A~B：场消隐期 即同步，相当于还原扫描坐标吧
B~C：场消隐后肩 相当于准备开始扫描吧
C~D：场显示期 扫描中，数据有效区域
D~E：场消隐前肩 完成扫描，相当于准备同步
综上描述，我们只要知道每个时期的时间，便可以表示出VGA的时序。而FPGA的工作是由固定频率的时钟触发的，因此某固定时间可以用n次触发来表示。因此我们很容易就想到了FPGA常用的计数方法：比如说行扫描，我们计数0~H_total-1。用另一个进程将其划分为4个时期，按标注分配。其实这相当于状态机。
以下是固定分辨率1280*1024 60fps下HS,VS的标准：
有图可得：
①各个时期像素数：
// Horizontal Parameter( Pixel )
H_DISP = 11'd1280,
H_FRONT = 11'd48,
H_SYNC = 11'd112,
H_BACK = 11'd248,
H_TOTAL = 11'd1688,
// Virtical Parameter( Line )
V_DISP = 11'd1024,
V_FRONT = 11'd1,
V_SYNC = 11'd3,
V_BACK = 11'd38,
V_TOTAL = 11'd1066;
②像素时钟频率（即所需的VGA时钟频率）
（H_DISP + H_BACK + H_SYNC + H_FRONT）×（V_DISP + V_BACK + V_SYNC + V_FRONT）× REFRESH_RATE
在此为（1280 + 248 + 112 + 48）×（1024 + 38 + 3 + 1）× 60 = 1688 × 1066 × 60 = 107.964480 MHz （工业标准为 108.000 MHz ，当然都是能正常显示的，推荐用工业标准。）
③一帧图像的数据量（以RGB565 格式为例）
H_DISP × V_DISP × （5 + 6 + 5）bit = [H_DISP × V_DISP × （5 + 6 + 5）bit ] ÷ 8 B = [H_DISP × V_DISP × （5 + 6 + 5）bit ] ÷ 8 ÷ 1024 K
在此为 1280 × 1024 × 16 bit = 20971520 ÷ 8 B = 2621440 ÷ 1024 K = 2560 ÷ 1024 M = 2.5 M
（3）三基色原理
常见的彩色显示器一般都是由CRT (阴极射线管) 构成,每一个像素的色彩由R ( 红, Red) 、G( 绿,Green) 、B(蓝,Blue) 三基色构成。显示时采用的是逐行扫描的方式。由VGA 显示模块产生的水平同步信号和垂直同步信号控制阴极射线管中的电子枪产生电子束,轰击涂有荧光粉的屏幕,产生RGB 三基色,于显示屏上合成一个彩色像素点。
像素是产生各种颜色的基本单元。根据物理学中的混色原理，三色发光的亮度比例适当，可呈现白色。适当的调整发光比例可以出现不同的颜色。
程序设计
显示模块（顶层）：
/************************************************************************
* Author : yllinux 博客：http://www.cnblogs.com/yllinux/
* Module Name : vga_color_line.v
* Tool versions : Quartus II 12.1；Cyclone IV E（EP4CE6F17C8）
* Create Date : 2017-7-21
* Revision : v1.0
* Description : 使1280*1024@60HZ的VGA显示器显示竖彩条
************************************************************************/ module VGA_color_line (clk, rst_n, hs_vga, vs_vga, r_vga, g_vga, b_vga); input clk, rst_n; //系统时钟和低电平复位
output hs_vga, vs_vga; //行同步hs_vga，场同步vs_vga
output r_vga, g_vga , b_vga; //像素三基色输出R、G、B
reg [:] rgb_vga; //相当于输入信号了
wire clk_vga; //像素时钟 1688 * 1066 * 60 MZ （工业标准 108 MHZ） // VGA_1280_1024_60fps_50MHz
// Horizontal Parameter( Pixel )
parameter
H_DISP = 'd1280,
H_FRONT = 'd48,
H_SYNC = 'd112,
H_BACK = 'd248,
H_TOTAL = 'd1688,
// Virtical Parameter( Line )
V_DISP = 'd1024,
V_FRONT = 'd1,
V_SYNC = 'd3,
V_BACK = 'd38,
V_TOTAL = 'd1066; //调用IP核ALTPLL，像素频率108 MHZ
pll_pixel_clock pll_pixel_clock_inst (
.inclk0 ( clk ),
.c0 ( clk_vga ) //例化端口必须是网线型
); //行同步计数器(信号发生器)
reg [:] hcnt;
reg hs_vga;
always @ (posedge clk_vga or negedge rst_n)
begin
if (!rst_n)
hcnt <= ; //复位后计数清零
else
begin
if (hcnt < H_TOTAL - 'b1) //判断扫描完一行,像素区间为[0, H_TOTAL - 1'b1]
hcnt <= hcnt + 'b1;
else
hcnt <= ;
end
end
//行同步
always @ (posedge clk_vga or negedge rst_n)
begin
if (!rst_n)
hs_vga <= ; //因为复位后计数器置零，而0 ~ (H_DISP - 1)区间为显示区，此处必为 0
else
begin
//像素(H_DISP + H_FRONT - 1, H_DISP + H_FRONT + H_SYNC - 1]区间同步
if (hcnt >= (H_DISP + H_FRONT - 'b1) && hcnt < (H_DISP + H_FRONT + H_SYNC - 1'b1))
hs_vga <= ; //在同步区置1，行同步
else
hs_vga <= ;
end
end //场同步计数器(信号发生器)
reg [:] vcnt;
reg vs_vga;
always @ (posedge clk_vga or negedge rst_n) //异步复位
begin
if (!rst_n)
vcnt <= ; //复位后计数清零
else
begin
if (hcnt == H_DISP - 'b1) //判断显示区扫面完一行，此处也可判断整个一行扫描完
begin
if (vcnt < V_TOTAL - 'b1) //判断扫面完一场
vcnt <= vcnt + 'b1;
else
vcnt <= ;
end
else
vcnt <= vcnt;
end
end
//场同步
always @ (posedge clk_vga or negedge rst_n)
begin
if (!rst_n)
vs_vga <= ;
else
begin
if (vcnt >= (V_DISP + V_FRONT - 'b1) && vcnt < (V_DISP + V_FRONT + V_SYNC - 1'b1))
vs_vga <= ;
else
vs_vga <= ;
end
end //在显示期坐标根据显示的扫描而改变，在非显示期，坐标置零
wire [:] xpos_vga, ypos_vga;
assign xpos_vga = (hcnt < H_DISP) ? (hcnt + 'b1) : 11'd0; //在显示区横坐标 + 1（即1~H_DISP）
assign ypos_vga = (vcnt < V_DISP) ? (vcnt + 'b1) : 11'd0; //在显示区竖坐标 + 1（即1~V_DISP） //竖彩条显示
always @ (posedge clk_vga or negedge rst_n)
if (!rst_n)
rgb_vga <= 'b000;
else
begin
/*if (xpos_vga > 0 && xpos_vga < 80) rgb_vga <= 3'b010;
else if (xpos_vga < 160) rgb_vga <= 3'b011;
else if (xpos_vga < 240) rgb_vga <= 3'b100;
else if (xpos_vga < 320) rgb_vga <= 3'b101;
else if (xpos_vga < 400) rgb_vga <= 3'b110;
else if (xpos_vga < 480) rgb_vga <= 3'b111;
else if (xpos_vga < 560) rgb_vga <= 3'b001;
else if (xpos_vga < 640) rgb_vga <= 3'b010;
else if (xpos_vga < 720) rgb_vga <= 3'b011;
else if (xpos_vga < 800) rgb_vga <= 3'b100;
else if (xpos_vga < 880) rgb_vga <= 3'b101;
else if (xpos_vga < 960) rgb_vga <= 3'b110;
else if (xpos_vga < 1040) rgb_vga <= 3'b111;
else if (xpos_vga < 1120) rgb_vga <= 3'b001;
else if (xpos_vga < 1200) rgb_vga <= 3'b010;
else if (xpos_vga <= 1280) rgb_vga <= 3'b011;
else rgb_vga <= 3'b000;*/ if (xpos_vga > && xpos_vga <= ) rgb_vga <= 'b111;//white
else if (xpos_vga > && xpos_vga <= ) rgb_vga <= 'b100;//red
else if (xpos_vga > && xpos_vga <= ) rgb_vga <= 'b101;//mangenta
else if (xpos_vga > && xpos_vga <= ) rgb_vga <= 'b110;//yellow
else if (xpos_vga > && xpos_vga <= ) rgb_vga <= 'b010;//green
else if (xpos_vga > && xpos_vga <= ) rgb_vga <= 'b001;//blue
else if (xpos_vga > && xpos_vga <= ) rgb_vga <= 'b011;//cyan
else if (xpos_vga > && xpos_vga <= ) rgb_vga <= 'b000; else if (xpos_vga > && xpos_vga <= ) rgb_vga <= 'b111;//white
else if (xpos_vga > && xpos_vga <= ) rgb_vga <= 'b100;
else if (xpos_vga > && xpos_vga <= ) rgb_vga <= 'b101;
else if (xpos_vga > && xpos_vga <= ) rgb_vga <= 'b110;
else if (xpos_vga > && xpos_vga <= ) rgb_vga <= 'b010;
else if (xpos_vga > && xpos_vga <= ) rgb_vga <= 'b001;
else if (xpos_vga > && xpos_vga <= ) rgb_vga <= 'b011;
else if (xpos_vga > && xpos_vga <= ) rgb_vga <= 'b111;
else rgb_vga <= 'b000;//black，这个很重要，不然颜色不怎么正常 end //三基色分离（可省，直接用 rgb_vga）
assign r_vga = rgb_vga[];
assign g_vga = rgb_vga[];
assign b_vga = rgb_vga[]; endmodule
调用的锁相环 IP 核 ALTPLL：
// megafunction wizard: %ALTPLL%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altpll // ============================================================
// File Name: pll_pixel_clock.v
// Megafunction Name(s):
// altpll
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 12.1 Build 177 11/07/2012 SJ Full Version
// ************************************************************ //Copyright (C) 1991-2012 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details. // synopsys translate_off
`timescale ps / ps
// synopsys translate_on
module pll_pixel_clock (
inclk0,
c0); input inclk0;
output c0; wire [:] sub_wire0;
wire [:] sub_wire4 = 'h0;
wire [:] sub_wire1 = sub_wire0[:];
wire c0 = sub_wire1;
wire sub_wire2 = inclk0;
wire [:] sub_wire3 = {sub_wire4, sub_wire2}; altpll altpll_component (
.inclk (sub_wire3),
.clk (sub_wire0),
.activeclock (),
.areset ('b0),
.clkbad (),
.clkena ({{'b1}}),
.clkloss (),
.clkswitch ('b0),
.configupdate ('b0),
.enable0 (),
.enable1 (),
.extclk (),
.extclkena ({{'b1}}),
.fbin ('b1),
.fbmimicbidir (),
.fbout (),
.fref (),
.icdrclk (),
.locked (),
.pfdena ('b1),
.phasecounterselect ({{'b1}}),
.phasedone (),
.phasestep ('b1),
.phaseupdown ('b1),
.pllena ('b1),
.scanaclr ('b0),
.scanclk ('b0),
.scanclkena ('b1),
.scandata ('b0),
.scandataout (),
.scandone (),
.scanread ('b0),
.scanwrite ('b0),
.sclkout0 (),
.sclkout1 (),
.vcooverrange (),
.vcounderrange ());
defparam
altpll_component.bandwidth_type = "AUTO",
altpll_component.clk0_divide_by = ,
altpll_component.clk0_duty_cycle = ,
altpll_component.clk0_multiply_by = ,
altpll_component.clk0_phase_shift = "",
altpll_component.compensate_clock = "CLK0",
altpll_component.inclk0_input_frequency = ,
altpll_component.intended_device_family = "Cyclone IV E",
altpll_component.lpm_hint = "CBX_MODULE_PREFIX=pll_pixel_clock",
altpll_component.lpm_type = "altpll",
altpll_component.operation_mode = "NORMAL",
altpll_component.pll_type = "AUTO",
altpll_component.port_activeclock = "PORT_UNUSED",
altpll_component.port_areset = "PORT_UNUSED",
altpll_component.port_clkbad0 = "PORT_UNUSED",
altpll_component.port_clkbad1 = "PORT_UNUSED",
altpll_component.port_clkloss = "PORT_UNUSED",
altpll_component.port_clkswitch = "PORT_UNUSED",
altpll_component.port_configupdate = "PORT_UNUSED",
altpll_component.port_fbin = "PORT_UNUSED",
altpll_component.port_inclk0 = "PORT_USED",
altpll_component.port_inclk1 = "PORT_UNUSED",
altpll_component.port_locked = "PORT_UNUSED",
altpll_component.port_pfdena = "PORT_UNUSED",
altpll_component.port_phasecounterselect = "PORT_UNUSED",
altpll_component.port_phasedone = "PORT_UNUSED",
altpll_component.port_phasestep = "PORT_UNUSED",
altpll_component.port_phaseupdown = "PORT_UNUSED",
altpll_component.port_pllena = "PORT_UNUSED",
altpll_component.port_scanaclr = "PORT_UNUSED",
altpll_component.port_scanclk = "PORT_UNUSED",
altpll_component.port_scanclkena = "PORT_UNUSED",
altpll_component.port_scandata = "PORT_UNUSED",
altpll_component.port_scandataout = "PORT_UNUSED",
altpll_component.port_scandone = "PORT_UNUSED",
altpll_component.port_scanread = "PORT_UNUSED",
altpll_component.port_scanwrite = "PORT_UNUSED",
altpll_component.port_clk0 = "PORT_USED",
altpll_component.port_clk1 = "PORT_UNUSED",
altpll_component.port_clk2 = "PORT_UNUSED",
altpll_component.port_clk3 = "PORT_UNUSED",
altpll_component.port_clk4 = "PORT_UNUSED",
altpll_component.port_clk5 = "PORT_UNUSED",
altpll_component.port_clkena0 = "PORT_UNUSED",
altpll_component.port_clkena1 = "PORT_UNUSED",
altpll_component.port_clkena2 = "PORT_UNUSED",
altpll_component.port_clkena3 = "PORT_UNUSED",
altpll_component.port_clkena4 = "PORT_UNUSED",
altpll_component.port_clkena5 = "PORT_UNUSED",
altpll_component.port_extclk0 = "PORT_UNUSED",
altpll_component.port_extclk1 = "PORT_UNUSED",
altpll_component.port_extclk2 = "PORT_UNUSED",
altpll_component.port_extclk3 = "PORT_UNUSED",
altpll_component.width_clock = ; endmodule // ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "108.000000"
// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000"
// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "108.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
// Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll_pixel_clock.mif"
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "25"
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "54"
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_pixel_clock.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_pixel_clock.ppf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_pixel_clock.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_pixel_clock.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_pixel_clock.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_pixel_clock_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_pixel_clock_bb.v FALSE
// Retrieval info: LIB_FILE: altera_mf
// Retrieval info: CBX_MODULE_PREFIX: ON
【注】：
①对时序部分代码的编写不论从哪个时期作为判断依据都无所谓，这是一个周期性循环的。后面附另一种判断的写法，其实都一样。
②尽管使用的是LCD而不是CRT，消隐前后期必须保留，若令 H_FRONT、H_BACK、V_FRONT、V_BACK 为零，显示器将不能显示，亲测。
③尽量按照工业标准来写，这样兼容性更强。
RTL:
Technology Map：
Modelsim 仿真
写一个简单的 testbench：
`timescale ns/ ps
module VGA_color_line_vlg_tst();
reg clk;
reg rst_n;
// wires
wire b_vga;
wire g_vga;
wire hs_vga;
wire r_vga;
wire vs_vga; VGA_color_line i1 (
.b_vga(b_vga),
.clk(clk),
.g_vga(g_vga),
.hs_vga(hs_vga),
.r_vga(r_vga),
.rst_n(rst_n),
.vs_vga(vs_vga)
);
initial
begin
clk = ;
end
always
begin
# clk = ~clk;
end
endmodule
仿真波形：
可以看出波形正常。
2017-07-22--------------------------------------------------------------------------------------------------------------↓↓↓
对于VGA时序里 hcnt、xpos_vga、hs_vga 等随时钟变化存疑，故手动仿真如下：
我们假设 H_DISP = 4， H_BACK = 1， H_SYNC = 1， H_FRONT = 1， H_TOTAL = 7。
由此用 quartus ii 9.0 自带仿真工具测试一下：
module VGA_color_line_test (clk, rst, xpos_vga, hcnt, hs_vga);
input clk, rst;
output hcnt, hs_vga;
output [:] xpos_vga; reg [:] hcnt;
reg hs_vga;
wire [:] xpos_vga; parameter
H_DISP = 'd4,
H_FRONT = 'd1,
H_SYNC = 'd1,
H_BACK = 'd1,
H_TOTAL = 'd7; always @(posedge clk or negedge rst) begin
if (!rst)
hs_vga <= ;
else
if (hcnt >= H_DISP + H_FRONT - && hcnt < H_DISP + H_FRONT + H_SYNC - )
hs_vga <= ;
else
hs_vga <= ;
end always @(posedge clk or negedge rst) begin
if (!rst)
hcnt <= ;
else
if (hcnt < H_TOTAL - )
hcnt <= hcnt + ;
else
hcnt <= ;
end assign xpos_vga = (hcnt < H_DISP) ? hcnt : ; endmodule
从仿真波形可以看出手动分析完全正确。则原代码中 105 和 106 行 assign语句中不应该加 1。
（assign xpos_vga = (hcnt < H_DISP) ? hcnt : 11'd0; 即可，ypos_vga同理）
由此能得出在非显示区坐标为 0，那 0 坐标点在非显示期会不会出现异常呢，我把非显示期改为 11'dz 也能正常显示，但是这样好吗？？？ （希望大神们给点提示^_^）
改为11'dz 仿真波形如下：
2017-07-22--------------------------------------------------------------------------------------------------------------↑↑↑
硬件实测
硬件采用：Cyclone IV E（EP4CE6F17C8）
引脚分配：
实际效果：
上面的是比较完善的，下面粘贴第一个版本代码，能显示，稍有瑕疵，程序中有些细节可能有问题，懒得改了，直接粘贴
顶层文件：
module VGA_display_easy (clk, rst_n, hs_vga, vs_vga, r_vga, g_vga, b_vga);
input clk, rst_n;
output hs_vga, vs_vga;
output r_vga, g_vga , b_vga;
reg [:] rgb_vga;
// VGA_1280_1024_60fps_50MHz
// Horizontal Parameter( Pixel )
parameter
H_DISP = 'd1280,
H_FRONT = 'd48,
H_SYNC = 'd112,
H_BACK = 'd248,
H_TOTAL = 'd1688,
// Virtical Parameter( Line )
V_DISP = 'd1024,
V_FRONT = 'd1,
V_SYNC = 'd3,
V_BACK = 'd38,
V_TOTAL = 'd1066;
//PLL
/*pll_vga pll_vga_inst (
.areset ( ~rst_n ),
.inclk0 ( clk ),
.c0 ( clk_vga ),
.locked ( locked_sig )
);*/
ceshi ceshi_inst (
.inclk0 ( clk ),
.c0 ( clk_vga )
);
wire clk_vga;
//行同步信号发生器
reg [:] hcnt;
reg hs_vga;
always @ (posedge clk_vga or negedge rst_n)
begin
if (!rst_n)
hcnt <= ; // hcnt <= 0;
else
begin
if (hcnt <= H_TOTAL ) // if (hcnt < H_TOTAL - 1'b1)
hcnt <= hcnt + 'b1;
else
hcnt <= ; //hcnt <= 0;
end
end
always @ (posedge clk_vga or negedge rst_n)
begin
if (!rst_n)
hs_vga <= ;
else
begin
if (hcnt <= H_SYNC)
hs_vga <= ;
//if ((hcnt >= H_DISP + H_FRONT - 1'b1) && (hcnt < H_DISP + H_FRONT + H_SYNC - 1'b1))
//hs_vga <= 0;
else
hs_vga <= ;
//hs_vga <= 1;
end
end
//场同步信号发生器
reg [:] vcnt;
reg vs_vga;
always @ (posedge clk_vga or negedge rst_n)
begin
if (!rst_n)
vcnt <= ;
else
begin
if (vcnt <= V_TOTAL)
begin
if (hcnt == H_TOTAL)
vcnt <= vcnt + 'b1;
else
vcnt <= vcnt;
end
else
vcnt <= ;
/*if (hcnt == H_DISP - 1)
begin
if (vcnt < V_TOTAL - 1'b1)
vcnt <= vcnt + 1'b1;
else
vcnt <= 0;
end
else
vcnt <= vcnt;*/
end
end
always @ (posedge clk_vga or negedge rst_n)
begin
if (!rst_n)
vs_vga <= ;
else
begin
if (vcnt <= V_SYNC)
//if ((vcnt >= V_DISP + V_FRONT - 1'b1) && (vcnt < V_DISP + V_FRONT + V_SYNC - 1'b1))
vs_vga <= ;
//vs_vga <= 0;
else
vs_vga <= ;
//vs_vga <= 1;
end
end
//显示期坐标，非显示期，坐标置零。
wire [:] xpos_vga, ypos_vga;
assign xpos_vga = (hcnt > H_SYNC + H_BACK && hcnt <= H_SYNC + H_BACK + H_DISP) ? (hcnt - H_SYNC - H_BACK) : 'd0;
assign ypos_vga = (vcnt > V_SYNC + V_BACK && vcnt <= V_SYNC + V_BACK + V_DISP) ? (vcnt - V_SYNC - V_BACK) : 'd0;
//assign xpos_vga = (hcnt < H_DISP) ? (hcnt + 1'b1) : 11'd0;
//assign ypos_vga = (vcnt < V_DISP) ? (vcnt + 1'b1) : 11'd0;
//
always @ (posedge clk_vga or negedge rst_n)
if (!rst_n)
rgb_vga <= 'b000;
else /*if ((xpos_vga >= 200) && (xpos_vga<=220) && (ypos_vga >= 140) && (ypos_vga <= 460))
rgb_vga <= 3'b100;
else if ((xpos_vga >= 580) && (xpos_vga<=600) && (ypos_vga >= 140) && (ypos_vga <= 460))
rgb_vga <= 3'b010;
else if ((xpos_vga >= 220) && (xpos_vga<=580) && (ypos_vga >= 140) && (ypos_vga <= 160))
rgb_vga <= 3'b001;
else if ((xpos_vga >= 220) && (xpos_vga<=580) && (ypos_vga >= 440) && (ypos_vga <= 460))
rgb_vga <= 3'b110;
else rgb_vga <= 3'b000;*/
begin
if (xpos_vga > && xpos_vga <= ) rgb_vga <= 'b111;//white
else if (xpos_vga > && xpos_vga <= ) rgb_vga <= 'b100;//red
else if (xpos_vga > && xpos_vga <= ) rgb_vga <= 'b101;//mangenta
else if (xpos_vga > && xpos_vga <= ) rgb_vga <= 'b110;//yellow
else if (xpos_vga > && xpos_vga <= ) rgb_vga <= 'b010;//green
else if (xpos_vga > && xpos_vga <= ) rgb_vga <= 'b001;//blue
else if (xpos_vga > && xpos_vga <= ) rgb_vga <= 'b011;//cyan
else if (xpos_vga > && xpos_vga <= ) rgb_vga <= 'b000;
else if (xpos_vga > && xpos_vga <= ) rgb_vga <= 'b111;//white
else if (xpos_vga > && xpos_vga <= ) rgb_vga <= 'b100;
else if (xpos_vga > && xpos_vga <= ) rgb_vga <= 'b101;
else if (xpos_vga > && xpos_vga <= ) rgb_vga <= 'b110;
else if (xpos_vga > && xpos_vga <= ) rgb_vga <= 'b010;
else if (xpos_vga > && xpos_vga <= ) rgb_vga <= 'b001;
else if (xpos_vga > && xpos_vga <= ) rgb_vga <= 'b011;
else if (xpos_vga > && xpos_vga <= ) rgb_vga <= 'b111;
else rgb_vga <= 'b000;//black
end
assign r_vga = rgb_vga[];
assign g_vga = rgb_vga[];
assign b_vga = rgb_vga[];
endmodule
pll ：
// megafunction wizard: %ALTPLL%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altpll // ============================================================
// File Name: ceshi.v
// Megafunction Name(s):
// altpll
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 12.1 Build 177 11/07/2012 SJ Full Version
// ************************************************************ //Copyright (C) 1991-2012 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details. // synopsys translate_off
`timescale ps / ps
// synopsys translate_on
module ceshi (
inclk0,
c0); input inclk0;
output c0; wire [:] sub_wire0;
wire [:] sub_wire4 = 'h0;
wire [:] sub_wire1 = sub_wire0[:];
wire c0 = sub_wire1;
wire sub_wire2 = inclk0;
wire [:] sub_wire3 = {sub_wire4, sub_wire2}; altpll altpll_component (
.inclk (sub_wire3),
.clk (sub_wire0),
.activeclock (),
.areset ('b0),
.clkbad (),
.clkena ({{'b1}}),
.clkloss (),
.clkswitch ('b0),
.configupdate ('b0),
.enable0 (),
.enable1 (),
.extclk (),
.extclkena ({{'b1}}),
.fbin ('b1),
.fbmimicbidir (),
.fbout (),
.fref (),
.icdrclk (),
.locked (),
.pfdena ('b1),
.phasecounterselect ({{'b1}}),
.phasedone (),
.phasestep ('b1),
.phaseupdown ('b1),
.pllena ('b1),
.scanaclr ('b0),
.scanclk ('b0),
.scanclkena ('b1),
.scandata ('b0),
.scandataout (),
.scandone (),
.scanread ('b0),
.scanwrite ('b0),
.sclkout0 (),
.sclkout1 (),
.vcooverrange (),
.vcounderrange ());
defparam
altpll_component.bandwidth_type = "AUTO",
altpll_component.clk0_divide_by = ,
altpll_component.clk0_duty_cycle = ,
altpll_component.clk0_multiply_by = ,
altpll_component.clk0_phase_shift = "",
altpll_component.compensate_clock = "CLK0",
altpll_component.inclk0_input_frequency = ,
altpll_component.intended_device_family = "Cyclone IV E",
altpll_component.lpm_hint = "CBX_MODULE_PREFIX=ceshi",
altpll_component.lpm_type = "altpll",
altpll_component.operation_mode = "NORMAL",
altpll_component.pll_type = "AUTO",
altpll_component.port_activeclock = "PORT_UNUSED",
altpll_component.port_areset = "PORT_UNUSED",
altpll_component.port_clkbad0 = "PORT_UNUSED",
altpll_component.port_clkbad1 = "PORT_UNUSED",
altpll_component.port_clkloss = "PORT_UNUSED",
altpll_component.port_clkswitch = "PORT_UNUSED",
altpll_component.port_configupdate = "PORT_UNUSED",
altpll_component.port_fbin = "PORT_UNUSED",
altpll_component.port_inclk0 = "PORT_USED",
altpll_component.port_inclk1 = "PORT_UNUSED",
altpll_component.port_locked = "PORT_UNUSED",
altpll_component.port_pfdena = "PORT_UNUSED",
altpll_component.port_phasecounterselect = "PORT_UNUSED",
altpll_component.port_phasedone = "PORT_UNUSED",
altpll_component.port_phasestep = "PORT_UNUSED",
altpll_component.port_phaseupdown = "PORT_UNUSED",
altpll_component.port_pllena = "PORT_UNUSED",
altpll_component.port_scanaclr = "PORT_UNUSED",
altpll_component.port_scanclk = "PORT_UNUSED",
altpll_component.port_scanclkena = "PORT_UNUSED",
altpll_component.port_scandata = "PORT_UNUSED",
altpll_component.port_scandataout = "PORT_UNUSED",
altpll_component.port_scandone = "PORT_UNUSED",
altpll_component.port_scanread = "PORT_UNUSED",
altpll_component.port_scanwrite = "PORT_UNUSED",
altpll_component.port_clk0 = "PORT_USED",
altpll_component.port_clk1 = "PORT_UNUSED",
altpll_component.port_clk2 = "PORT_UNUSED",
altpll_component.port_clk3 = "PORT_UNUSED",
altpll_component.port_clk4 = "PORT_UNUSED",
altpll_component.port_clk5 = "PORT_UNUSED",
altpll_component.port_clkena0 = "PORT_UNUSED",
altpll_component.port_clkena1 = "PORT_UNUSED",
altpll_component.port_clkena2 = "PORT_UNUSED",
altpll_component.port_clkena3 = "PORT_UNUSED",
altpll_component.port_clkena4 = "PORT_UNUSED",
altpll_component.port_clkena5 = "PORT_UNUSED",
altpll_component.port_extclk0 = "PORT_UNUSED",
altpll_component.port_extclk1 = "PORT_UNUSED",
altpll_component.port_extclk2 = "PORT_UNUSED",
altpll_component.port_extclk3 = "PORT_UNUSED",
altpll_component.width_clock = ; endmodule // ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "107.964478"
// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000"
// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "107.96448000"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
// Retrieval info: PRIVATE: RECONFIG_FILE STRING "ceshi.mif"
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "156250"
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "337389"
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
// Retrieval info: GEN_FILE: TYPE_NORMAL ceshi.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL ceshi.ppf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL ceshi.inc TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL ceshi.cmp TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL ceshi.bsf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL ceshi_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL ceshi_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
// Retrieval info: CBX_MODULE_PREFIX: ON
testbench：
// Copyright (C) 1991-2012 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License
// Subscription Agreement, Altera MegaCore Function License
// Agreement, or other applicable license agreement, including,
// without limitation, that your use is for the sole purpose of
// programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the
// applicable agreement for further details. // *****************************************************************************
// This file contains a Verilog test bench template that is freely editable to
// suit user's needs .Comments are provided in each section to help the user
// fill out necessary details.
// *****************************************************************************
// Generated on "07/19/2017 19:00:02" // Verilog Test Bench template for design : VGA_display_easy
//
// Simulation tool : ModelSim (Verilog)
// `timescale ns/ ps
module VGA_display_easy_vlg_tst();
// constants
// general purpose registers reg clk;
reg rst_n;
// wires
wire b_vga;
wire clk_vga;
wire g_vga;
wire hs_vga;
wire r_vga;
wire vs_vga; // assign statements (if any)
VGA_display_easy i1 (
// port map - connection between master ports and signals/registers
.b_vga(b_vga),
.clk(clk),
.clk_vga(clk_vga),
.g_vga(g_vga),
.hs_vga(hs_vga),
.r_vga(r_vga),
.rst_n(rst_n),
.vs_vga(vs_vga)
);
initial
begin
clk = ;
end
always
begin
# clk = ~clk;
end
endmodule
未完待续。。。
参考：
Crazy Bingo：http://www.cnblogs.com/crazybingo/archive/2011/02/24/1963652.html
《EDA技术实用教程--Verilog HDL版（第四版）》---- 潘松、黄继业、潘明 编著
如有错误还请指出，如有侵权还请告知，如需转载请注明出处！
本人博客：http://www.cnblogs.com/yllinux/
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