FPGA中分数分频器的实现代码

module clkFracDiv(
                  output reg   clkout,
                  input        rstn,
                  input        refclk,
                  input [:] fenzi,
                  input [:] fenmu
);
   reg [:]                   rstn_syn;
   reg [:]                  cnt;

   always @(posedge refclk) begin
      rstn_syn[] <= rstn;
      rstn_syn[] <= rstn_syn[];
      rstn_syn[] <= rstn_syn[];
   end

   //1. main algorithm
   always @(posedge refclk or negedge rstn_syn[]) begin
      if(!rstn_syn[]) cnt <= ;
      else begin
         if(cnt < fenzi) cnt <= cnt + fenmu;
         else cnt <= cnt + fenmu - fenzi;
      end
   end

   always @(posedge refclk or negedge rstn_syn[]) begin
      if(!rstn_syn[]) clkout <= ;
      else begin
         if( ((cnt > (fenzi>>)) || (cnt == (fenzi>>)) ) && (cnt < fenzi)) clkout <= ;
         else clkout <= ;
      end
   end

endmodule

`timescale 1ns/10ps
module tb_top;
   reg refclk;
   initial begin
      refclk = ;
   end
   always #0.2 refclk = !refclk;

   reg rstn;
   initial begin
      rstn = ;
      #;
      rstn = ;
   end

   reg [:] fenzi;
   reg [:] fenmu;
   reg        enable_clkFracDiv;
   initial begin
      fenzi='d13;
      fenmu='d3;
      enable_clkFracDiv=;
      #;
      enable_clkFracDiv=;
   end

   clkFracDiv clkFracDiv(
                         /*output reg   */.clkout (clkout),
                         /*input        */.rstn   (rstn && enable_clkFracDiv ),
                         /*input        */.refclk (refclk),
                         /*input [31:0] */.fenzi  (fenzi ),//fenzi/fenmu must equal or more than 2
                         /*input [31:0] */.fenmu  (fenmu ) //fenzi/fenmu must equal or more than 2
                         );
endmodule