开发环境：win10 64位 + VMware12 + Ubuntu14.04 32位

工具链：linaro提供的gcc-linaro-6.1.1-2016.08-x86_64_arm-linux-gnueabi

要移植的u-boot版本：u-boot-2016-11

Tiny4412开发板硬件版本为：

底板： Tiny4412SDK 1312B

核心板：Tiny4412 - 1306

1、时钟体系

exynos4412芯片时钟体系的介绍在《Exynos 4412 SCP_Users Manual_Ver.0.10.00_Preliminary.pdf》的第七章节。

据P447介绍：其有三个时钟源：

XRTCXTI：32.768KZH，用于RTC时钟的实时时钟源。有XRTCXTI、XRTCXTO两个引脚，且之间需要10mΩ的并联电阻
XXTI：12MHZ--50MZH，APLL、MPLL、VPLL和EPLL可使用此时钟作为适当模块的电源。可以仅用于测试，不用时接地
XUSBXTI：24MZH。因为IROM设计基于24兆赫输入时钟。有XUSBXTI、XUSBXTO两个引脚，且之间需要5mΩ的并联电阻

在友善之臂tiny4412的开发板中， XRTCXTI 上没有外接晶振，系统时钟来源是XUSBXTI引脚上接的24MH 晶振，如下图所示：

2、启动方式

　由P455页可看出XOM[０]接在FIN_PLL上，在结合第五章节内容

OM[5:1]	启动设备
5b’00010	SDMMC_CH2
5b’00100	eMMC44_CH4

可看出ＯＭ[０]＝１;ＯＭ[１]＝０;ＯＭ[４]＝０;ＯＭ[５]＝０;

ＯＭ[２]＝１，ＯＭ[３]＝０时，为SD卡启动；

ＯＭ[２]＝０，ＯＭ[３]＝１时，为ｅMMC启动；

而正是由于ＯＭ[１]＝１；表明芯片选择XUSBXTI为时钟源

3、时钟代码

diff --git a/arch/arm/mach-exynos/Makefile b/arch/arm/mach-exynos/Makefile
index 5f8b6ba..
--- a/arch/arm/mach-exynos/Makefile
+++ b/arch/arm/mach-exynos/Makefile
@@ -, +, @@ ifdef CONFIG_SPL_BUILD
 obj-$(CONFIG_EXYNOS5)  += clock_init_exynos5.o
 obj-$(CONFIG_EXYNOS5)  += dmc_common.o dmc_init_ddr3.o
 obj-$(CONFIG_EXYNOS4210)+= dmc_init_exynos4.o clock_init_exynos4.o
-obj-$(CONFIG_EXYNOS4412)+= dmc_init_exynos4.o clock_init_exynos4.o
+obj-$(CONFIG_EXYNOS4412)+= dmc_init_exynos4412.o clock_init_exynos4412.o
 
 obj-y  += spl_boot.o tzpc.o
 obj-y  += lowlevel_init.o

在mach-exynos下，新建clock_init_exynos4412.c和exynos4412_setup.h

clock
/*
 * Clock Initialization for board based on EXYNOS4412
 *
 *                 2016
 * Modified by AP0904225 <ap0904225@qq.com>
 *
 * Copyright (C) 2013 Samsung Electronics
 * Rajeshwari Shinde <rajeshwari.s@samsung.com>
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */
 
#include <common.h>
#include <config.h>
#include <asm/io.h>
#include <asm/arch/cpu.h>
#include <asm/arch/clk.h>
#include <asm/arch/clock.h>
#include "common_setup.h"
 
#include "exynos4412_setup.h"
 
/*
 * system_clock_init: Initialize core clock and bus clock.
 * void system_clock_init(void)
 */
void system_clock_init(void)
{
   unsigned int set, clr, clr_src_cpu, clr_pll_con0, clr_src_dmc;
   struct exynos4x12_clock *clk =(struct exynos4x12_clock *)
                       samsung_get_base_clock();
 
   /*
   *   APLL= 1400 MHz
   *   MPLL=800 MHz
   *   EPLL=96 MHz
   *   VPLL=108 MHz
   *   freq (ARMCLK) = 1400 MHz at 1.3 V
   *   freq (ACLK_COREM0) = 350 MHz at 1.3V
   *   freq (ACLK_COREM1) = 188 MHz at 1.3 V
   *   freq (PERIPHCLK) = 1400 MHz at 1.3 V
   *   freq (ATCLK) = 214 MHz at 1.3 V
   *   freq (PCLK_DBG) = 107 MHz at 1.3 V
   *   freq (SCLK_DMC) = 400 MHz at 1.0 V
   *   freq (ACLK_DMCD) = 200 MHz at 1.0 V
   *   freq (ACLK_DMCP) = 100 MHz at 1.0 V
   *   freq (ACLK_ACP) = 200 MHz at 1.0 V
   *   freq (PCLK_ACP) = 100 MHz at 1.0 V
   *   freq (SCLK_C2C) = 400 MHz at 1.0 V
   *   freq (ACLK_C2C) = 200 MHz at 1.0 V
   *   freq (ACLK_GDL) = 200 MHz at 1.0 V
   *   freq (ACLK_GPL) = 100 MHz at 1.0 V
   *   freq (ACLK_GDR) = 200 MHz at 1.0 V
   *   freq (ACLK_GPR) = 100 MHz at 1.0 V
   *   freq (ACLK_400_MCUISP) = 400 MHz at 1.0 V
   *   freq (ACLK_200) = 160 MHz at 1.0 V
   *   freq (ACLK_100) = 100 MHz at 1.0 V
   *   freq (ACLK_160) = 160 MHz at 1.0 V
   *   freq (ACLK_133) = 133 MHz at 1.0 V
   *   freq (SCLK_ONENAND) = 160 MHz at 1.0 V
   */
 
   /*
    *before set system clocks,we switch system clocks src to FINpll
   */
 
       /*
        * Bit values:             0      ;    1
        * MUX_APLL_SEL:        FIN_PLL   ; FOUT_APLL
        * MUX_CORE_SEL:        MOUT_APLL ; SCLK_MPLL
        * MUX_HPM_SEL:         MOUT_APLL ; SCLK_MPLL_USER_C
        * MUX_MPLL_USER_SEL_C: FIN_PLL   ; SCLK_MPLL
       */
   clr_src_cpu = MUX_APLL_SEL() | MUX_CORE_SEL() |
             MUX_HPM_SEL() | MUX_MPLL_USER_SEL_C();
   set = MUX_APLL_SEL() | MUX_CORE_SEL() | MUX_HPM_SEL() |
         MUX_MPLL_USER_SEL_C();
   clrsetbits_le32(&clk->src_cpu, clr_src_cpu, set);
   /* Wait for mux change */
   while (readl(&clk->mux_stat_cpu) & MUX_STAT_CPU_CHANGING)
       continue;
 
   /*
   ******************************************************
   *           Step 1: Set Clock divider
   ******************************************************
   */
 
   /*=====================set APLL related dividers(CMU_CPU)==============================*/
       /*
        * Set dividers for MOUTcore
        * MOUTcore     =   MOUTapll = 1400 MHz
        * SCLKapll     =   MOUTapll / (APLL_RATIO  1) = 700 MHz (DIVapll:APLL_RATIO=1)
        * ARMCLK       =   MOUTcore / (ratio  1) = 1400 MHz (DIVcore:CORE_RATIO=0;DIVcore2:CORE2_RATIO=0)
        * ACLK_COREM0  =   ARMCLK / (COREM0_RATIO  1) = 355 MHz (DIVcorem0:COREM0_RATIO=3)
        * ACLK_COREM1  =   ARMCLK / (COREM1_RATIO  1) = 188 MHz (DIVcorem1:COREM1_RATIO=7)
        * PERIPHCLK    =   ARMCLK / (PERIPH_RATIO  1) = 1400 MHz (DIVperiph:PERIPH_RATIO=0)
        * OUTatb       =   MOUTcore / (ATB_RATIO  1) = 200 MHz (DIVatb:ATB_RATIO=6)
        * ATCLK        =   OUTatb = 200 MHz
        * PCLK_DBG     = OUTatb / (PCLK_DBG_RATIO  1) = 100 MHz (PCLK_DBG_RATIO=1)
       */
   clr = APLL_RATIO() |CORE_RATIO()| CORE2_RATIO()|
           COREM0_RATIO() | COREM1_RATIO() |
         PERIPH_RATIO() | ATB_RATIO() | PCLK_DBG_RATIO() ;
   set = APLL_RATIO() |CORE_RATIO() | CORE2_RATIO() |
           COREM0_RATIO() | COREM1_RATIO()|
         PERIPH_RATIO() | ATB_RATIO() | PCLK_DBG_RATIO() ;
   clrsetbits_le32(&clk->div_cpu0, clr, set);
 
   /* Wait for divider ready status */
   while (readl(&clk->div_stat_cpu0) & DIV_STAT_CPU0_CHANGING)
       continue;
 
       /* Set dividers for MOUThpm
        * MOUThpm =    MOUTapll = 1400 MHz
        * OUTcopy =    MOUThpm / (COPY_RATIO  1) = 200 (DIVcopy:COPY_RATIO=6)
        * sclkhpm =    OUTcopy / (HPM_RATIO  1) = 200 (DIVhpm:HPM_RATIO=0)
        * ACLK_CORES = ARMCLK / (CORES_RATIO  1) = 233 (DIVcores:CORES_RATIO=5)
        */
   clr = COPY_RATIO() | HPM_RATIO() | CORES_RATIO();
   set = COPY_RATIO() | HPM_RATIO() | CORES_RATIO();
   clrsetbits_le32(&clk->div_cpu1, clr, set);
 
   /* Wait for divider ready status */
   while (readl(&clk->div_stat_cpu1) & DIV_STAT_CPU1_CHANGING)
       continue;
 
   /*=====================set MPLL related dividers(CMU_DMC)==============================*/
 
       /*
        * Set CLK_DIV_DMC0
        * MOUTmpll = SCLKmpll = 800 MHz
        * MOUTdmc_bus  = SCLKmpll = 800 MHz
        * MOUTdphy = SCLKmpll = 800 MHz
        *
        * SCLK_DMC = MOUTdmc_bus / (DMC_RATIO  1) = 400MHz (DIVdmc:DMC_RATIO=1)
        * ACLK_DMCD = SCLK_DMC / (DMCD_RATIO  1) = 200MHz  (DIVdmcd:DMCD_RATIO=1)
        * ACLK_DMCP = ACLK_DMCD / (DMCP_RATIO  1) = 100MHz (DIVdmcp:DMCP_RATIO=1)
        * ACLK_ACP = MOUTdmc_bus / (ACP_RATIO  1) = 200MHz (DIVacp:ACP_RATIO=3)
        * PCLK_ACP = ACLK_ACP / (ACP_PCLK_RATIO  1) = 100MHz (DIVacp_pclk:ACP_PCLK_RATIO=1)
        * SCLK_DPHY = MOUTdphy / (DPHY_RATIO  1) = 400MHz (DIVdphy:DPHY_RATIO=1)
        */
   clr = DMC_RATIO() | DMCD_RATIO() | DMCP_RATIO() |
               ACP_RATIO() | ACP_PCLK_RATIO() | DPHY_RATIO();
   set = DMC_RATIO() | DMCD_RATIO() | DMCP_RATIO() |
               ACP_RATIO() | ACP_PCLK_RATIO() | DPHY_RATIO();
   clrsetbits_le32(&clk->div_dmc0, clr, set);
 
   /* Wait for divider ready status */
   while (readl(&clk->div_stat_dmc0) & DIV_STAT_DMC0_CHANGING)
       continue;
 
       /*
        * Set CLK_DIV_DMC1
        * MOUTmpll = SCLKmpll = 800 MHz
        * MOUTc2c = SCLKmpll = 800 Mhz
        * MOUTpwi = SCLKmpll = 800 MHz
        * MOUTg2d_acp = SCLKmpll = 800 MHz
        *
        * SCLK_C2C = MOUTc2c / (C2C_RATIO  1) = 400MHz (DIVc2c:C2C_RATIO=1)
        * ACLK_C2C = SCLK_C2C / (C2C_ACLK_RATIO  1) = 200MHz (DIVc2c_aclk:C2C_ACLK_RATIO=1)
        * SCLK_PWI = MOUTpwi / (PWI_RATIO  1) = 100MHz (DIVpwi:PWI_RATIO=7)
        * SCLK_G2D_ACP = MOUTg2d_acp / (G2D_ACP_RATIO  1) = 200MHz (G2D_ACP_RATIO=3)
        * IECDPMCLKEN = ACLK_DMCP/( DPM_RATIO 1) = 50MHz(DIVdpm:DPM_RATIO=1)
        * IECDVSEMCLKEN = ACLK_DMCP/( DVSEM_RATIO 1) = 50MHz(DIVdvsem:DVSEM_RATIO=1)
        */
   clr = C2C_RATIO() | C2C_ACLK_RATIO() | PWI_RATIO() |
               G2D_ACP_RATIO() | DVSEM_RATIO() | DPM_RATIO();
   set = C2C_RATIO() | C2C_ACLK_RATIO() | PWI_RATIO() |
               G2D_ACP_RATIO() | DVSEM_RATIO() | DPM_RATIO();
   clrsetbits_le32(&clk->div_dmc1, clr, set);
 
   /* Wait for divider ready status */
   while (readl(&clk->div_stat_dmc1) & DIV_STAT_DMC1_CHANGING)
       continue;
 
   /*=====================set CMU_TOP related dividers==============================*/
       /*
        * Set CLK_DIV_TOP
        * SCLKmll_user_t = SCLKmpll = 800 MHz
        * MOUTACLK_400_MC = SCLKmpll = 800 MHz
        * MOUTACLK_400_MCUISP = MOUTACLK_400_MC/(ACLK_400_MCUISP_RATIO  1) = 400MHz (DIVaclk_400_mc:ACLK_400_MCUISP_RATIO=1)
        * MOUTACLK_200 = SCLKmpll = 800 MHz
        * ACLK_200 = MOUTACLK_200/(ACLK_200_RATIO  1) = 160MHz (DIVaclk_200:ACLK_200_RATIO=4)
        * MOUTACLK_266_gps = SCLKmpll = 800 MHz
        * ACLK_266_GPS = [MOUTACLK_266_GPS /(ACLK_266_GPS_RATIO  1)] = 266MHz (DIVaclk_266_gps:ACLK_266_GPS_RATIO=2)
        * MOUTACLK_100 = SCLKmpll = 800 MHz
        * ACLK_100 = [MOUTACLK_100/(ACLK_100_RATIO  1)] = 100MHz (DIVaclk_100:ACLK_100_RATIO=7)
        * MOUTACLK_160 = SCLKmpll = 800 MHz
        * ACLK_160 = [MOUTACLK_160 /(ACLK_160_RATIO  1)] = 160MHz (DIVaclk_160:ACLK_160_RATIO=4)
        * MOUTACLK_133 = SCLKmpll = 800 MHz
        * ACLK_133 = [MOUTACLK_133 /(ACLK_133_RATIO  1)] = 133MHz (DIVaclk_133:ACLK_133_RATIO=5)
        * MOUTonenand = MOUTonenand_1 = ACLK_133MHz
        * SCLK_ONENAND = [MOUTONENAND_1 /(ONENAND_RATIO  1)] = 66MHz (DIVonenand:ONENAND_RATIO=1)
        */
   clr = ACLK_400_MCUISP_RATIO() | ACLK_200_RATIO() | ACLK_266_GPS_RATIO() |
               ACLK_100_RATIO() | ACLK_160_RATIO() | ACLK_133_RATIO() |ONENAND_RATIO();
   set = ACLK_400_MCUISP_RATIO() | ACLK_200_RATIO() | ACLK_266_GPS_RATIO() |
               ACLK_100_RATIO() | ACLK_160_RATIO() | ACLK_133_RATIO() |ONENAND_RATIO();
   clrsetbits_le32(&clk->div_top, clr, set);
 
   /* Wait for divider ready status */
   while (readl(&clk->div_stat_top) & DIV_STAT_TOP_CHANGING)
       continue;
 
   /*=====================set CMU_LEFTBUS related dividers==============================*/
       /*
        * Set CLK_DIV_LEFTBUS
        * MOUTgdl = SCLKmpll = 800 MHz
        * ACLK_GDL = MOUTgdl/(GDL_RATIO  1) = 200MHz (DIVgdl:GDL_RATIO=3)
        * ACLK_GPL = ACLK_GDL/(GPL_RATIO  1) = 100MHz (DIVgpl:GPL_RATIO=1)
        */
   clr = GDL_RATIO() | GPL_RATIO() ;
   set = GDL_RATIO() | GPL_RATIO() ;
   clrsetbits_le32(&clk->div_leftbus, clr, set);
 
   /* Wait for divider ready status */
   while (readl(&clk->div_stat_leftbus) & DIV_STAT_LEFTBUS_CHANGING)
       continue;
 
   /*=====================set CMU_RIGHTBUS related dividers==============================*/
       /*
        * Set CLK_DIV_RIGHTBUS
        * MOUTgdr = SCLKmpll = 800 MHz
        * ACLK_GDR = MOUTgdr/(GDR_RATIO  1) = 200MHz (DIVgdl:GDR_RATIO=3)
        * ACLK_GPL = ACLK_GDL/(GPR_RATIO  1) = 100MHz (DIVgpl:GPR_RATIO=1)
        */
   clr = GDR_RATIO() | GPR_RATIO() ;
   set = GDR_RATIO() | GPR_RATIO() ;
   clrsetbits_le32(&clk->div_rightbus, clr, set);
 
   /* Wait for divider ready status */
   while (readl(&clk->div_stat_rightbus) & DIV_STAT_LEFTBUS_CHANGING)
       continue;
 
   /*=====================set other dividers==============================*/
 
   /* CLK_DIV_PERIL0 (UART0-4 dividers ) */
       /*
        * MOUTuart0-4 = SCLKMPLL_USER_T =800MHz
        *
        * SCLK_UARTx = MOUTuartX / (UARTx_RATIO  1) = 100MHz (DIVuart0-4:UARTx_RATIO=7)
       */
   clr = UART0_RATIO() | UART1_RATIO() | UART2_RATIO() |
             UART3_RATIO() | UART4_RATIO();
   set = UART0_RATIO() | UART1_RATIO() | UART2_RATIO() |
             UART3_RATIO() | UART4_RATIO();
   clrsetbits_le32(&clk->div_peril0, clr, set);
 
   while (readl(&clk->div_stat_peril0) & DIV_STAT_PERIL0_CHANGING)
       continue;
 
   /* CLK_DIV_FSYS1 */
   clr = MMC0_RATIO() | MMC0_PRE_RATIO() | MMC1_RATIO() |
             MMC1_PRE_RATIO();
       /*
        * For MOUTmmc0-3 = 800 MHz (MPLL)
        *
        * DOUTmmc1 = MOUTmmc1 / (ratio  1) = 100 (7)
        * sclk_mmc1 = DOUTmmc1 / (ratio  1) = 50 (1)
        * DOUTmmc0 = MOUTmmc0 / (ratio  1) = 100 (7)
        * sclk_mmc0 = DOUTmmc0 / (ratio  1) = 50 (1)
       */
   set = MMC0_RATIO() | MMC0_PRE_RATIO() | MMC1_RATIO() |
             MMC1_PRE_RATIO();
 
   clrsetbits_le32(&clk->div_fsys1, clr, set);
 
   /* Wait for divider ready status */
   while (readl(&clk->div_stat_fsys1) & DIV_STAT_FSYS1_CHANGING)
       continue;
 
   /* CLK_DIV_FSYS2 */
   clr = MMC2_RATIO() | MMC2_PRE_RATIO() | MMC3_RATIO() |
             MMC3_PRE_RATIO();
       /*
        * For MOUTmmc0-3 = 800 MHz (MPLL)
        *
        * DOUTmmc3 = MOUTmmc3 / (ratio  1) = 100 (7)
        * sclk_mmc3 = DOUTmmc3 / (ratio  1) = 50 (1)
        * DOUTmmc2 = MOUTmmc2 / (ratio  1) = 100 (7)
        * sclk_mmc2 = DOUTmmc2 / (ratio  1) = 50 (1)
       */
   set = MMC2_RATIO() | MMC2_PRE_RATIO() | MMC3_RATIO() |
             MMC3_PRE_RATIO();
 
   clrsetbits_le32(&clk->div_fsys2, clr, set);
 
   /* Wait for divider ready status */
   while (readl(&clk->div_stat_fsys2) & DIV_STAT_FSYS2_CHANGING)
       continue;
 
   /* CLK_DIV_FSYS3 */
   clr = MMC4_RATIO() | MMC4_PRE_RATIO();
       /*
        * For MOUTmmc4 = 800 MHz (MPLL)
        *
        * DOUTmmc4 = MOUTmmc4 / (ratio  1) = 100 (7)
        * sclk_mmc4 = DOUTmmc4 / (ratio  1) = 100 (0)
       */
   set = MMC4_RATIO() | MMC4_PRE_RATIO();
 
   clrsetbits_le32(&clk->div_fsys3, clr, set);
 
   /* Wait for divider ready status */
   while (readl(&clk->div_stat_fsys3) & DIV_STAT_FSYS3_CHANGING)
       continue;
 
   /*
    * Step 2: Set APLL, MPLL, EPLL, VPLL locktime
   */
   clr = PLL_LOCKTIME();
 
   /*====== APLL locktime [APLL = 1400MHz :  SDIV(0) , PDIV(3) , MDIV(175)] =====*/
   set = PLL_LOCKTIME( PDIV() *  );
   clrsetbits_le32(&clk->apll_lock, clr, set);
 
   /*====== MPLL locktime [MPLL = 800MHz  :  SDIV(0) , PDIV(3) , MDIV(100)] =====*/
   set = PLL_LOCKTIME( PDIV() *  );
   clrsetbits_le32(&clk->mpll_lock, clr, set);
 
   /*====== EPLL locktime [EPLL = 96MHz   :  SDIV(3) , PDIV(2) , MDIV(64)] =====*/
   set = PLL_LOCKTIME( PDIV() *  );
   clrsetbits_le32(&clk->epll_lock, clr, set);
 
   /*====== VPLL locktime [VPLL = 108MHz  :  SDIV(3) , PDIV(2) , MDIV(72)] =====*/
   set = PLL_LOCKTIME( PDIV() *  );
   clrsetbits_le32(&clk->vpll_lock, clr, set);
 
   /*
    * Step 3: Set PLL PMS values and enable PLL
    *      1.Set PDIV, MDIV, and SDIV values for APLL, MPLL, EPLL, VPLL
    *      2.Turn on APLL, MPLL, EPLL, VPLL
   */
 
   /**************** Set APLL to 1400MHz ****************/
   /*APLL_CON1*/
   clr = AFC() | LOCK_CON_DLY() | LOCK_CON_IN() |
           LOCK_CON_OUT() |FEED_EN()| AFC_ENB() |
           DCC_ENB() | BYPASS() |RESV0() | RESV1();
   set = AFC() | LOCK_CON_DLY() | LOCK_CON_IN() |
           LOCK_CON_OUT() |FEED_EN()| AFC_ENB() |
           DCC_ENB() | BYPASS() |RESV0() | RESV1();
   clrsetbits_le32(&clk->apll_con1, clr, set);
 
   /*APLL_CON0*/
   clr_pll_con0 = SDIV() | PDIV() | MDIV() | FSEL();
   set = SDIV() | PDIV() | MDIV() | FSEL() | PLL_ENABLE();
   clrsetbits_le32(&clk->apll_con0, clr_pll_con0, set);
 
   /* Wait for PLL to be locked */
   while (!(readl(&clk->apll_con0) & PLL_LOCKED_BIT))
       continue;
 
   /**************** Set MPLL to 800MHz ****************/
   /*MPLL_CON1*/
   clr = AFC() | LOCK_CON_DLY() | LOCK_CON_IN() |
           LOCK_CON_OUT() |FEED_EN()| AFC_ENB() |
           DCC_ENB() | BYPASS() |RESV0() | RESV1();
   set = AFC() | LOCK_CON_DLY() | LOCK_CON_IN() |
           LOCK_CON_OUT() |FEED_EN()| AFC_ENB() |
           DCC_ENB() | BYPASS() |RESV0() | RESV1();
   clrsetbits_le32(&clk->mpll_con1, clr, set);
 
   /*MPLL_CON0*/
   set = SDIV() | PDIV() | MDIV() | FSEL() | PLL_ENABLE();
   clrsetbits_le32(&clk->mpll_con0, clr_pll_con0, set);
 
   /* Wait for PLL to be locked */
   while (!(readl(&clk->mpll_con0) & PLL_LOCKED_BIT))
       continue;
 
   /**************** Set EPLL to 96MHz ****************/
   /*EPLL_CON2*/
   clr = BYPASS_E_V() | SSCG_EN() |
           AFC_ENB_E_V() |DCC_ENB_E_V() ;
   set = BYPASS_E_V() | SSCG_EN() |
           AFC_ENB_E_V() |DCC_ENB_E_V() ;
   clrsetbits_le32(&clk->epll_con2, clr, set);
 
   /*EPLL_CON1*/
   clr = K() | MFR() | MRR() | SEL_PF();
   set = K() | MFR() | MRR() | SEL_PF();
   clrsetbits_le32(&clk->epll_con1, clr, set);
 
   /*EPLL_CON0*/
   set = SDIV() | PDIV() | MDIV() | PLL_ENABLE();
   clrsetbits_le32(&clk->epll_con0, clr_pll_con0, set);
 
   /* Wait for PLL to be locked */
   while (!(readl(&clk->epll_con0) & PLL_LOCKED_BIT))
       continue;
 
   /**************** Set VPLL to 108MHz ****************/
   /*VPLL_CON2*/
   clr = BYPASS_E_V() | SSCG_EN() |
           AFC_ENB_E_V() |DCC_ENB_E_V() ;
   set = BYPASS_E_V() | SSCG_EN() |
           AFC_ENB_E_V() |DCC_ENB_E_V() ;
   clrsetbits_le32(&clk->vpll_con2, clr, set);
 
   /*VPLL_CON1*/
   clr = K() | MFR() | MRR() | SEL_PF();
   set = K() | MFR() | MRR() | SEL_PF();
   clrsetbits_le32(&clk->vpll_con1, clr, set);
 
   /*VPLL_CON0*/
   set = SDIV() | PDIV() | MDIV() | PLL_ENABLE();
   clrsetbits_le32(&clk->vpll_con0, clr_pll_con0, set);
 
   /* Wait for PLL to be locked */
   while (!(readl(&clk->vpll_con0) & PLL_LOCKED_BIT))
       continue;
 
   /*
    * Step 4: Select the PLL(APLL, MPLL, EPLL, VPLL ...) output clock
   */
 
   /*************** Set CMU_UART0-4 clocks src MUX ***************/
 
   /* CLK_SRC_PERIL0 */
   clr = UART0_SEL() | UART1_SEL() | UART2_SEL() |
         UART3_SEL() | UART4_SEL();
   /*
    * Set CLK_SRC_PERIL0 clocks src to MPLL
    * src values: 0(XXTI); 1(XusbXTI); 2(SCLK_HDMI24M); 3(SCLK_USBPHY0);
    *             5(SCLK_HDMIPHY); 6(SCLK_MPLL_USER_T); 7(SCLK_EPLL);
    *             8(SCLK_VPLL)
    *
    * Set all to SCLK_MPLL_USER_T
    */
   set = UART0_SEL() | UART1_SEL() | UART2_SEL() | UART3_SEL() |
         UART4_SEL();
 
   clrsetbits_le32(&clk->src_peril0, clr, set);
 
   /*************** Set CMU_LEFTBUS clocks src MUX ***************/
   /* CLK_SRC_LEFTBUS */
   clr = MUX_GDL_SEL() | MUX_MPLL_USER_SEL_L();
   set = MUX_GDL_SEL() | MUX_MPLL_USER_SEL_L();
   clrsetbits_le32(&clk->src_leftbus, clr, set);
 
   /* Wait for mux change */
   sdelay(0x30000);
 
   /*************** Set CMU_RIGHTBUS clocks src MUX ***************/
   /* CLK_SRC_RIGHTBUS */
   clr = MUX_MPLL_USER_SEL_R() | MUX_GDR_SEL();
   set = MUX_MPLL_USER_SEL_R() | MUX_GDR_SEL();
   clrsetbits_le32(&clk->src_rightbus, clr, set);
 
   /* Wait for mux change */
   sdelay(0x30000);
 
   /*************** Set CMU_TOP clocks src MUX ***************/
   /* CLK_SRC_TOP0 */
   clr = MUX_EPLL_SEL() | MUX_VPLL_SEL() | MUX_ACLK_200_SEL() |
           MUX_ACLK_100_SEL() | MUX_ACLK_160_SEL() |
           MUX_ACLK_133_SEL() | MUX_ONENAND_SEL() | MUX_ONENAND_1_SEL();
   set = MUX_EPLL_SEL() | MUX_VPLL_SEL() | MUX_ACLK_200_SEL() |
           MUX_ACLK_100_SEL() | MUX_ACLK_160_SEL() |
           MUX_ACLK_133_SEL() | MUX_ONENAND_SEL() | MUX_ONENAND_1_SEL();
   clrsetbits_le32(&clk->src_top0, clr, set);
 
   /* Wait for mux change */
   sdelay(0x30000);
 
   /* CLK_SRC_TOP1 */
   clr = MUX_MPLL_USER_SEL_T() | MUX_ACLK_400_MCUISP_SEL() |
           MUX_ACLK_400_MCUISP_SUB_SEL() | MUX_ACLK_200_SUB_SEL() |
           MUX_ACLK_266_GPS_SEL() | MUX_ACLK_266_GPS_SUB_SEL();
 
   set = MUX_MPLL_USER_SEL_T() | MUX_ACLK_400_MCUISP_SEL() |
           MUX_ACLK_400_MCUISP_SUB_SEL() | MUX_ACLK_200_SUB_SEL() |
           MUX_ACLK_266_GPS_SEL() | MUX_ACLK_266_GPS_SUB_SEL();
   clrsetbits_le32(&clk->src_top1, clr, set);
 
   /* Wait for mux change */
   sdelay(0x30000);
 
   /*************** Set CMU_DMC clocks src MUX ***************/
       /*
        * Set CMU_DMC clocks src to MPLL
        * Bit values:             0  ; 1
        * MUX_C2C_SEL:      SCLKMPLL ; SCLKAPLL
        * MUX_DMC_BUS_SEL:  SCLKMPLL ; SCLKAPLL
        * MUX_DPHY_SEL:     SCLKMPLL ; SCLKAPLL
        * MUX_MPLL_SEL:     FINPLL   ; MOUT_MPLL_FOUT
        * MUX_PWI_SEL:      0110 (MPLL); 0111 (EPLL); 1000 (VPLL); 0(XXTI)
        * MUX_G2D_ACP0_SEL: SCLKMPLL ; SCLKAPLL
        * MUX_G2D_ACP1_SEL: SCLKEPLL ; SCLKVPLL
        * MUX_G2D_ACP_SEL:  OUT_ACP0 ; OUT_ACP1
       */
   clr_src_dmc = MUX_C2C_SEL() | MUX_DMC_BUS_SEL() |
             MUX_DPHY_SEL() | MUX_MPLL_SEL() |
             MUX_PWI_SEL() | MUX_G2D_ACP0_SEL() |
             MUX_G2D_ACP1_SEL() | MUX_G2D_ACP_SEL();
   set = MUX_MPLL_SEL() | MUX_C2C_SEL() | MUX_DMC_BUS_SEL() |
           MUX_DPHY_SEL() | MUX_PWI_SEL() |
           MUX_G2D_ACP0_SEL() | MUX_G2D_ACP1_SEL() | MUX_G2D_ACP_SEL();
   clrsetbits_le32(&clk->src_dmc, clr_src_dmc, set);
 
   /* Wait for mux change */
   while (readl(&clk->mux_stat_dmc) & MUX_STAT_DMC_CHANGING)
       continue;
 
   /*************** Set CMU_CPU clocks src MUX ***************/
       /* Set CMU_CPU clocks src to APLL
        * Bit values:             0      ;    1
        * MUX_APLL_SEL:        FIN_PLL   ; FOUT_APLL
        * MUX_CORE_SEL:        MOUT_APLL ; SCLK_MPLL
        * MUX_HPM_SEL:         MOUT_APLL ; SCLK_MPLL_USER_C
        * MUX_MPLL_USER_SEL_C: FIN_PLL   ; SCLK_MPLL
       */
   clr_src_cpu = MUX_APLL_SEL() | MUX_CORE_SEL() |
                   MUX_HPM_SEL() | MUX_MPLL_USER_SEL_C();
   set = MUX_APLL_SEL() | MUX_CORE_SEL() | MUX_HPM_SEL() |
         MUX_MPLL_USER_SEL_C();
   clrsetbits_le32(&clk->src_cpu, clr_src_cpu, set);
 
   /* Wait for mux change */
   while (readl(&clk->mux_stat_cpu) & MUX_STAT_CPU_CHANGING)
       continue;
}

/*
 * Copyright (C) 2014 Samsung Electronics
 * Przemyslaw Marczak <p.marczak@samsung.com>
 *
 * SPDX-License-Identifier:    GPL-2.0
 */
 
#ifndef __EXYNOS4412_SETUP__
#define __EXYNOS4412_SETUP__
 
/* A/M/E/V PLL_CON0 */
#define SDIV(x)                 ((x) & 0x7)
#define PDIV(x)                 (((x) & 0x3f) << 8)
#define MDIV(x)                 (((x) & 0x3ff) << 16)
#define FSEL(x)                 (((x) & 0x1) << 27)
#define PLL_LOCKED_BIT          (0x1 << 29)
#define PLL_ENABLE(x)           (((x) & 0x1) << 31)
 
/* A/M PLL_CON1 */
#define AFC(x)                 ((x) & 0xf)
#define LOCK_CON_DLY(x)        (((x) & 0xf) << 8)
#define LOCK_CON_IN(x)        (((x) & 0x3) << 12)
#define LOCK_CON_OUT(x)        (((x) & 0x3) << 14)
#define FEED_EN(x)        (((x) & 0x1) << 16)
#define AFC_ENB(x)        (((x) & 0x1) << 20)
#define DCC_ENB(x)        (((x) & 0x1) << 21)
#define BYPASS(x)        (((x) & 0x1) << 22)
#define RESV0(x)        (((x) & 0x1) << 23)
#define RESV1(x)        (((x) & 0x1) << 24)
 
/* E/V PLL_CON1 */
#define K(x)                 ((x) & 0xffff)
#define MFR(x)        (((x) & 0xff) << 16)
#define MRR(x)        (((x) & 0x1f) << 24)
#define SEL_PF(x)        (((x) & 0x3) << 9)
 
/* E/V PLL_CON2 */
#define ICP_BOOST(x)    ((x) & 0x3)
#define FSEL_E_V(x)        (((x) & 0x1) << 2)
#define FVCO_EN(x)        (((x) & 0x1) << 3)
#define BYPASS_E_V(x)        (((x) & 0x1) << 4)
#define SSCG_EN(x)        (((x) & 0x1) << 5)
#define AFC_ENB_E_V(x)        (((x) & 0x1) << 6)
#define DCC_ENB_E_V(x)        (((x) & 0x1) << 7)
#define EXTAFC(x)        (((x) & 0x1f) << 8)
 
#define PLL_LOCKTIME(x)    ((x) & 0xffff)
 
/* CLK_SRC_CPU */
#define MUX_APLL_SEL(x)         ((x) & 0x1)
#define MUX_CORE_SEL(x)         (((x) & 0x1) << 16)
#define MUX_HPM_SEL(x)          (((x) & 0x1) << 20)
#define MUX_MPLL_USER_SEL_C(x)  (((x) & 0x1) << 24)
 
#define MUX_STAT_CHANGING       0x100
 
/* CLK_MUX_STAT_CPU */
#define APLL_SEL(x)             ((x) & 0x7)
#define CORE_SEL(x)             (((x) & 0x7) << 16)
#define HPM_SEL(x)              (((x) & 0x7) << 20)
#define MPLL_USER_SEL_C(x)      (((x) & 0x7) << 24)
#define MUX_STAT_CPU_CHANGING   (APLL_SEL(MUX_STAT_CHANGING) | \
               CORE_SEL(MUX_STAT_CHANGING) | \
               HPM_SEL(MUX_STAT_CHANGING) | \
               MPLL_USER_SEL_C(MUX_STAT_CHANGING))
 
/* CLK_DIV_CPU0 */
#define CORE_RATIO(x)           ((x) & 0x7)
#define COREM0_RATIO(x)         (((x) & 0x7) << 4)
#define COREM1_RATIO(x)         (((x) & 0x7) << 8)
#define PERIPH_RATIO(x)         (((x) & 0x7) << 12)
#define ATB_RATIO(x)            (((x) & 0x7) << 16)
#define PCLK_DBG_RATIO(x)       (((x) & 0x7) << 20)
#define APLL_RATIO(x)           (((x) & 0x7) << 24)
#define CORE2_RATIO(x)          (((x) & 0x7) << 28)
 
/* CLK_DIV_STAT_CPU0 */
#define DIV_CORE(x)             ((x) & 0x1)
#define DIV_COREM0(x)           (((x) & 0x1) << 4)
#define DIV_COREM1(x)           (((x) & 0x1) << 8)
#define DIV_PERIPH(x)           (((x) & 0x1) << 12)
#define DIV_ATB(x)              (((x) & 0x1) << 16)
#define DIV_PCLK_DBG(x)         (((x) & 0x1) << 20)
#define DIV_APLL(x)             (((x) & 0x1) << 24)
#define DIV_CORE2(x)            (((x) & 0x1) << 28)
 
#define DIV_STAT_CHANGING       0x1
#define DIV_STAT_CPU0_CHANGING  (DIV_CORE(DIV_STAT_CHANGING) | \
               DIV_COREM0(DIV_STAT_CHANGING) | \
               DIV_COREM1(DIV_STAT_CHANGING) | \
               DIV_PERIPH(DIV_STAT_CHANGING) | \
               DIV_ATB(DIV_STAT_CHANGING) | \
               DIV_PCLK_DBG(DIV_STAT_CHANGING) | \
               DIV_APLL(DIV_STAT_CHANGING) | \
               DIV_CORE2(DIV_STAT_CHANGING))
 
/* CLK_DIV_CPU1 */
#define COPY_RATIO(x)           ((x) & 0x7)
#define HPM_RATIO(x)            (((x) & 0x7) << 4)
#define CORES_RATIO(x)          (((x) & 0x7) << 8)
 
/* CLK_DIV_STAT_CPU1 */
#define DIV_COPY(x)             ((x) & 0x7)
#define DIV_HPM(x)              (((x) & 0x1) << 4)
#define DIV_CORES(x)            (((x) & 0x1) << 8)
 
#define DIV_STAT_CPU1_CHANGING (DIV_COPY(DIV_STAT_CHANGING) | \
               DIV_HPM(DIV_STAT_CHANGING) | \
               DIV_CORES(DIV_STAT_CHANGING))
 
/* CLK_SRC_DMC */
#define MUX_C2C_SEL(x)     ((x) & 0x1)
#define MUX_DMC_BUS_SEL(x) (((x) & 0x1) << 4)
#define MUX_DPHY_SEL(x)        (((x) & 0x1) << 8)
#define MUX_MPLL_SEL(x)        (((x) & 0x1) << 12)
#define MUX_PWI_SEL(x)     (((x) & 0xf) << 16)
#define MUX_G2D_ACP0_SEL(x)    (((x) & 0x1) << 20)
#define MUX_G2D_ACP1_SEL(x)    (((x) & 0x1) << 24)
#define MUX_G2D_ACP_SEL(x) (((x) & 0x1) << 28)
 
/* CLK_MUX_STAT_DMC */
#define C2C_SEL(x)     (((x)) & 0x7)
#define DMC_BUS_SEL(x)     (((x) & 0x7) << 4)
#define DPHY_SEL(x)        (((x) & 0x7) << 8)
#define MPLL_SEL(x)        (((x) & 0x7) << 12)
/* #define PWI_SEL(x)      (((x) & 0xf) << 16)  - Reserved */
#define G2D_ACP0_SEL(x)        (((x) & 0x7) << 20)
#define G2D_ACP1_SEL(x)        (((x) & 0x7) << 24)
#define G2D_ACP_SEL(x)     (((x) & 0x7) << 28)
 
#define MUX_STAT_DMC_CHANGING  (C2C_SEL(MUX_STAT_CHANGING) | \
               DMC_BUS_SEL(MUX_STAT_CHANGING) | \
               DPHY_SEL(MUX_STAT_CHANGING) | \
               MPLL_SEL(MUX_STAT_CHANGING) |\
               G2D_ACP0_SEL(MUX_STAT_CHANGING) | \
               G2D_ACP1_SEL(MUX_STAT_CHANGING) | \
               G2D_ACP_SEL(MUX_STAT_CHANGING))
 
/* CLK_DIV_DMC0 */
#define ACP_RATIO(x)       ((x) & 0x7)
#define ACP_PCLK_RATIO(x)  (((x) & 0x7) << 4)
#define DPHY_RATIO(x)      (((x) & 0x7) << 8)
#define DMC_RATIO(x)       (((x) & 0x7) << 12)
#define DMCD_RATIO(x)      (((x) & 0x7) << 16)
#define DMCP_RATIO(x)      (((x) & 0x7) << 20)
 
/* CLK_DIV_STAT_DMC0 */
#define DIV_ACP(x)     ((x) & 0x1)
#define DIV_ACP_PCLK(x)        (((x) & 0x1) << 4)
#define DIV_DPHY(x)        (((x) & 0x1) << 8)
#define DIV_DMC(x)     (((x) & 0x1) << 12)
#define DIV_DMCD(x)        (((x) & 0x1) << 16)
#define DIV_DMCP(x)        (((x) & 0x1) << 20)
 
#define DIV_STAT_DMC0_CHANGING (DIV_ACP(DIV_STAT_CHANGING) | \
               DIV_ACP_PCLK(DIV_STAT_CHANGING) | \
               DIV_DPHY(DIV_STAT_CHANGING) | \
               DIV_DMC(DIV_STAT_CHANGING) | \
               DIV_DMCD(DIV_STAT_CHANGING) | \
               DIV_DMCP(DIV_STAT_CHANGING))
 
/* CLK_DIV_DMC1 */
#define G2D_ACP_RATIO(x)   ((x) & 0xf)
#define C2C_RATIO(x)       (((x) & 0x7) << 4)
#define PWI_RATIO(x)       (((x) & 0xf) << 8)
#define C2C_ACLK_RATIO(x)  (((x) & 0x7) << 12)
#define DVSEM_RATIO(x)     (((x) & 0x7f) << 16)
#define DPM_RATIO(x)       (((x) & 0x7f) << 24)
 
/* CLK_DIV_STAT_DMC1 */
#define DIV_G2D_ACP(x)     ((x) & 0x1)
#define DIV_C2C(x)     (((x) & 0x1) << 4)
#define DIV_PWI(x)     (((x) & 0x1) << 8)
#define DIV_C2C_ACLK(x)        (((x) & 0x1) << 12)
#define DIV_DVSEM(x)       (((x) & 0x1) << 16)
#define DIV_DPM(x)     (((x) & 0x1) << 24)
 
#define DIV_STAT_DMC1_CHANGING (DIV_G2D_ACP(DIV_STAT_CHANGING) | \
               DIV_C2C(DIV_STAT_CHANGING) | \
               DIV_PWI(DIV_STAT_CHANGING) | \
               DIV_C2C_ACLK(DIV_STAT_CHANGING) | \
               DIV_DVSEM(DIV_STAT_CHANGING) | \
               DIV_DPM(DIV_STAT_CHANGING))
 
/* CLK_DIV_TOP */
#define    ACLK_400_MCUISP_RATIO(x)    (((x) & 0x7) << 24)
#define    ACLK_266_GPS_RATIO(x)   (((x) & 0x7) << 20)
#define    ONENAND_RATIO(x)    (((x) & 0x7) << 16)
#define    ACLK_133_RATIO(x)   (((x) & 0x7) << 12)
#define ACLK_160_RATIO(x)  (((x) & 0x7) << 8)
#define ACLK_100_RATIO(x)  (((x) & 0xf) << 4)
#define ACLK_200_RATIO(x)  ((x) & 0x7)
 
#define DIV_STAT_TOP_CHANGING  (ACLK_400_MCUISP_RATIO(DIV_STAT_CHANGING) | \
               ACLK_266_GPS_RATIO(DIV_STAT_CHANGING) | \
               ONENAND_RATIO(DIV_STAT_CHANGING) | \
               ACLK_133_RATIO(DIV_STAT_CHANGING) | \
               ACLK_160_RATIO(DIV_STAT_CHANGING) | \
               ACLK_100_RATIO(DIV_STAT_CHANGING) | \
               ACLK_200_RATIO(DIV_STAT_CHANGING))
 
/* CLK_SRC_TOP0 */
#define MUX_ONENAND_SEL(x)     (((x) & 0x1) << 28)
#define MUX_ACLK_133_SEL(x)        (((x) & 0x1) << 24)
#define MUX_ACLK_160_SEL(x)        (((x) & 0x1) << 20)
#define MUX_ACLK_100_SEL(x)        (((x) & 0x1) << 16)
#define MUX_ACLK_200_SEL(x)        (((x) & 0x1) << 12)
#define MUX_VPLL_SEL(x)        (((x) & 0x1) << 8)
#define MUX_EPLL_SEL(x)        (((x) & 0x1) << 4)
#define MUX_ONENAND_1_SEL(x)   ((x) & 0x1)
 
/* CLK_MUX_STAT_TOP */
#define ONENAND_SEL(x)     (((x) & 0x3) << 28)
#define ACLK_133_SEL(x)        (((x) & 0x3) << 24)
#define ACLK_160_SEL(x)        (((x) & 0x3) << 20)
#define ACLK_100_SEL(x)        (((x) & 0x3) << 16)
#define ACLK_200_SEL(x)        (((x) & 0x3) << 12)
#define VPLL_SEL(x)        (((x) & 0x3) << 8)
#define EPLL_SEL(x)        (((x) & 0x3) << 4)
#define ONENAND_1_SEL(x)   ((x) & 0x3)
 
/* CLK_SRC_TOP1 */
#define MUX_ACLK_400_MCUISP_SUB_SEL(x)     (((x) & 0x1) << 24)
#define MUX_ACLK_200_SUB_SEL(x)        (((x) & 0x1) << 20)
#define MUX_ACLK_266_GPS_SUB_SEL(x)        (((x) & 0x1) << 16)
#define MUX_MPLL_USER_SEL_T(x)     (((x) & 0x1) << 12)
#define MUX_ACLK_400_MCUISP_SEL(x)     (((x) & 0x1) << 8)
#define MUX_ACLK_266_GPS_SEL(x)        (((x) & 0x1) << 4)
 
/* CLK_MUX_STAT_TOP1 */
#define ACLK_400_MCUISP_SUB_SEL(x)     (((x) & 0x3) << 24)
#define ACLK_200_SUB_SEL(x)        (((x) & 0x3) << 20)
#define ACLK_266_GPS_SUB_SEL(x)        (((x) & 0x3) << 16)
#define MPLL_USER_SEL_T(x)     (((x) & 0x3) << 12)
#define ACLK_400_MCUISP_SEL(x)     (((x) & 0x3) << 8)
#define ACLK_266_GPS_SEL(x)        (((x) & 0x3) << 4)
 
/*CLK_DIV_LEFTBUS*/
#define GDL_RATIO(x)   ((x) & 0x7)
#define GPL_RATIO(x)   (((x) & 0x7) << 4)
 
#define DIV_STAT_LEFTBUS_CHANGING  (GDL_RATIO(DIV_STAT_CHANGING) | \
                                       GPL_RATIO(DIV_STAT_CHANGING) )
/* CLK_SRC_LEFTBUS */
#define MUX_MPLL_USER_SEL_L(x)     (((x) & 0x1) << 4)
#define MUX_GDL_SEL(x)     ((x) & 0x1)
 
/* CLK_MUX_STAT_LEFTBUS */
#define MPLL_USER_SEL_L(x)     (((x) & 0x3) << 4)
#define GDL_SEL(x)     ((x) & 0x3)
 
/*CLK_DIV_RIGHTBUS*/
#define GDR_RATIO(x)   ((x) & 0x7)
#define GPR_RATIO(x)   (((x) & 0x7) << 4)
 
#define DIV_STAT_RIGHTBUS_CHANGING (GDR_RATIO(DIV_STAT_CHANGING) | \
                               GPR_RATIO(DIV_STAT_CHANGING) )
 
/* CLK_SRC_RIGHTBUS */
#define MUX_MPLL_USER_SEL_R(x)     (((x) & 0x1) << 4)
#define MUX_GDR_SEL(x)     ((x) & 0x1)
 
/* CLK_MUX_STAT_RIGHTBUS */
#define MPLL_USER_SEL_R(x)     (((x) & 0x3) << 4)
#define GDR_SEL(x)     ((x) & 0x3)
 
/* Set CLK_SRC_PERIL0 */
#define UART4_SEL(x)       (((x) & 0xf) << 16)
#define UART3_SEL(x)       (((x) & 0xf) << 12)
#define UART2_SEL(x)       (((x) & 0xf) << 8)
#define UART1_SEL(x)       (((x) & 0xf) << 4)
#define UART0_SEL(x)       ((x) & 0xf)
 
/* Set CLK_DIV_PERIL0 */
#define UART4_RATIO(x)     (((x) & 0xf) << 16)
#define UART3_RATIO(x)     (((x) & 0xf) << 12)
#define UART2_RATIO(x)     (((x) & 0xf) << 8)
#define UART1_RATIO(x)     (((x) & 0xf) << 4)
#define UART0_RATIO(x)     ((x) & 0xf)
 
/* Set CLK_DIV_STAT_PERIL0 */
#define DIV_UART4(x)       (((x) & 0x1) << 16)
#define DIV_UART3(x)       (((x) & 0x1) << 12)
#define DIV_UART2(x)       (((x) & 0x1) << 8)
#define DIV_UART1(x)       (((x) & 0x1) << 4)
#define DIV_UART0(x)       ((x) & 0x1)
 
#define DIV_STAT_PERIL0_CHANGING   (DIV_UART4(DIV_STAT_CHANGING) | \
                   DIV_UART3(DIV_STAT_CHANGING) | \
                   DIV_UART2(DIV_STAT_CHANGING) | \
                   DIV_UART1(DIV_STAT_CHANGING) | \
                   DIV_UART0(DIV_STAT_CHANGING))
 
/* CLK_DIV_FSYS1 */
#define MMC0_RATIO(x)      ((x) & 0xf)
#define MMC0_PRE_RATIO(x)  (((x) & 0xff) << 8)
#define MMC1_RATIO(x)      (((x) & 0xf) << 16)
#define MMC1_PRE_RATIO(x)  (((x) & 0xff) << 24)
 
/* CLK_DIV_STAT_FSYS1 */
#define DIV_MMC0(x)        ((x) & 1)
#define DIV_MMC0_PRE(x)        (((x) & 1) << 8)
#define DIV_MMC1(x)        (((x) & 1) << 16)
#define DIV_MMC1_PRE(x)        (((x) & 1) << 24)
 
#define DIV_STAT_FSYS1_CHANGING        (DIV_MMC0(DIV_STAT_CHANGING) | \
                   DIV_MMC0_PRE(DIV_STAT_CHANGING) | \
                   DIV_MMC1(DIV_STAT_CHANGING) | \
                   DIV_MMC1_PRE(DIV_STAT_CHANGING))
 
/* CLK_DIV_FSYS2 */
#define MMC2_RATIO(x)      ((x) & 0xf)
#define MMC2_PRE_RATIO(x)  (((x) & 0xff) << 8)
#define MMC3_RATIO(x)      (((x) & 0xf) << 16)
#define MMC3_PRE_RATIO(x)  (((x) & 0xff) << 24)
 
/* CLK_DIV_STAT_FSYS2 */
#define DIV_MMC2(x)        ((x) & 0x1)
#define DIV_MMC2_PRE(x)        (((x) & 0x1) << 8)
#define DIV_MMC3(x)        (((x) & 0x1) << 16)
#define DIV_MMC3_PRE(x)        (((x) & 0x1) << 24)
 
#define DIV_STAT_FSYS2_CHANGING        (DIV_MMC2(DIV_STAT_CHANGING) | \
                   DIV_MMC2_PRE(DIV_STAT_CHANGING) | \
                   DIV_MMC3(DIV_STAT_CHANGING) | \
                   DIV_MMC3_PRE(DIV_STAT_CHANGING))
 
/* CLK_DIV_FSYS3 */
#define MMC4_RATIO(x)      ((x) & 0x7)
#define MMC4_PRE_RATIO(x)  (((x) & 0xff) << 8)
 
/* CLK_DIV_STAT_FSYS3 */
#define DIV_MMC4(x)        ((x) & 0x1)
#define DIV_MMC4_PRE(x)        (((x) & 0x1) << 8)
 
#define DIV_STAT_FSYS3_CHANGING        (DIV_MMC4(DIV_STAT_CHANGING) | \
                   DIV_MMC4_PRE(DIV_STAT_CHANGING))
 
#endif /*__EXYNOS4412_SETUP__ */

这块非常重要，配置不好会涉及到后面驱动移植。还需多注意。

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tiny4412 --Uboot移植(3) 时钟