linux qcom LCD framwork

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0.关键字

MDSS : Multimedia Display sub system
DSI: Display Serial Interface

1.涉及文件

（1） drivers\video\fbmem.c （核心层）

  register_framebuffer(struct fb_info *fb_info)   //对外暴露核心函数
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（2）drivers\video\msm\mdss\mdss_fb.c (mdss 核心层 fbx平台设备驱动)

// 调用 fbmem.c的 register_framebuffer注册 fbx
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（3）drivers\video\msm\mdss\dsi_host_v2.c （lcd驱动 dsi）

// 通过下面函数向 mdss_fb.c 注册了fb_info结构  (包含在mdss_dsi_ctrl_pdata结构中)

dsi_panel_device_register_v2(struct platform_device *dev,struct mdss_dsi_ctrl_pdata *ctrl_pdata)

static const struct of_device_id msm_dsi_v2_dt_match[] = {

    {.compatible = "qcom,msm-dsi-v2"},

    {}

};
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（4）msm8610-mdss.dtsi （文件名通常为 msmxxx-mdss.dtsi 指定了mdss 的 mdp 和 dsi）

  mdss_mdp: qcom,mdss_mdp@fd900000 {

            compatible = "qcom,mdss_mdp3";

----------

  mdss_dsi0: qcom,mdss_dsi@fdd00000 {

        compatible = "qcom,msm-dsi-v2";
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（5）drivers\video\msm\mdss\mdp3.c （mdp）

   .compatible = "qcom,mdss_mdp3",


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（6）msm8610-asus.dts （指定mdp中的哪一个配置）
通常在dts文件的 mdss_dsi0 lab里面通过 qcom,dsi-pref-prim-pan 属性指定使用哪一个lcd配置

&mdss_dsi0 {

        qcom,dsi-pref-prim-pan = <&dsi_fl10802_fwvga_vid>;

};
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（7）dsi-panel-fl10802-fwvga-video.dtsi

&mdss_mdp {

    dsi_fl10802_fwvga_vid: qcom,mdss_dsi_fl10802_fwvga_video {

        qcom,mdss-dsi-panel-name = "fl10802 fwvga video mode dsi panel";

        qcom,mdss-dsi-drive-ic = "fl10802";

        qcom,mdss-dsi-panel-controller = <&mdss_dsi0>;

        qcom,mdss-dsi-panel-type = "dsi_video_mode";

        qcom,mdss-dsi-panel-destination = "display_1";

        ...

        }
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2. mdss_mdp 和 mdss_dsi0 的关系

mdss_mdp 相当于一个数组，里面定义了很多不同lcd显示屏的配置项包括分辨率等等

mdss_dsi0 的 “qcom,dsi-pref-prim-pan ” 属性指定了使用mdss_mdp中哪一个lcd配置选项

3.时序图

画的有点渣，凑活看吧，不要在意细节

4. 重要结构



backLight

关键字：qcom,mdss-dsi-bl-pmic-control-type
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// mdss_dsi_ctrl_pdata->panel_data.panel_info    = struct mdss_panel_info

struct mdss_dsi_ctrl_pdata {

    int ndx;    /* panel_num */

    int (*on) (struct mdss_panel_data *pdata);                              // ★ on

    int (*off) (struct mdss_panel_data *pdata);                             // ★ off

    int (*partial_update_fnc) (struct mdss_panel_data *pdata);

    int (*check_status) (struct mdss_dsi_ctrl_pdata *pdata);

    int (*cmdlist_commit)(struct mdss_dsi_ctrl_pdata *ctrl, int from_mdp);

    void (*switch_mode) (struct mdss_panel_data *pdata, int mode);

    struct mdss_panel_data panel_data;                          //★ panel_data->set_backlight   设置背光亮度函数

    unsigned char *ctrl_base;

    struct dss_io_data ctrl_io;

    struct dss_io_data mmss_misc_io;

    struct dss_io_data phy_io;

    int reg_size;

    u32 bus_clk_cnt;

    u32 link_clk_cnt;

    u32 flags;

    struct clk *mdp_core_clk;

    struct clk *ahb_clk;

    struct clk *axi_clk;

    struct clk *mmss_misc_ahb_clk;

    struct clk *byte_clk;

    struct clk *esc_clk;

    struct clk *pixel_clk;

    u8 ctrl_state;

    int panel_mode;

    int irq_cnt;

    int rst_gpio;                   // ★ gpio  qcom,platform-reset-gpio:        Specifies the panel reset gpio.

    int disp_en_gpio;               // qcom,platform-enable-gpio:               Specifies the panel lcd/display enable gpio.

    int disp_te_gpio;               // qcom,platform-te-gpio:                   Specifies the gpio used for TE.

    int mode_gpio;                  // qcom,platform-mode-gpio:             Select video/command mode of panel through gpio when it supports both modes.

    int disp_te_gpio_requested;

    int bklt_ctrl;                  /* backlight ctrl 背光类型*/

    int pwm_period;

    int pwm_pmic_gpio;

    int pwm_lpg_chan;

    int bklt_max;

    int new_fps;

    int pwm_enabled;

    bool dmap_iommu_map;

    struct pwm_device *pwm_bl;

    struct dsi_drv_cm_data shared_pdata;

    u32 pclk_rate;

    u32 byte_clk_rate;

    struct dss_module_power power_data;     // ★ clock & regulator

    u32 dsi_irq_mask;

    struct mdss_hw *dsi_hw;

    struct mdss_panel_recovery *recovery;

    struct dsi_panel_cmds on_cmds;          // light on cmd  ★    qcom,mdss-dsi-on-command

    struct dsi_panel_cmds off_cmds;         // off cmd      ★    qcom,mdss-dsi-off-command

    struct dsi_panel_cmds status_cmds;

    u32 status_value;

    struct dsi_panel_cmds video2cmd;

    struct dsi_panel_cmds cmd2video;

    struct dcs_cmd_list cmdlist;

    struct completion dma_comp;

    struct completion mdp_comp;

    struct completion video_comp;

    struct completion bta_comp;

    spinlock_t irq_lock;

    spinlock_t mdp_lock;

    int mdp_busy;

    struct mutex mutex;

    struct mutex cmd_mutex;

    bool ulps;

    struct dsi_buf tx_buf;

    struct dsi_buf rx_buf;

    struct dsi_buf status_buf;

    int status_mode;

};
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struct mdss_panel_info {

    u32 xres;                   // x 分辨率     qcom,mdss-dsi-panel-width

    u32 yres;                   // y 分辨率        qcom,mdss-dsi-panel-height

    u32 physical_width;         // x 物理大小   qcom,mdss-pan-physical-width-dimension

    u32 physical_height;        // y 物理大小   qcom,mdss-pan-physical-height-dimension

    struct lcd_panel_info lcdc; // 边界       （1）边界

    u32 bpp;                    // bpp          qcom,mdss-dsi-bpp

    struct mipi_panel_info mipi; // mipi显示模式 video or cmd  （2）mipi

    u32 type;

    u32 wait_cycle;

    u32 pdest;                 // 第几个fb设备  qcom,mdss-dsi-panel-destination = "display_1";

    u32 brightness_max;

    u32 bl_max;

    u32 bl_min;

    u32 fb_num;

    u32 clk_rate;

    u32 clk_min;

    u32 clk_max;

    u32 frame_count;

    u32 is_3d_panel;

    u32 out_format;

    u32 rst_seq[MDSS_DSI_RST_SEQ_LEN];

    ...

    }
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（1）边界

struct lcd_panel_info {

    u32 h_back_porch;

    u32 h_front_porch;

    u32 h_pulse_width;

    u32 v_back_porch;

    u32 v_front_porch;

    u32 v_pulse_width;

    u32 border_clr;

    u32 underflow_clr;

    u32 hsync_skew;

    /* Pad width */

    u32 xres_pad;       // qcom,mdss-dsi-h-left-border

    /* Pad height */

    u32 yres_pad;       // qcom,mdss-dsi-h-right-border

};

（2）mipi

struct mipi_panel_info {

    char mode;      /* video/cmd */   // 显示模式   qcom,mdss-dsi-panel-type = "dsi_video_mode";

    char interleave_mode;

    char crc_check;

    char ecc_check;

    char dst_format;    /* shared by video and command */

    char data_lane0;

    char data_lane1;

    char data_lane2;

    char data_lane3;

    char dlane_swap;    /* data lane swap */

    char rgb_swap;

    char b_sel;

    char g_sel;

    char r_sel;

    char rx_eot_ignore;

    char tx_eot_append;

    char t_clk_post; /* 0xc0, DSI_CLKOUT_TIMING_CTRL */

    char t_clk_pre;  /* 0xc0, DSI_CLKOUT_TIMING_CTRL */

    char vc;    /* virtual channel */

    struct mdss_dsi_phy_ctrl dsi_phy_db;

    /* video mode */

    char pulse_mode_hsa_he;

    char hfp_power_stop;

    char hbp_power_stop;

    char hsa_power_stop;

    char eof_bllp_power_stop;

    char last_line_interleave_en;

    char bllp_power_stop;

    char traffic_mode;

    char frame_rate;

    /* command mode */

    char interleave_max;

    char insert_dcs_cmd;

    char wr_mem_continue;

    char wr_mem_start;

    char te_sel;

    char stream;    /* 0 or 1 */

    char mdp_trigger;

    char dma_trigger;

    /*Dynamic Switch Support*/

    bool dynamic_switch_enabled;

    u32 pixel_packing;

    u32 dsi_pclk_rate;

    /* The packet-size should not bet changed */

    char no_max_pkt_size;

    /* Clock required during LP commands */

    char force_clk_lane_hs;

    char vsync_enable;

    char hw_vsync_mode;

    char lp11_init;

    u32  init_delay;

};


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