时钟信号的占空比调整——Verilog

时钟信号的占空比调整——Verilog

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer: chensimin
//
// Create Date: 2018/10/16 11:09:15
// Design Name:
// Module Name: duty_regulate
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////

module duty_regulate(

    input     wire     clk,
    input     wire     rst,

    output    wire     SCL_POS,
    output    wire     SCL_HIG,
    output    wire     SCL_NEG,
    output    wire     SCL_LOW
    );

//-------------------------------------------------
//首先规定一个时钟周期的长度 512
reg [:]start_cnt = ;

always @(posedge clk or posedge rst)
begin
    if(rst)
        start_cnt <= 'd0;
    else if(start_cnt == 'd511)
        start_cnt <= 'd0;
    else
        start_cnt <= start_cnt + 'b1;
end

//-------------------------------------------------
//当计数器计数到0时，SCL_HIG即整个高电平的中点
//当计数器计数到127时，SCL_NEG即时钟的下降沿
//当计数器计数到255时，SCL_LOW即时钟整个低电平的中点
//当计数器计数到382时，SCL_POS即时钟的上升沿
//结论：通过调整时钟上升沿，下降沿，高电平中点，低电平中点的位置，即可以调整整个时钟的占空比
reg [:]cnt = 'd5;
always @(posedge clk or posedge rst)
begin
    if(rst)
        cnt <= 'd5;
    else
    begin
        case(start_cnt)
            'd0 :  cnt <= 3'd1;
            'd127:  cnt <= 3'd2;
            'd255:  cnt <= 3'd3;
            'd382:  cnt <= 3'd0;
            default:  cnt <= 'd5;
        endcase
    end
end

//-------------------------------------------------

assign  SCL_POS    =    (cnt=='d0);
assign  SCL_HIG    =    (cnt=='d1);
assign  SCL_NEG    =    (cnt=='d2);
assign  SCL_LOW =    (cnt=='d3);

endmodule

/*

add_force {/duty_regulate/clk} -radix hex {1 0ns} {0 50000ps} -repeat_every 100000ps
add_force {/duty_regulate/rst} -radix hex {1 0ns} {0 200ns}

*/

仿真结果：