Xilinx Spartan6常用资源Verilog例化
// DSP48A1 : In order to incorporate this function into the design,
// Verilog : the following instance declaration needs to be placed
// instance : in the body of the design code. The instance name
// declaration : (DSP48A1_inst) and/or the port declarations within the
// code : parenthesis may be changed to properly reference and
// : connect this function to the design. All inputs
// : and outputs must be connected. // <-----Cut code below this line----> // DSP48A1: 48-bit Multi-Functional Arithmetic Block
// Spartan-6
// Xilinx HDL Language Template, version 14.7 DSP48A1 #(
.A0REG(), // First stage A input pipeline register (0/1)
.A1REG(), // Second stage A input pipeline register (0/1)
.B0REG(), // First stage B input pipeline register (0/1)
.B1REG(), // Second stage B input pipeline register (0/1)
.CARRYINREG(), // CARRYIN input pipeline register (0/1)
.CARRYINSEL("OPMODE5"), // Specify carry-in source, "CARRYIN" or "OPMODE5"
.CARRYOUTREG(), // CARRYOUT output pipeline register (0/1)
.CREG(), // C input pipeline register (0/1)
.DREG(), // D pre-adder input pipeline register (0/1)
.MREG(), // M pipeline register (0/1)
.OPMODEREG(), // Enable=1/disable=0 OPMODE input pipeline registers
.PREG(), // P output pipeline register (0/1)
.RSTTYPE("SYNC") // Specify reset type, "SYNC" or "ASYNC"
)
DSP48A1_inst (
// Cascade Ports: 18-bit (each) output: Ports to cascade from one DSP48 to another
.BCOUT(BCOUT), // 18-bit output: B port cascade output
.PCOUT(PCOUT), // 48-bit output: P cascade output (if used, connect to PCIN of another DSP48A1)
// Data Ports: 1-bit (each) output: Data input and output ports
.CARRYOUT(CARRYOUT), // 1-bit output: carry output (if used, connect to CARRYIN pin of another
// DSP48A1) .CARRYOUTF(CARRYOUTF), // 1-bit output: fabric carry output
.M(M), // 36-bit output: fabric multiplier data output
.P(P), // 48-bit output: data output
// Cascade Ports: 48-bit (each) input: Ports to cascade from one DSP48 to another
.PCIN(PCIN), // 48-bit input: P cascade input (if used, connect to PCOUT of another DSP48A1)
// Control Input Ports: 1-bit (each) input: Clocking and operation mode
.CLK(CLK), // 1-bit input: clock input
.OPMODE(OPMODE), // 8-bit input: operation mode input
// Data Ports: 18-bit (each) input: Data input and output ports
.A(A), // 18-bit input: A data input
.B(B), // 18-bit input: B data input (connected to fabric or BCOUT of adjacent DSP48A1)
.C(C), // 48-bit input: C data input
.CARRYIN(CARRYIN), // 1-bit input: carry input signal (if used, connect to CARRYOUT pin of another
// DSP48A1) .D(D), // 18-bit input: B pre-adder data input
// Reset/Clock Enable Input Ports: 1-bit (each) input: Reset and enable input ports
.CEA(CEA), // 1-bit input: active high clock enable input for A registers
.CEB(CEB), // 1-bit input: active high clock enable input for B registers
.CEC(CEC), // 1-bit input: active high clock enable input for C registers
.CECARRYIN(CECARRYIN), // 1-bit input: active high clock enable input for CARRYIN registers
.CED(CED), // 1-bit input: active high clock enable input for D registers
.CEM(CEM), // 1-bit input: active high clock enable input for multiplier registers
.CEOPMODE(CEOPMODE), // 1-bit input: active high clock enable input for OPMODE registers
.CEP(CEP), // 1-bit input: active high clock enable input for P registers
.RSTA(RSTA), // 1-bit input: reset input for A pipeline registers
.RSTB(RSTB), // 1-bit input: reset input for B pipeline registers
.RSTC(RSTC), // 1-bit input: reset input for C pipeline registers
.RSTCARRYIN(RSTCARRYIN), // 1-bit input: reset input for CARRYIN pipeline registers
.RSTD(RSTD), // 1-bit input: reset input for D pipeline registers
.RSTM(RSTM), // 1-bit input: reset input for M pipeline registers
.RSTOPMODE(RSTOPMODE), // 1-bit input: reset input for OPMODE pipeline registers
.RSTP(RSTP) // 1-bit input: reset input for P pipeline registers
); // End of DSP48A1_inst instantiation // PLL_BASE : In order to incorporate this function into the design,
// Verilog : the following instance declaration needs to be placed
// instance : in the body of the design code. The instance name
// declaration : (PLL_BASE_inst) and/or the port declarations within the
// code : parenthesis may be changed to properly reference and
// : connect this function to the design. All inputs
// : and outputs must be connected. // <-----Cut code below this line----> // PLL_BASE: Phase Locked Loop (PLL) Clock Management Component
// Spartan-6
// Xilinx HDL Language Template, version 14.7 PLL_BASE #(
.BANDWIDTH("OPTIMIZED"), // "HIGH", "LOW" or "OPTIMIZED"
.CLKFBOUT_MULT(), // Multiply value for all CLKOUT clock outputs (1-64)
.CLKFBOUT_PHASE(0.0), // Phase offset in degrees of the clock feedback output (0.0-360.0).
.CLKIN_PERIOD(0.0), // Input clock period in ns to ps resolution (i.e. 33.333 is 30
// MHz).
// CLKOUT0_DIVIDE - CLKOUT5_DIVIDE: Divide amount for CLKOUT# clock output (1-128)
.CLKOUT0_DIVIDE(),
.CLKOUT1_DIVIDE(),
.CLKOUT2_DIVIDE(),
.CLKOUT3_DIVIDE(),
.CLKOUT4_DIVIDE(),
.CLKOUT5_DIVIDE(),
// CLKOUT0_DUTY_CYCLE - CLKOUT5_DUTY_CYCLE: Duty cycle for CLKOUT# clock output (0.01-0.99).
.CLKOUT0_DUTY_CYCLE(0.5),
.CLKOUT1_DUTY_CYCLE(0.5),
.CLKOUT2_DUTY_CYCLE(0.5),
.CLKOUT3_DUTY_CYCLE(0.5),
.CLKOUT4_DUTY_CYCLE(0.5),
.CLKOUT5_DUTY_CYCLE(0.5),
// CLKOUT0_PHASE - CLKOUT5_PHASE: Output phase relationship for CLKOUT# clock output (-360.0-360.0).
.CLKOUT0_PHASE(0.0),
.CLKOUT1_PHASE(0.0),
.CLKOUT2_PHASE(0.0),
.CLKOUT3_PHASE(0.0),
.CLKOUT4_PHASE(0.0),
.CLKOUT5_PHASE(0.0),
.CLK_FEEDBACK("CLKFBOUT"), // Clock source to drive CLKFBIN ("CLKFBOUT" or "CLKOUT0")
.COMPENSATION("SYSTEM_SYNCHRONOUS"), // "SYSTEM_SYNCHRONOUS", "SOURCE_SYNCHRONOUS", "EXTERNAL"
.DIVCLK_DIVIDE(), // Division value for all output clocks (1-52)
.REF_JITTER(0.1), // Reference Clock Jitter in UI (0.000-0.999).
.RESET_ON_LOSS_OF_LOCK("FALSE") // Must be set to FALSE
)
PLL_BASE_inst (
.CLKFBOUT(CLKFBOUT), // 1-bit output: PLL_BASE feedback output
// CLKOUT0 - CLKOUT5: 1-bit (each) output: Clock outputs
.CLKOUT0(CLKOUT0),
.CLKOUT1(CLKOUT1),
.CLKOUT2(CLKOUT2),
.CLKOUT3(CLKOUT3),
.CLKOUT4(CLKOUT4),
.CLKOUT5(CLKOUT5),
.LOCKED(LOCKED), // 1-bit output: PLL_BASE lock status output
.CLKFBIN(CLKFBIN), // 1-bit input: Feedback clock input
.CLKIN(CLKIN), // 1-bit input: Clock input
.RST(RST) // 1-bit input: Reset input
); // End of PLL_BASE_inst instantiation // DCM_CLKGEN : In order to incorporate this function into the design,
// Verilog : the following instance declaration needs to be placed
// instance : in the body of the design code. The instance name
// declaration : (DCM_CLKGEN_inst) and/or the port declarations within the
// code : parenthesis may be changed to properly reference and
// : connect this function to the design. All inputs
// : and outputs must be connected. // <-----Cut code below this line----> // DCM_CLKGEN: Frequency Aligned Digital Clock Manager
// Spartan-6
// Xilinx HDL Language Template, version 14.7 DCM_CLKGEN #(
.CLKFXDV_DIVIDE(), // CLKFXDV divide value (2, 4, 8, 16, 32)
.CLKFX_DIVIDE(), // Divide value - D - (1-256)
.CLKFX_MD_MAX(0.0), // Specify maximum M/D ratio for timing anlysis
.CLKFX_MULTIPLY(), // Multiply value - M - (2-256)
.CLKIN_PERIOD(0.0), // Input clock period specified in nS
.SPREAD_SPECTRUM("NONE"), // Spread Spectrum mode "NONE", "CENTER_LOW_SPREAD", "CENTER_HIGH_SPREAD",
// "VIDEO_LINK_M0", "VIDEO_LINK_M1" or "VIDEO_LINK_M2"
.STARTUP_WAIT("FALSE") // Delay config DONE until DCM_CLKGEN LOCKED (TRUE/FALSE)
)
DCM_CLKGEN_inst (
.CLKFX(CLKFX), // 1-bit output: Generated clock output
.CLKFX180(CLKFX180), // 1-bit output: Generated clock output 180 degree out of phase from CLKFX.
.CLKFXDV(CLKFXDV), // 1-bit output: Divided clock output
.LOCKED(LOCKED), // 1-bit output: Locked output
.PROGDONE(PROGDONE), // 1-bit output: Active high output to indicate the successful re-programming
.STATUS(STATUS), // 2-bit output: DCM_CLKGEN status
.CLKIN(CLKIN), // 1-bit input: Input clock
.FREEZEDCM(FREEZEDCM), // 1-bit input: Prevents frequency adjustments to input clock
.PROGCLK(PROGCLK), // 1-bit input: Clock input for M/D reconfiguration
.PROGDATA(PROGDATA), // 1-bit input: Serial data input for M/D reconfiguration
.PROGEN(PROGEN), // 1-bit input: Active high program enable
.RST(RST) // 1-bit input: Reset input pin
); // End of DCM_CLKGEN_inst instantiation // DCM_SP : In order to incorporate this function into the design,
// Verilog : the following instance declaration needs to be placed
// instance : in the body of the design code. The instance name
// declaration : (DCM_SP_inst) and/or the port declarations within the
// code : parenthesis may be changed to properly reference and
// : connect this function to the design. All inputs
// : and outputs must be connected. // <-----Cut code below this line----> // DCM_SP: Digital Clock Manager
// Spartan-6
// Xilinx HDL Language Template, version 14.7 DCM_SP #(
.CLKDV_DIVIDE(2.0), // CLKDV divide value
// (1.5,2,2.5,3,3.5,4,4.5,5,5.5,6,6.5,7,7.5,8,9,10,11,12,13,14,15,16).
.CLKFX_DIVIDE(), // Divide value on CLKFX outputs - D - (1-32)
.CLKFX_MULTIPLY(), // Multiply value on CLKFX outputs - M - (2-32)
.CLKIN_DIVIDE_BY_2("FALSE"), // CLKIN divide by two (TRUE/FALSE)
.CLKIN_PERIOD(10.0), // Input clock period specified in nS
.CLKOUT_PHASE_SHIFT("NONE"), // Output phase shift (NONE, FIXED, VARIABLE)
.CLK_FEEDBACK("1X"), // Feedback source (NONE, 1X, 2X)
.DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"), // SYSTEM_SYNCHRNOUS or SOURCE_SYNCHRONOUS
.DFS_FREQUENCY_MODE("LOW"), // Unsupported - Do not change value
.DLL_FREQUENCY_MODE("LOW"), // Unsupported - Do not change value
.DSS_MODE("NONE"), // Unsupported - Do not change value
.DUTY_CYCLE_CORRECTION("TRUE"), // Unsupported - Do not change value
.FACTORY_JF('hc080), // Unsupported - Do not change value
.PHASE_SHIFT(), // Amount of fixed phase shift (-255 to 255)
.STARTUP_WAIT("FALSE") // Delay config DONE until DCM_SP LOCKED (TRUE/FALSE)
)
DCM_SP_inst (
.CLK0(CLK0), // 1-bit output: 0 degree clock output
.CLK180(CLK180), // 1-bit output: 180 degree clock output
.CLK270(CLK270), // 1-bit output: 270 degree clock output
.CLK2X(CLK2X), // 1-bit output: 2X clock frequency clock output
.CLK2X180(CLK2X180), // 1-bit output: 2X clock frequency, 180 degree clock output
.CLK90(CLK90), // 1-bit output: 90 degree clock output
.CLKDV(CLKDV), // 1-bit output: Divided clock output
.CLKFX(CLKFX), // 1-bit output: Digital Frequency Synthesizer output (DFS)
.CLKFX180(CLKFX180), // 1-bit output: 180 degree CLKFX output
.LOCKED(LOCKED), // 1-bit output: DCM_SP Lock Output
.PSDONE(PSDONE), // 1-bit output: Phase shift done output
.STATUS(STATUS), // 8-bit output: DCM_SP status output
.CLKFB(CLKFB), // 1-bit input: Clock feedback input
.CLKIN(CLKIN), // 1-bit input: Clock input
.DSSEN(DSSEN), // 1-bit input: Unsupported, specify to GND.
.PSCLK(PSCLK), // 1-bit input: Phase shift clock input
.PSEN(PSEN), // 1-bit input: Phase shift enable
.PSINCDEC(PSINCDEC), // 1-bit input: Phase shift increment/decrement input
.RST(RST) // 1-bit input: Active high reset input
); // End of DCM_SP_inst instantiation // RAMB16BWER : In order to incorporate this function into the design,
// Verilog : the following instance declaration needs to be placed
// instance : in the body of the design code. The instance name
// declaration : (RAMB16BWER_inst) and/or the port declarations within the
// code : parenthesis may be changed to properly reference and
// : connect this function to the design. All inputs
// : and outputs must be connected. // <-----Cut code below this line----> // RAMB16BWER: 16k-bit Data and 2k-bit Parity Configurable Synchronous Dual Port Block RAM with Optional Output Registers
// Spartan-6
// Xilinx HDL Language Template, version 14.7 RAMB16BWER #(
// DATA_WIDTH_A/DATA_WIDTH_B: 0, 1, 2, 4, 9, 18, or 36
.DATA_WIDTH_A(),
.DATA_WIDTH_B(),
// DOA_REG/DOB_REG: Optional output register (0 or 1)
.DOA_REG(),
.DOB_REG(),
// EN_RSTRAM_A/EN_RSTRAM_B: Enable/disable RST
.EN_RSTRAM_A("TRUE"),
.EN_RSTRAM_B("TRUE"),
// INITP_00 to INITP_07: Initial memory contents.
.INITP_00('h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01('h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02('h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03('h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04('h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05('h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06('h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07('h0000000000000000000000000000000000000000000000000000000000000000),
// INIT_00 to INIT_3F: Initial memory contents.
.INIT_00('h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01('h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02('h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03('h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04('h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05('h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06('h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07('h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08('h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09('h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A('h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B('h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C('h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D('h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E('h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F('h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10('h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11('h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12('h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13('h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14('h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15('h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16('h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17('h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18('h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19('h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A('h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B('h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C('h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D('h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E('h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F('h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20('h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21('h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22('h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23('h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24('h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25('h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26('h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27('h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28('h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29('h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A('h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B('h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C('h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D('h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E('h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F('h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30('h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31('h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32('h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33('h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34('h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35('h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36('h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37('h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38('h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39('h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A('h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B('h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C('h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D('h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E('h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F('h0000000000000000000000000000000000000000000000000000000000000000),
// INIT_A/INIT_B: Initial values on output port
.INIT_A('h000000000),
.INIT_B('h000000000),
// INIT_FILE: Optional file used to specify initial RAM contents
.INIT_FILE("NONE"),
// RSTTYPE: "SYNC" or "ASYNC"
.RSTTYPE("SYNC"),
// RST_PRIORITY_A/RST_PRIORITY_B: "CE" or "SR"
.RST_PRIORITY_A("CE"),
.RST_PRIORITY_B("CE"),
// SIM_COLLISION_CHECK: Collision check enable "ALL", "WARNING_ONLY", "GENERATE_X_ONLY" or "NONE"
.SIM_COLLISION_CHECK("ALL"),
// SIM_DEVICE: Must be set to "SPARTAN6" for proper simulation behavior
.SIM_DEVICE("SPARTAN3ADSP"),
// SRVAL_A/SRVAL_B: Set/Reset value for RAM output
.SRVAL_A('h000000000),
.SRVAL_B('h000000000),
// WRITE_MODE_A/WRITE_MODE_B: "WRITE_FIRST", "READ_FIRST", or "NO_CHANGE"
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST")
)
RAMB16BWER_inst (
// Port A Data: 32-bit (each) output: Port A data
.DOA(DOA), // 32-bit output: A port data output
.DOPA(DOPA), // 4-bit output: A port parity output
// Port B Data: 32-bit (each) output: Port B data
.DOB(DOB), // 32-bit output: B port data output
.DOPB(DOPB), // 4-bit output: B port parity output
// Port A Address/Control Signals: 14-bit (each) input: Port A address and control signals
.ADDRA(ADDRA), // 14-bit input: A port address input
.CLKA(CLKA), // 1-bit input: A port clock input
.ENA(ENA), // 1-bit input: A port enable input
.REGCEA(REGCEA), // 1-bit input: A port register clock enable input
.RSTA(RSTA), // 1-bit input: A port register set/reset input
.WEA(WEA), // 4-bit input: Port A byte-wide write enable input
// Port A Data: 32-bit (each) input: Port A data
.DIA(DIA), // 32-bit input: A port data input
.DIPA(DIPA), // 4-bit input: A port parity input
// Port B Address/Control Signals: 14-bit (each) input: Port B address and control signals
.ADDRB(ADDRB), // 14-bit input: B port address input
.CLKB(CLKB), // 1-bit input: B port clock input
.ENB(ENB), // 1-bit input: B port enable input
.REGCEB(REGCEB), // 1-bit input: B port register clock enable input
.RSTB(RSTB), // 1-bit input: B port register set/reset input
.WEB(WEB), // 4-bit input: Port B byte-wide write enable input
// Port B Data: 32-bit (each) input: Port B data
.DIB(DIB), // 32-bit input: B port data input
.DIPB(DIPB) // 4-bit input: B port parity input
); // End of RAMB16BWER_inst instantiation // RAMB8BWER : In order to incorporate this function into the design,
// Verilog : the following instance declaration needs to be placed
// instance : in the body of the design code. The instance name
// declaration : (RAMB8BWER_inst) and/or the port declarations within the
// code : parenthesis may be changed to properly reference and
// : connect this function to the design. All inputs
// : and outputs must be connected. // <-----Cut code below this line----> // RAMB8BWER: 8k-bit Data and 1k-bit Parity Configurable Synchronous Block RAM
// Spartan-6
// Xilinx HDL Language Template, version 14.7 RAMB8BWER #(
// DATA_WIDTH_A/DATA_WIDTH_B: 'If RAM_MODE="TDP": 0, 1, 2, 4, 9 or 18; If RAM_MODE="SDP": 36'
.DATA_WIDTH_A(),
.DATA_WIDTH_B(),
// DOA_REG/DOB_REG: Optional output register (0 or 1)
.DOA_REG(),
.DOB_REG(),
// EN_RSTRAM_A/EN_RSTRAM_B: Enable/disable RST
.EN_RSTRAM_A("TRUE"),
.EN_RSTRAM_B("TRUE"),
// INITP_00 to INITP_03: Initial memory contents.
.INITP_00('h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01('h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02('h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03('h0000000000000000000000000000000000000000000000000000000000000000),
// INIT_00 to INIT_1F: Initial memory contents.
.INIT_00('h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01('h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02('h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03('h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04('h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05('h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06('h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07('h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08('h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09('h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A('h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B('h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C('h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D('h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E('h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F('h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10('h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11('h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12('h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13('h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14('h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15('h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16('h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17('h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18('h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19('h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A('h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B('h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C('h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D('h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E('h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F('h0000000000000000000000000000000000000000000000000000000000000000),
// INIT_A/INIT_B: Initial values on output port
.INIT_A('h00000),
.INIT_B('h00000),
// INIT_FILE: Not Supported
.INIT_FILE("NONE"), // Do not modify
// RAM_MODE: "SDP" or "TDP"
.RAM_MODE("TDP"),
// RSTTYPE: "SYNC" or "ASYNC"
.RSTTYPE("SYNC"),
// RST_PRIORITY_A/RST_PRIORITY_B: "CE" or "SR"
.RST_PRIORITY_A("CE"),
.RST_PRIORITY_B("CE"),
// SIM_COLLISION_CHECK: Collision check enable "ALL", "WARNING_ONLY", "GENERATE_X_ONLY" or "NONE"
.SIM_COLLISION_CHECK("ALL"),
// SRVAL_A/SRVAL_B: Set/Reset value for RAM output
.SRVAL_A('h00000),
.SRVAL_B('h00000),
// WRITE_MODE_A/WRITE_MODE_B: "WRITE_FIRST", "READ_FIRST", or "NO_CHANGE"
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST")
)
RAMB8BWER_inst (
// Port A Data: 16-bit (each) output: Port A data
.DOADO(DOADO), // 16-bit output: A port data/LSB data output
.DOPADOP(DOPADOP), // 2-bit output: A port parity/LSB parity output
// Port B Data: 16-bit (each) output: Port B data
.DOBDO(DOBDO), // 16-bit output: B port data/MSB data output
.DOPBDOP(DOPBDOP), // 2-bit output: B port parity/MSB parity output
// Port A Address/Control Signals: 13-bit (each) input: Port A address and control signals (write port
// when RAM_MODE="SDP")
.ADDRAWRADDR(ADDRAWRADDR), // 13-bit input: A port address/Write address input
.CLKAWRCLK(CLKAWRCLK), // 1-bit input: A port clock/Write clock input
.ENAWREN(ENAWREN), // 1-bit input: A port enable/Write enable input
.REGCEA(REGCEA), // 1-bit input: A port register enable input
.RSTA(RSTA), // 1-bit input: A port set/reset input
.WEAWEL(WEAWEL), // 2-bit input: A port write enable input
// Port A Data: 16-bit (each) input: Port A data
.DIADI(DIADI), // 16-bit input: A port data/LSB data input
.DIPADIP(DIPADIP), // 2-bit input: A port parity/LSB parity input
// Port B Address/Control Signals: 13-bit (each) input: Port B address and control signals (read port
// when RAM_MODE="SDP")
.ADDRBRDADDR(ADDRBRDADDR), // 13-bit input: B port address/Read address input
.CLKBRDCLK(CLKBRDCLK), // 1-bit input: B port clock/Read clock input
.ENBRDEN(ENBRDEN), // 1-bit input: B port enable/Read enable input
.REGCEBREGCE(REGCEBREGCE), // 1-bit input: B port register enable/Register enable input
.RSTBRST(RSTBRST), // 1-bit input: B port set/reset input
.WEBWEU(WEBWEU), // 2-bit input: B port write enable input
// Port B Data: 16-bit (each) input: Port B data
.DIBDI(DIBDI), // 16-bit input: B port data/MSB data input
.DIPBDIP(DIPBDIP) // 2-bit input: B port parity/MSB parity input
); // End of RAMB8BWER_inst instantiation // RAM256X1S : In order to incorporate this function into the design,
// Verilog : the forllowing instance declaration needs to be placed
// instance : in the body of the design code. The instance name
// declaration : (RAM256X1S_inst) and/or the port declarations within the
// code : parenthesis may be changed to properly reference and
// : connect this function to the design. All inputs
// : and outputs must be connected. // <-----Cut code below this line----> // RAM256X1S: 256-deep by 1-wide positive edge write, asynchronous read
// single-port distributed LUT RAM
// Spartan-6
// Xilinx HDL Language Template, version 14.7 RAM256X1S #(
.INIT('h0000000000000000000000000000000000000000000000000000000000000000)
) RAM256X1S_inst (
.O(O), // Read/write port 1-bit output
.A(A), // Read/write port 8-bit address input
.WE(WE), // Write enable input
.WCLK(WCLK), // Write clock input
.D(D) // RAM data input
); // End of RAM256X1S_inst instantiation // RAM64M : In order to incorporate this function into the design,
// Verilog : the forllowing instance declaration needs to be placed
// instance : in the body of the design code. The instance name
// declaration : (RAM64M_inst) and/or the port declarations within the
// code : parenthesis may be changed to properly reference and
// : connect this function to the design. All inputs
// : and outputs must be connected. // <-----Cut code below this line----> // RAM64M: 64-deep by 4-wide Multi Port LUT RAM
// Spartan-6
// Xilinx HDL Language Template, version 14.7 RAM64M #(
.INIT_A('h0000000000000000), // Initial contents of A Port
.INIT_B('h0000000000000000), // Initial contents of B Port
.INIT_C('h0000000000000000), // Initial contents of C Port
.INIT_D('h0000000000000000) // Initial contents of D Port
) RAM64M_inst (
.DOA(DOA), // Read port A 1-bit output
.DOB(DOB), // Read port B 1-bit output
.DOC(DOC), // Read port C 1-bit output
.DOD(DOD), // Read/write port D 1-bit output
.DIA(DIA), // RAM 1-bit data write input addressed by ADDRD,
// read addressed by ADDRA
.DIB(DIB), // RAM 1-bit data write input addressed by ADDRD,
// read addressed by ADDRB
.DIC(DIC), // RAM 1-bit data write input addressed by ADDRD,
// read addressed by ADDRC
.DID(DID), // RAM 1-bit data write input addressed by ADDRD,
// read addressed by ADDRD
.ADDRA(ADDRA), // Read port A 6-bit address input
.ADDRB(ADDRB), // Read port B 6-bit address input
.ADDRC(ADDRC), // Read port C 6-bit address input
.ADDRD(ADDRD), // Read/write port D 6-bit address input
.WE(WE), // Write enable input
.WCLK(WCLK) // Write clock input
); // End of RAM64M_inst instantiation // RAM32X1D : In order to incorporate this function into the design,
// Verilog : the forllowing instance declaration needs to be placed
// instance : in the body of the design code. The instance name
// declaration : (RAM32X1D_inst) and/or the port declarations within the
// code : parenthesis may be changed to properly reference and
// : connect this function to the design. All inputs
// : and outputs must be connected. // <-----Cut code below this line----> // RAM32X1D: 32 x 1 positive edge write, asynchronous read dual-port distributed RAM
// Spartan-6
// Xilinx HDL Language Template, version 14.7 RAM32X1D #(
.INIT('h00000000) // Initial contents of RAM
) RAM32X1D_inst (
.DPO(DPO), // Read-only 1-bit data output
.SPO(SPO), // Rw/ 1-bit data output
.A0(A0), // Rw/ address[0] input bit
.A1(A1), // Rw/ address[1] input bit
.A2(A2), // Rw/ address[2] input bit
.A3(A3), // Rw/ address[3] input bit
.A4(A4), // Rw/ address[4] input bit
.D(D), // Write 1-bit data input
.DPRA0(DPRA0), // Read-only address[0] input bit
.DPRA1(DPRA1), // Read-only address[1] input bit
.DPRA2(DPRA2), // Read-only address[2] input bit
.DPRA3(DPRA3), // Read-only address[3] input bit
.DPRA4(DPRA4), // Read-only address[4] input bit
.WCLK(WCLK), // Write clock input
.WE(WE) // Write enable input
); // End of RAM32X1D_inst instantiation // MUXF8 : In order to incorporate this function into the design,
// Verilog : the forllowing instance declaration needs to be placed
// instance : in the body of the design code. The instance name
// declaration : (MUXF8_inst) and/or the port declarations within the
// code : parenthesis may be changed to properly reference and
// : connect this function to the design. All inputs
// : and outputs must be connected. // <-----Cut code below this line----> // MUXF8: CLB MUX to tie two MUXF7's together with general output
// Spartan-6
// Xilinx HDL Language Template, version 14.7 MUXF8 MUXF8_inst (
.O(O), // Output of MUX to general routing
.I0(I0), // Input (tie to MUXF7 LO out)
.I1(I1), // Input (tie to MUXF7 LO out)
.S(S) // Input select to MUX
); // End of MUXF8_inst instantiation
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