imx6开启启动之后，运行板子上的ROM程序。ROM确定启动的设备，进行一些初始化，然后读取IVT，进行寄存器初始化,最后运行uboot/cpu/arm_cortexa8/start.S中的_start函数。

参考

http://blog.csdn.net/njuitjf/article/details/20563867

http://blog.csdn.net/sz_zh/article/details/7930341

截取IMX6SDLRM.pdf部分内容

  1. 8.6.1 Image Vector Table and Boot Data
  2. # ROM读取IVT中内容。
  3. The Image Vector Table (IVT) is the data structure that the ROM reads from the boot
  4. device supplying the program image containing the required data components to perform
  5. a successful boot.
  6. # IVT包含DCD的入口点和其他的入口点，给ROM使用。
  7. # IVT在设备中的地址是固定的，这样ROM才能够找到。
  8. The IVT includes the program image entry point, a pointer to Device Configuration Data
  9. (DCD) and other pointers used by the ROM during the boot process.The ROM locates
  10. the IVT at a fixed address that is determined by the boot device connected to the Chip.
  11. The IVT offset from the base address and initial load region size for each boot device
  12. type is defined in the table below. The location of the IVT is the only fixed requirement
  13. by the ROM. The remainder or the image memory map is flexible and is determined by
  14. the contents of the IVT.
  15. # IVT表在不同设备中的偏移地址和空间的大小
  16. Table 8-24. Image Vector Table Offset and Initial Load Region Size
  17. Boot Device Type 		Image Vector Table Offset 		Initial Load Region Size
  18. NOR 					4 Kbyte = 0x1000 bytes 			Entire Image Size
  19. NAND 					1 Kbyte = 0x400 bytes 			4 Kbyte
  20. OneNAND 				256 bytes = 0x100 bytes 		1 Kbyte
  21. SD/MMC/eSD/eMMC/SDXC 	1 Kbyte = 0x400 bytes 			4 Kbyte
  22. I2C/SPI EEPROM 			1 Kbyte = 0x400 bytes 			4 Kbyte
  24. # DCD
  25. 8.6.2 Device Configuration Data (DCD)
  26. # 开启启动的时候根据需要更改寄存器的默认值,方便一些外设一开机就配置
  27. Upon reset, the Chip uses the default register values for all peripherals in the system.
  28. However, these settings typically are not ideal for achieving optimal system performance
  29. and there are even some peripherals that must be configured before they can be used.
  31. The DCD is configuration information contained in a Program Image, external to the
  32. ROM, that the ROM interprets to configure various peripherals on the Chip.

flash_header.S分析

  1. #include <config.h>
  2. #include <asm/arch/mx6.h>
  4. #ifdef	CONFIG_FLASH_HEADER
  5. #ifndef CONFIG_FLASH_HEADER_OFFSET
  6. # error "Must define the offset of flash header"
  7. #endif
  9. #define CPU_2_BE_32(l) \
  10.        ((((l) & 0x000000FF) << 24) | \
  11. 	(((l) & 0x0000FF00) << 8)  | \
  12. 	(((l) & 0x00FF0000) >> 8)  | \
  13. 	(((l) & 0xFF000000) >> 24))
  15. #define MXC_DCD_ITEM(i, addr, val)   \
  16. dcd_node_##i:                        \
  17.         .word CPU_2_BE_32(addr) ;     \		# 存放寄存器地址, 4字节
  18.         .word CPU_2_BE_32(val)  ;     \		# 存放设置的值,	  4字节
  20. .section ".text.flasheader", "x"
  21. 	b	_start
  22. 	.org	CONFIG_FLASH_HEADER_OFFSET
  24. # ivt header
  25. ivt_header:       .word 0x402000D1 /* Tag=0xD1, Len=0x0020, Ver=0x40 */
  26. # entry
  27. app_code_jump_v:  .word _start
  28. reserv1:          .word 0x0
  29. dcd_ptr:          .word dcd_hdr
  30. boot_data_ptr:	  .word boot_data
  31. self_ptr:         .word ivt_header
  32. #ifdef CONFIG_SECURE_BOOT
  33. app_code_csf:     .word __hab_data
  34. #else
  35. app_code_csf:     .word 0x0
  36. #endif
  37. reserv2:          .word 0x0
  39. boot_data:        .word TEXT_BASE
  40. #ifdef CONFIG_SECURE_BOOT
  41. image_len:        .word __hab_data_end - TEXT_BASE + CONFIG_FLASH_HEADER_OFFSET
  42. #else
  43. image_len:        .word _end_of_copy  - TEXT_BASE + CONFIG_FLASH_HEADER_OFFSET
  44. #endif
  45. plugin:           .word 0x0
  47. #if defined CONFIG_MX6DL_DDR3
  48. #if defined CONFIG_DDR_32BIT
  49. dcd_hdr:          .word 0x40E001D2 /* Tag=0xD2, Len=59*8 + 4 + 4, Ver=0x40 */
  50. write_dcd_cmd:    .word 0x04DC01CC /* Tag=0xCC, Len=59*8 + 4, Param=0x04 */
  51. # 各种DDR寄存器的初始化
  52. MXC_DCD_ITEM(1, IOMUXC_BASE_ADDR + 0x774, 0x000C0000)        // DDR3
  53. MXC_DCD_ITEM(2, IOMUXC_BASE_ADDR + 0x754, 0x00000000)        // DDR Pull/Kepper Disable
  55. MXC_DCD_ITEM(3, IOMUXC_BASE_ADDR + 0x4ac, 0x00000030)
  56. MXC_DCD_ITEM(4, IOMUXC_BASE_ADDR + 0x4b0, 0x00000030)
  58. MXC_DCD_ITEM(5, IOMUXC_BASE_ADDR + 0x464, 0x00000030)
  59. MXC_DCD_ITEM(6, IOMUXC_BASE_ADDR + 0x490, 0x00000030)
  60. MXC_DCD_ITEM(7, IOMUXC_BASE_ADDR + 0x74c, 0x00000030)
  62. MXC_DCD_ITEM(8, IOMUXC_BASE_ADDR + 0x494, 0x00000030)
  64. MXC_DCD_ITEM(9, IOMUXC_BASE_ADDR + 0x4a0, 0x00000000)
  66. MXC_DCD_ITEM(10, IOMUXC_BASE_ADDR + 0x4b4, 0x00000030)
  67. MXC_DCD_ITEM(11, IOMUXC_BASE_ADDR + 0x4b8, 0x00000030)
  68. MXC_DCD_ITEM(12, IOMUXC_BASE_ADDR + 0x76c, 0x00000030)
  70. MXC_DCD_ITEM(13, IOMUXC_BASE_ADDR + 0x750, 0x00020000)
  72. MXC_DCD_ITEM(14, IOMUXC_BASE_ADDR + 0x4bc, 0x00000030)
  73. MXC_DCD_ITEM(15, IOMUXC_BASE_ADDR + 0x4c0, 0x00000030)
  74. MXC_DCD_ITEM(16, IOMUXC_BASE_ADDR + 0x4c4, 0x00000030)
  75. MXC_DCD_ITEM(17, IOMUXC_BASE_ADDR + 0x4c8, 0x00000030)
  77. MXC_DCD_ITEM(18, IOMUXC_BASE_ADDR + 0x760, 0x00020000)
  79. MXC_DCD_ITEM(19, IOMUXC_BASE_ADDR + 0x764, 0x00000030)
  80. MXC_DCD_ITEM(20, IOMUXC_BASE_ADDR + 0x770, 0x00000030)
  81. MXC_DCD_ITEM(21, IOMUXC_BASE_ADDR + 0x778, 0x00000030)
  82. MXC_DCD_ITEM(22, IOMUXC_BASE_ADDR + 0x77c, 0x00000030)
  84. MXC_DCD_ITEM(23, IOMUXC_BASE_ADDR + 0x470, 0x00000030)
  85. MXC_DCD_ITEM(24, IOMUXC_BASE_ADDR + 0x474, 0x00000030)
  86. MXC_DCD_ITEM(25, IOMUXC_BASE_ADDR + 0x478, 0x00000030)
  87. MXC_DCD_ITEM(26, IOMUXC_BASE_ADDR + 0x47c, 0x00000030)
  89. MXC_DCD_ITEM(27, MMDC_P0_BASE_ADDR + 0x800, 0xA1390003)
  91. MXC_DCD_ITEM(28, MMDC_P0_BASE_ADDR + 0x80c, 0x001F001F)
  92. MXC_DCD_ITEM(29, MMDC_P0_BASE_ADDR + 0x810, 0x001F001F)
  94. MXC_DCD_ITEM(30, MMDC_P0_BASE_ADDR + 0x83c, 0x42190219)
  95. MXC_DCD_ITEM(31, MMDC_P0_BASE_ADDR + 0x840, 0x017B0177)
  96. MXC_DCD_ITEM(32, MMDC_P0_BASE_ADDR + 0x848, 0x4B4D4E4D)
  97. MXC_DCD_ITEM(33, MMDC_P0_BASE_ADDR + 0x850, 0x3F3E2D36)
  99. MXC_DCD_ITEM(34, MMDC_P0_BASE_ADDR + 0x81c, 0x33333333)
  100. MXC_DCD_ITEM(35, MMDC_P0_BASE_ADDR + 0x820, 0x33333333)
  101. MXC_DCD_ITEM(36, MMDC_P0_BASE_ADDR + 0x824, 0x33333333)
  102. MXC_DCD_ITEM(37, MMDC_P0_BASE_ADDR + 0x828, 0x33333333)
  104. MXC_DCD_ITEM(38, MMDC_P0_BASE_ADDR + 0x8b8, 0x00000800)
  106. MXC_DCD_ITEM(39, MMDC_P0_BASE_ADDR + 0x004, 0x0002002D)
  107. MXC_DCD_ITEM(40, MMDC_P0_BASE_ADDR + 0x008, 0x00333030)
  108. MXC_DCD_ITEM(41, MMDC_P0_BASE_ADDR + 0x00c, 0x3F435313)
  109. MXC_DCD_ITEM(42, MMDC_P0_BASE_ADDR + 0x010, 0xB66E8B63)
  110. MXC_DCD_ITEM(43, MMDC_P0_BASE_ADDR + 0x014, 0x01FF00DB)
  111. MXC_DCD_ITEM(44, MMDC_P0_BASE_ADDR + 0x018, 0x00001740)
  113. MXC_DCD_ITEM(45, MMDC_P0_BASE_ADDR + 0x01c, 0x00008000)
  114. MXC_DCD_ITEM(46, MMDC_P0_BASE_ADDR + 0x02c, 0x000026d2)
  116. MXC_DCD_ITEM(47, MMDC_P0_BASE_ADDR + 0x030, 0x00431023)
  117. MXC_DCD_ITEM(48, MMDC_P0_BASE_ADDR + 0x040, 0x00000017)
  119. MXC_DCD_ITEM(49, MMDC_P0_BASE_ADDR + 0x000, 0x83190000)
  121. MXC_DCD_ITEM(50, MMDC_P0_BASE_ADDR + 0x01c, 0x04008032)
  122. MXC_DCD_ITEM(51, MMDC_P0_BASE_ADDR + 0x01c, 0x00008033)
  123. MXC_DCD_ITEM(52, MMDC_P0_BASE_ADDR + 0x01c, 0x00048031)
  124. MXC_DCD_ITEM(53, MMDC_P0_BASE_ADDR + 0x01c, 0x05208030)
  125. MXC_DCD_ITEM(54, MMDC_P0_BASE_ADDR + 0x01c, 0x04008040)
  127. MXC_DCD_ITEM(55, MMDC_P0_BASE_ADDR + 0x020, 0x00005800)
  128. MXC_DCD_ITEM(56, MMDC_P0_BASE_ADDR + 0x818, 0x00011117)
  130. MXC_DCD_ITEM(57, MMDC_P0_BASE_ADDR + 0x004, 0x0002556d)
  131. MXC_DCD_ITEM(58, MMDC_P0_BASE_ADDR + 0x404, 0x00011006)
  133. MXC_DCD_ITEM(59, MMDC_P0_BASE_ADDR + 0x01c, 0x00000000)
  134. #else /* i.MX6DL 64BIT-DDR */
  135. dcd_hdr:          .word 0x40A002D2 /* Tag=0xD2, Len=83*8 + 4 + 4, Ver=0x40 */
  136. write_dcd_cmd:    .word 0x049C02CC /* Tag=0xCC, Len=83*8 + 4, Param=0x04 */
  138. # IOMUXC_BASE_ADDR  = 0x20e0000
  139. # DDR IO TYPE
  140. MXC_DCD_ITEM(1, IOMUXC_BASE_ADDR + 0x774, 0x000c0000)
  141. MXC_DCD_ITEM(2, IOMUXC_BASE_ADDR + 0x754, 0x00000000)
  142. # Clock
  143. MXC_DCD_ITEM(3, IOMUXC_BASE_ADDR + 0x4ac, 0x00000030)
  144. MXC_DCD_ITEM(4, IOMUXC_BASE_ADDR + 0x4b0, 0x00000030)
  145. # Address
  146. MXC_DCD_ITEM(5, IOMUXC_BASE_ADDR + 0x464, 0x00000030)
  147. MXC_DCD_ITEM(6, IOMUXC_BASE_ADDR + 0x490, 0x00000030)
  148. MXC_DCD_ITEM(7, IOMUXC_BASE_ADDR + 0x74c, 0x00000030)
  149. # Control
  150. MXC_DCD_ITEM(8, IOMUXC_BASE_ADDR + 0x494, 0x00000030)
  152. MXC_DCD_ITEM(9, IOMUXC_BASE_ADDR + 0x4a0, 0x00000000)
  154. MXC_DCD_ITEM(10, IOMUXC_BASE_ADDR + 0x4b4, 0x00000030)
  155. MXC_DCD_ITEM(11, IOMUXC_BASE_ADDR + 0x4b8, 0x00000030)
  156. MXC_DCD_ITEM(12, IOMUXC_BASE_ADDR + 0x76c, 0x00000030)
  157. # Data Strobe
  158. MXC_DCD_ITEM(13, IOMUXC_BASE_ADDR + 0x750, 0x00020000)
  160. MXC_DCD_ITEM(14, IOMUXC_BASE_ADDR + 0x4bc, 0x00000030)
  161. MXC_DCD_ITEM(15, IOMUXC_BASE_ADDR + 0x4c0, 0x00000030)
  162. MXC_DCD_ITEM(16, IOMUXC_BASE_ADDR + 0x4c4, 0x00000030)
  163. MXC_DCD_ITEM(17, IOMUXC_BASE_ADDR + 0x4c8, 0x00000030)
  164. MXC_DCD_ITEM(18, IOMUXC_BASE_ADDR + 0x4cc, 0x00000030)
  165. MXC_DCD_ITEM(19, IOMUXC_BASE_ADDR + 0x4d0, 0x00000030)
  166. MXC_DCD_ITEM(20, IOMUXC_BASE_ADDR + 0x4d4, 0x00000030)
  167. MXC_DCD_ITEM(21, IOMUXC_BASE_ADDR + 0x4d8, 0x00000030)
  169. MXC_DCD_ITEM(22, IOMUXC_BASE_ADDR + 0x760, 0x00020000)
  171. MXC_DCD_ITEM(23, IOMUXC_BASE_ADDR + 0x764, 0x00000030)
  172. MXC_DCD_ITEM(24, IOMUXC_BASE_ADDR + 0x770, 0x00000030)
  173. MXC_DCD_ITEM(25, IOMUXC_BASE_ADDR + 0x778, 0x00000030)
  174. MXC_DCD_ITEM(26, IOMUXC_BASE_ADDR + 0x77c, 0x00000030)
  175. MXC_DCD_ITEM(27, IOMUXC_BASE_ADDR + 0x780, 0x00000030)
  176. MXC_DCD_ITEM(28, IOMUXC_BASE_ADDR + 0x784, 0x00000030)
  177. MXC_DCD_ITEM(29, IOMUXC_BASE_ADDR + 0x78c, 0x00000030)
  178. MXC_DCD_ITEM(30, IOMUXC_BASE_ADDR + 0x748, 0x00000030)
  180. MXC_DCD_ITEM(31, IOMUXC_BASE_ADDR + 0x470, 0x00000030)
  181. MXC_DCD_ITEM(32, IOMUXC_BASE_ADDR + 0x474, 0x00000030)
  182. MXC_DCD_ITEM(33, IOMUXC_BASE_ADDR + 0x478, 0x00000030)
  183. MXC_DCD_ITEM(34, IOMUXC_BASE_ADDR + 0x47c, 0x00000030)
  184. MXC_DCD_ITEM(35, IOMUXC_BASE_ADDR + 0x480, 0x00000030)
  185. MXC_DCD_ITEM(36, IOMUXC_BASE_ADDR + 0x484, 0x00000030)
  186. MXC_DCD_ITEM(37, IOMUXC_BASE_ADDR + 0x488, 0x00000030)
  187. MXC_DCD_ITEM(38, IOMUXC_BASE_ADDR + 0x48c, 0x00000030)
  189. # MMDC_P0_BASE_ADDR = 0x021b0000
  190. # MMDC_P1_BASE_ADDR = 0x021b4000
  191. # Calibrations
  192. # ZQ
  193. MXC_DCD_ITEM(39, MMDC_P0_BASE_ADDR + 0x800, 0xa1390003)
  195. # write leveling
  196. MXC_DCD_ITEM(40, MMDC_P0_BASE_ADDR + 0x80c, 0x001F001F)
  197. MXC_DCD_ITEM(41, MMDC_P0_BASE_ADDR + 0x810, 0x001F001F)
  198. MXC_DCD_ITEM(42, MMDC_P1_BASE_ADDR + 0x80c, 0x001F001F)
  199. MXC_DCD_ITEM(43, MMDC_P1_BASE_ADDR + 0x810, 0x001F001F)
  200. # DQS gating, read delay, write delay calibration values
  201. # based on calibration compare of 0x00ffff00
  202. MXC_DCD_ITEM(44, MMDC_P0_BASE_ADDR + 0x83c, 0x42480248)
  203. MXC_DCD_ITEM(45, MMDC_P0_BASE_ADDR + 0x840, 0x0211020B)
  204. MXC_DCD_ITEM(46, MMDC_P1_BASE_ADDR + 0x83C, 0x417F0211)
  205. MXC_DCD_ITEM(47, MMDC_P1_BASE_ADDR + 0x840, 0x015D0166)
  207. MXC_DCD_ITEM(48, MMDC_P0_BASE_ADDR + 0x848, 0x4B4C504D)
  208. MXC_DCD_ITEM(49, MMDC_P1_BASE_ADDR + 0x848, 0x494C4F48)
  210. MXC_DCD_ITEM(50, MMDC_P0_BASE_ADDR + 0x850, 0x3F3F2E31)
  211. MXC_DCD_ITEM(51, MMDC_P1_BASE_ADDR + 0x850, 0x2B35382B)
  213. MXC_DCD_ITEM(52, MMDC_P0_BASE_ADDR + 0x81c, 0x33333333)
  214. MXC_DCD_ITEM(53, MMDC_P0_BASE_ADDR + 0x820, 0x33333333)
  215. MXC_DCD_ITEM(54, MMDC_P0_BASE_ADDR + 0x824, 0x33333333)
  216. MXC_DCD_ITEM(55, MMDC_P0_BASE_ADDR + 0x828, 0x33333333)
  217. MXC_DCD_ITEM(56, MMDC_P1_BASE_ADDR + 0x81c, 0x33333333)
  218. MXC_DCD_ITEM(57, MMDC_P1_BASE_ADDR + 0x820, 0x33333333)
  219. MXC_DCD_ITEM(58, MMDC_P1_BASE_ADDR + 0x824, 0x33333333)
  220. MXC_DCD_ITEM(59, MMDC_P1_BASE_ADDR + 0x828, 0x33333333)
  222. MXC_DCD_ITEM(60, MMDC_P0_BASE_ADDR + 0x8b8, 0x00000800)
  223. MXC_DCD_ITEM(61, MMDC_P1_BASE_ADDR + 0x8b8, 0x00000800)
  224. # MMDC init:
  225. # in DDR3, 64-bit mode, only MMDC0 is initiated:
  226. MXC_DCD_ITEM(62, MMDC_P0_BASE_ADDR + 0x004, 0x0002002D)
  227. MXC_DCD_ITEM(63, MMDC_P0_BASE_ADDR + 0x008, 0x00333030)
  228. MXC_DCD_ITEM(64, MMDC_P0_BASE_ADDR + 0x00c, 0x3F435313)
  229. MXC_DCD_ITEM(65, MMDC_P0_BASE_ADDR + 0x010, 0xB66E8B63)
  230. MXC_DCD_ITEM(66, MMDC_P0_BASE_ADDR + 0x014, 0x01FF00DB)
  231. MXC_DCD_ITEM(67, MMDC_P0_BASE_ADDR + 0x018, 0x00081740)
  233. MXC_DCD_ITEM(68, MMDC_P0_BASE_ADDR + 0x01c, 0x00008000)
  234. MXC_DCD_ITEM(69, MMDC_P0_BASE_ADDR + 0x02c, 0x000026d2)
  235. MXC_DCD_ITEM(70, MMDC_P0_BASE_ADDR + 0x030, 0x00431023)
  236. MXC_DCD_ITEM(71, MMDC_P0_BASE_ADDR + 0x040, 0x00000027)
  238. MXC_DCD_ITEM(72, MMDC_P0_BASE_ADDR + 0x000, 0x831A0000)
  240. # Initialize 2GB DDR3 - Micron MT41J128M
  241. MXC_DCD_ITEM(73, MMDC_P0_BASE_ADDR + 0x01c, 0x04008032)
  242. MXC_DCD_ITEM(74, MMDC_P0_BASE_ADDR + 0x01c, 0x00008033)
  243. MXC_DCD_ITEM(75, MMDC_P0_BASE_ADDR + 0x01c, 0x00048031)
  244. MXC_DCD_ITEM(76, MMDC_P0_BASE_ADDR + 0x01c, 0x05208030)
  245. MXC_DCD_ITEM(77, MMDC_P0_BASE_ADDR + 0x01c, 0x04008040)
  247. MXC_DCD_ITEM(78, MMDC_P0_BASE_ADDR + 0x020, 0x00005800)
  249. MXC_DCD_ITEM(79, MMDC_P0_BASE_ADDR + 0x818, 0x00011117)
  250. MXC_DCD_ITEM(80, MMDC_P1_BASE_ADDR + 0x818, 0x00011117)
  252. MXC_DCD_ITEM(81, MMDC_P0_BASE_ADDR + 0x004, 0x0002556d)
  253. MXC_DCD_ITEM(82, MMDC_P1_BASE_ADDR + 0x404, 0x00011006)
  254. MXC_DCD_ITEM(83, MMDC_P0_BASE_ADDR + 0x01c, 0x00000000)
  255. #endif
  256. #else  /* i.MX6Q */
  257. dcd_hdr:          .word 0x40a002D2 /* Tag=0xD2, Len=83*8 + 4 + 4, Ver=0x40 */
  258. write_dcd_cmd:    .word 0x049c02CC /* Tag=0xCC, Len=83*8 + 4, Param=0x04 */
  260. /* DCD */
  261. MXC_DCD_ITEM(1, IOMUXC_BASE_ADDR + 0x798, 0x000C0000)
  262. MXC_DCD_ITEM(2, IOMUXC_BASE_ADDR + 0x758, 0x00000000)
  264. MXC_DCD_ITEM(3, IOMUXC_BASE_ADDR + 0x588, 0x00000030)
  265. MXC_DCD_ITEM(4, IOMUXC_BASE_ADDR + 0x594, 0x00000030)
  267. MXC_DCD_ITEM(5, IOMUXC_BASE_ADDR + 0x56c, 0x00000030)
  268. MXC_DCD_ITEM(6, IOMUXC_BASE_ADDR + 0x578, 0x00000030)
  269. MXC_DCD_ITEM(7, IOMUXC_BASE_ADDR + 0x74c, 0x00000030)
  271. MXC_DCD_ITEM(8, IOMUXC_BASE_ADDR + 0x57c, 0x00000030)
  273. MXC_DCD_ITEM(9, IOMUXC_BASE_ADDR + 0x58c, 0x00000000)
  274. MXC_DCD_ITEM(10, IOMUXC_BASE_ADDR + 0x59c, 0x00000030)
  275. MXC_DCD_ITEM(11, IOMUXC_BASE_ADDR + 0x5a0, 0x00000030)
  276. MXC_DCD_ITEM(12, IOMUXC_BASE_ADDR + 0x78c, 0x00000030)
  278. MXC_DCD_ITEM(13, IOMUXC_BASE_ADDR + 0x750, 0x00020000)
  280. MXC_DCD_ITEM(14, IOMUXC_BASE_ADDR + 0x5a8, 0x00000030)
  281. MXC_DCD_ITEM(15, IOMUXC_BASE_ADDR + 0x5b0, 0x00000030)
  282. MXC_DCD_ITEM(16, IOMUXC_BASE_ADDR + 0x524, 0x00000030)
  283. MXC_DCD_ITEM(17, IOMUXC_BASE_ADDR + 0x51c, 0x00000030)
  284. MXC_DCD_ITEM(18, IOMUXC_BASE_ADDR + 0x518, 0x00000030)
  285. MXC_DCD_ITEM(19, IOMUXC_BASE_ADDR + 0x50c, 0x00000030)
  286. MXC_DCD_ITEM(20, IOMUXC_BASE_ADDR + 0x5b8, 0x00000030)
  287. MXC_DCD_ITEM(21, IOMUXC_BASE_ADDR + 0x5c0, 0x00000030)
  289. MXC_DCD_ITEM(22, IOMUXC_BASE_ADDR + 0x774, 0x00020000)
  291. MXC_DCD_ITEM(23, IOMUXC_BASE_ADDR + 0x784, 0x00000030)
  292. MXC_DCD_ITEM(24, IOMUXC_BASE_ADDR + 0x788, 0x00000030)
  293. MXC_DCD_ITEM(25, IOMUXC_BASE_ADDR + 0x794, 0x00000030)
  294. MXC_DCD_ITEM(26, IOMUXC_BASE_ADDR + 0x79c, 0x00000030)
  295. MXC_DCD_ITEM(27, IOMUXC_BASE_ADDR + 0x7a0, 0x00000030)
  296. MXC_DCD_ITEM(28, IOMUXC_BASE_ADDR + 0x7a4, 0x00000030)
  297. MXC_DCD_ITEM(29, IOMUXC_BASE_ADDR + 0x7a8, 0x00000030)
  298. MXC_DCD_ITEM(30, IOMUXC_BASE_ADDR + 0x748, 0x00000030)
  300. MXC_DCD_ITEM(31, IOMUXC_BASE_ADDR + 0x5ac, 0x00000030)
  301. MXC_DCD_ITEM(32, IOMUXC_BASE_ADDR + 0x5b4, 0x00000030)
  302. MXC_DCD_ITEM(33, IOMUXC_BASE_ADDR + 0x528, 0x00000030)
  303. MXC_DCD_ITEM(34, IOMUXC_BASE_ADDR + 0x520, 0x00000030)
  304. MXC_DCD_ITEM(35, IOMUXC_BASE_ADDR + 0x514, 0x00000030)
  305. MXC_DCD_ITEM(36, IOMUXC_BASE_ADDR + 0x510, 0x00000030)
  306. MXC_DCD_ITEM(37, IOMUXC_BASE_ADDR + 0x5bc, 0x00000030)
  307. MXC_DCD_ITEM(38, IOMUXC_BASE_ADDR + 0x5c4, 0x00000030)
  309. MXC_DCD_ITEM(39, MMDC_P0_BASE_ADDR + 0x800, 0xA1390003)
  311. MXC_DCD_ITEM(40, MMDC_P0_BASE_ADDR + 0x80c, 0x001F001F)
  312. MXC_DCD_ITEM(41, MMDC_P0_BASE_ADDR + 0x810, 0x001F001F)
  313. MXC_DCD_ITEM(42, MMDC_P1_BASE_ADDR + 0x80c, 0x001F001F)
  314. MXC_DCD_ITEM(43, MMDC_P1_BASE_ADDR + 0x810, 0x001F001F)
  316. MXC_DCD_ITEM(44, MMDC_P0_BASE_ADDR + 0x83c, 0x4333033F)
  317. MXC_DCD_ITEM(45, MMDC_P0_BASE_ADDR + 0x840, 0x032C031D)
  318. MXC_DCD_ITEM(46, MMDC_P1_BASE_ADDR + 0x83c, 0x43200332)
  319. MXC_DCD_ITEM(47, MMDC_P1_BASE_ADDR + 0x840, 0x031A026A)
  320. MXC_DCD_ITEM(48, MMDC_P0_BASE_ADDR + 0x848, 0x4D464746)
  321. MXC_DCD_ITEM(49, MMDC_P1_BASE_ADDR + 0x848, 0x47453F4D)
  322. MXC_DCD_ITEM(50, MMDC_P0_BASE_ADDR + 0x850, 0x3E434440)
  323. MXC_DCD_ITEM(51, MMDC_P1_BASE_ADDR + 0x850, 0x47384839)
  325. MXC_DCD_ITEM(52, MMDC_P0_BASE_ADDR + 0x81c, 0x33333333)
  326. MXC_DCD_ITEM(53, MMDC_P0_BASE_ADDR + 0x820, 0x33333333)
  327. MXC_DCD_ITEM(54, MMDC_P0_BASE_ADDR + 0x824, 0x33333333)
  328. MXC_DCD_ITEM(55, MMDC_P0_BASE_ADDR + 0x828, 0x33333333)
  329. MXC_DCD_ITEM(56, MMDC_P1_BASE_ADDR + 0x81c, 0x33333333)
  330. MXC_DCD_ITEM(57, MMDC_P1_BASE_ADDR + 0x820, 0x33333333)
  331. MXC_DCD_ITEM(58, MMDC_P1_BASE_ADDR + 0x824, 0x33333333)
  332. MXC_DCD_ITEM(59, MMDC_P1_BASE_ADDR + 0x828, 0x33333333)
  334. MXC_DCD_ITEM(60, MMDC_P0_BASE_ADDR + 0x8b8, 0x00000800)
  335. MXC_DCD_ITEM(61, MMDC_P1_BASE_ADDR + 0x8b8, 0x00000800)
  337. MXC_DCD_ITEM(62, MMDC_P0_BASE_ADDR + 0x004, 0x00020036)
  338. MXC_DCD_ITEM(63, MMDC_P0_BASE_ADDR + 0x008, 0x09444040)
  339. MXC_DCD_ITEM(64, MMDC_P0_BASE_ADDR + 0x00c, 0x555A7975)
  340. MXC_DCD_ITEM(65, MMDC_P0_BASE_ADDR + 0x010, 0xFF538F64)
  341. MXC_DCD_ITEM(66, MMDC_P0_BASE_ADDR + 0x014, 0x01FF00DB)
  342. MXC_DCD_ITEM(67, MMDC_P0_BASE_ADDR + 0x018, 0x00001740)
  344. MXC_DCD_ITEM(68, MMDC_P0_BASE_ADDR + 0x01c, 0x00008000)
  345. MXC_DCD_ITEM(69, MMDC_P0_BASE_ADDR + 0x02c, 0x000026D2)
  346. MXC_DCD_ITEM(70, MMDC_P0_BASE_ADDR + 0x030, 0x005A1023)
  347. MXC_DCD_ITEM(71, MMDC_P0_BASE_ADDR + 0x040, 0x00000027)
  349. MXC_DCD_ITEM(72, MMDC_P0_BASE_ADDR + 0x000, 0x831A0000)
  351. MXC_DCD_ITEM(73, MMDC_P0_BASE_ADDR + 0x01c, 0x04088032)
  352. MXC_DCD_ITEM(74, MMDC_P0_BASE_ADDR + 0x01c, 0x00008033)
  353. MXC_DCD_ITEM(75, MMDC_P0_BASE_ADDR + 0x01c, 0x00048031)
  354. MXC_DCD_ITEM(76, MMDC_P0_BASE_ADDR + 0x01c, 0x09408030)
  355. MXC_DCD_ITEM(77, MMDC_P0_BASE_ADDR + 0x01c, 0x04008040)
  357. MXC_DCD_ITEM(78, MMDC_P0_BASE_ADDR + 0x020, 0x00005800)
  359. MXC_DCD_ITEM(79, MMDC_P0_BASE_ADDR + 0x818, 0x00011117)
  360. MXC_DCD_ITEM(80, MMDC_P1_BASE_ADDR + 0x818, 0x00011117)
  362. MXC_DCD_ITEM(81, MMDC_P0_BASE_ADDR + 0x004, 0x00025576)
  363. MXC_DCD_ITEM(82, MMDC_P0_BASE_ADDR + 0x404, 0x00011006)
  364. MXC_DCD_ITEM(83, MMDC_P0_BASE_ADDR + 0x01c, 0x00000000)
  366. #endif
  368. #endif

查看u-boot.lds可以了解uboot编译之后的布局

  1. OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
  2. OUTPUT_ARCH(arm)
  3. ENTRY(_start)
  4. SECTIONS
  5. {
  6. 	. = 0x00000000;
  8. 	. = ALIGN(4);
  9. 	.text	   :
  10. 	{
  11. 	  /* WARNING - the following is hand-optimized to fit within	*/
  12. 	  /* the sector layout of our flash chips!	XXX FIXME XXX	*/
  13. 	  board/freescale/mx6q_sabresd/flash_header.o	(.text.flasheader)		# flash_header.S
  14. 	  cpu/arm_cortexa8/start.o												# start.S
  15. 	  board/freescale/mx6q_sabresd/libmx6q_sabresd.a	(.text)
  16. 	  lib_arm/libarm.a		(.text)
  17. 	  net/libnet.a			(.text)
  18. 	  drivers/mtd/libmtd.a		(.text)
  19. 	  drivers/mmc/libmmc.a		(.text)
  21. 	  . = DEFINED(env_offset) ? env_offset : .;
  22. 	  common/env_embedded.o(.text)
  24. 	  *(.text)
  25. 	}
  27. 	. = ALIGN(4);
  28. 	.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
  30. 	. = ALIGN(4);
  31. 	.data : { *(.data) }
  33. 	. = ALIGN(4);
  34. 	.got : { *(.got) }
  36. 	. = .;
  37. 	__u_boot_cmd_start = .;
  38. 	.u_boot_cmd : { *(.u_boot_cmd) }
  39. 	__u_boot_cmd_end = .;
  41. 	. = ALIGN(4);
  42. 	_end_of_copy = .; /* end_of ROM copy code here */
  44. 	/* Extend to align to 0x1000, then put the Hab Data */
  45. 	. = ALIGN(0x1000);
  46. 	__hab_data = .;
  47. 	. = . + 0x2000;
  48. 	__data_enc_key = .;
  49. 	/* actually, only 64bytes are needed, but this generates
  50. 		a size multiple of 512bytes, which is optimal for SD boot */
  51. 	. = . + 0x200;
  52. 	__hab_data_end = .;
  53. 	/* End of Hab Data, Place it before BSS section */
  55. 	__bss_start = .;
  56. 	.bss : { *(.bss) }
  57. 	_end = .;
  58. }

查看编译uboot生成的System.map也能够知道大概的分布情况。

System.map

  1. # 对应flash_header.S中的内容，地址连续
  2. 27800400 t ivt_header		# 首先是ivt header
  3. 27800404 t app_code_jump_v	# _start
  4. 27800408 t reserv1
  5. 2780040c t dcd_ptr
  6. 27800410 t boot_data_ptr
  7. 27800414 t self_ptr
  8. 27800418 t app_code_csf
  9. 2780041c t reserv2
  10. 27800420 t boot_data
  11. 27800424 t image_len
  12. 27800428 t plugin
  13. 2780042c t dcd_hdr
  14. 27800430 t write_dcd_cmd
  15. # 对应 flash_header.S中的内容，每个dcd_node大小8字节。
  16. # 前4个字节存放寄存器的地址，后4个字节设置寄存器的值。
  17. 27800434 t dcd_node_1
  18. 2780043c t dcd_node_2
  19. 27800444 t dcd_node_3
  20. 2780044c t dcd_node_4
  21. 27800454 t dcd_node_5
  22. 2780045c t dcd_node_6
  23. 27800464 t dcd_node_7
  24. 2780046c t dcd_node_8
  25. 27800474 t dcd_node_9
  26. 2780047c t dcd_node_10
  27. 27800484 t dcd_node_11
  28. 2780048c t dcd_node_12
  29. 27800494 t dcd_node_13
  30. 2780049c t dcd_node_14
  31. 278004a4 t dcd_node_15
  32. 278004ac t dcd_node_16
  33. 278004b4 t dcd_node_17
  34. 278004bc t dcd_node_18
  35. 278004c4 t dcd_node_19
  37. ......
  39. # uboot, start函数。对应cpu/arm_cortexa8/start.S中的内容
  40. 278006e0 T _start
  41. 27800700 t _undefined_instruction
  42. 27800704 t _software_interrupt
  43. 27800708 t _prefetch_abort
  44. 2780070c t _data_abort
  45. 27800710 t _not_used
  46. 27800714 t _irq
  47. 27800718 t _fiq
  48. 2780071c t _pad
  49. 27800720 T _end_vect
  50. 27800720 t _TEXT_BASE
  51. 27800724 T _armboot_start
  52. 27800728 T _bss_start
  53. 2780072c T _bss_end
  54. 27800730 t reset
  55. ...

imx6开启启动之后，运行板子上的ROM程序。ROM确定启动的设备，进行一些初始化，然后读取IVT，进行寄存器初始化,最后运行uboot/cpu/arm_cortexa8/start.S中的_start函数。

IVT中记录了寄存器的地址和要设置的值，以及uboot的_start函数。

初始化完成之后，最后运行uboot/cpu/arm_cortexa8/start.S中的 _start函数，进行uboot的初始化。

start.S

  1. .global _start
  2. _start: b   reset
  3.     ldr pc, _undefined_instruction
  4.     ldr pc, _software_interrupt
  5.     ldr pc, _prefetch_abort
  6.     ldr pc, _data_abort
  7.     ldr pc, _not_used
  8.     ldr pc, _irq
  9.     ldr pc, _fiq

Tony Liu

2016-12-20, Shenzhen

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