Verilog之基本算数运算

1.加减法

module addsub
(
    input [:] dataa,
    input [:] datab,
    input add_sub,      // if this is 1, add; else subtract
    input clk,
    output reg [:] result
);            

    always @ (posedge clk)
    begin
        if (add_sub)
            result <= dataa + datab;           //or "assign {cout,sum}=dataa+datab;"
        else
            result <= dataa - datab;
    end        

endmodule            

补码不仅可以执行正值和负值转换，其实补码存在的意义，就是避免计算机去做减法的操作。

　　1101       -3 补
+   1000        8
    01015
假设 -3 + 8，只要将 -3 转为补码形式，亦即 0011 => 1101，然后和 8，亦即 1000 相加
就会得到 5，亦即 0101。至于溢出的最高位可以无视掉

2.乘法

module mult(outcome,a,b);
parameter SIZE=;
input[SIZE:] a,b;
output reg[*SIZE:] outcome;
integer i;
always @(a or b)
        begin outcome<=;
        for(i=,i<=SIZE;i=i+)
        if(b[i]) outcome<=outcome+(a<<(i-));
        end
endmodule

乘法-带符号位，在初始化之际，取乘数和被乘数的正负关系，然后取被乘数和乘数的正值。输出结果根据正负关系取得。

          else if( Start_Sig )
              case( i )                

                    :
                     begin    

                         isNeg <= Multiplicand[] ^ Multiplier[];
                          Mcand <= Multiplicand[] ? ( ~Multiplicand + 'b1 ) : Multiplicand;
                          Mer <= Multiplier[] ? ( ~Multiplier + 'b1 ) : Multiplier;
                          Temp <= 'd0;
                          i <= i + 'b1;

                     end    

                     1: // Multipling
                     if( Mer == 0 ) i <= i + 1'b1;
                     else begin Temp <= Temp + Mcand; Mer <= Mer - 1'b1; end                        //浪费时钟

                     :
                     begin isDone <= 'b1; i <= i + 1'b1; end    

                     :
                     begin isDone <= 'b0; i <= 2'd0; end    

                endcase        

    /*************************/                        

     assign Done_Sig = isDone;
     assign Product = isNeg ? ( ~Temp + 'b1 ) : Temp;                    

     /*************************/                    

endmodule                        

乘法器.vt示例

`timescale  ps/  ps
module multiplier_module_simulation();

    reg CLK;
     reg RSTn;

     reg Start_Sig;
    reg [:] Multiplicand;
    reg [:] Multiplier;

    wire Done_Sig;
    wire [:]Product;

     /***********************************/

    initial
    begin      

        RSTn = ; #; RSTn = ;
         CLK = ; forever # CLK = ~CLK;

     end

     /***********************************/

    multiplier_module U1
     (
        .CLK(CLK),
         .RSTn(RSTn),
         .Start_Sig(Start_Sig),
        .Multiplicand(Multiplicand),
        .Multiplier(Multiplier),
         .Done_Sig(Done_Sig),
        .Product(Product)
    );

     /***********************************/

     reg [:]i;

    always @ ( posedge CLK or negedge RSTn )
        if( !RSTn )
            begin
                    i <= 'd0;
                    Start_Sig <= 'b0;
                Multiplicand <= 'd0;
                  Multiplier <= 'd0;
            end
          else
              case( i )

                    : // Multiplicand = 10 , Multiplier = 2
                     if( Done_Sig ) begin Start_Sig <= 'b0; i <= i + 1'b1; end
                     else begin Multiplicand <= 'd10; Multiplier <= 8'd2; Start_Sig <= 'b1; end

                     : // Multiplicand = 2 , Multiplier = 10
                     if( Done_Sig ) begin Start_Sig <= 'b0; i <= i + 1'b1; end
                     else begin Multiplicand <= 'd2; Multiplier <= 8'd10; Start_Sig <= 'b1; end

                     : // Multiplicand = 11 , Multiplier = -5
                     if( Done_Sig ) begin Start_Sig <= 'b0; i <= i + 1'b1; end
                     else begin Multiplicand <= 'd11; Multiplier <= 8'b11111011; Start_Sig <= 'b1; end

                    : // Multiplicand = -5 , Multiplier = -11
                     if( Done_Sig ) begin Start_Sig <= 'b0; i <= i + 1'b1; end
                     else begin Multiplicand <= 'b11111011; Multiplier <= 8'b11110101; Start_Sig <= 'b1; end

                    :
                     begin i <= 'd4; end

                endcase

    /***********************************/

endmodule

循环除法器

module streamlined_divider_module
(
    input CLK,
     input RSTn,

     input Start_Sig,
     input [:]Dividend,
     input [:]Divisor,

     output Done_Sig,
     output [:]Quotient,
     output [:]Reminder,

     /**************************/

     output [:]SQ_Diff,
     output [:]SQ_Temp
);

    /******************************/

     reg [:]i;
     reg [:]s;
     reg [:]Temp;
     reg [:]Diff;
     reg isNeg;
     reg isDone;

     always @ ( posedge CLK or negedge RSTn )
         if( !RSTn )
              begin
                    i <= 'd0;
                     s <= 'd0;
                     Temp <= 'd0;
                     Diff <= 'd0;
                     isNeg <= 'b0;
                     isDone <= 'b0;
                end
          else if( Start_Sig )
              case( i )

                    :
                     begin

                         isNeg <= Dividend[] ^ Divisor[];
                          s <= Divisor[] ? { 'b1, Divisor } : { 1'b1 , ~Divisor + 'b1 };
                          Temp <= Dividend[] ? { 'd0 , ~Dividend + 1'b1 } : { 'd0 , Dividend };
                          Diff <= 'd0;
                          i <= i + 'b1;

                     end

                     ,,,,,,,:
                     begin 

                          Diff = Temp + { s , 'd0 }; 

                          if( Diff[] ) Temp <= { Temp[:] , 'b0 };
                        else Temp <= { Diff[:] , 'b1 }; 

                         i <= i + 'b1;

                end

                     :
                     begin isDone <= 'b1; i <= i + 1'b1; end

                     :
                     begin isDone <= 'b0; i <= 2'd0; end

                endcase

    /*********************************/

     assign Done_Sig = isDone;
     assign Quotient = isNeg ? ( ~Temp[:] + 'b1 ) : Temp[7:0];
     assign Reminder = Temp[:];

     /**********************************/

     assign SQ_Diff = Diff;
     assign SQ_Temp = Temp;

     /**********************************/

endmodule