verilog之task用法实例

该用法的代码源自夏宇闻老师的教材。

源代码：

 module traffic_lights;
 reg clock, red, amber, green;
 parameter  on = , off = , red_tics = ,
 amber_tics = , green_tics = ;
 // initialize colors.
 initial red = off;
 initial amber = off;
 initial green = off;
 always begin  // sequence to control the lights.
     red = on;   // turn red light on
     light(red, red_tics);         // and wait.
     green = on;  // turn green light on
     light(green, green_tics);     // and wait.
     amber = on;  // turn amber light on
     light(amber, amber_tics);     // and wait.
 end
 // task to wait for 'tics' positive edge clocks
 // before turning 'color' light off.
 task light;
     output color;
     input [:] tics;
     begin
         repeat (tics) @ (posedge clock);
         color = off;  // turn light off.
     end
 endtask
 always begin  // waveform for the clock.
     # clock = ;
     # clock = ;
 end
 endmodule // traffic_lights.

测试代码run.do：

 vlib work
 vlog -novopt traffic_lights.v
 vsim -voptargs=+acc work.traffic_lights
 add wave *

 run 1000us

测试代码自动运行run.bat：

 vsim -do run.do

运行结果如下：