一个简单的Verilog计数器模型

一个简单的Verilog计数器模型

功能说明：

• 向上计数
• 向下计数
• 预装载值

一、代码

1.counter代码(counter.v)

 module counter(
                input                    clk,
                input                    rstn,
                input                    go,    //使能启动信号
                input       [:]        data,  //预装载数据
                input                    load,  //预装载信号
                input                    dir,   //计数方向

                output reg  [:]      cnt,  //计数输出值
                output                 overfloat,  //向上溢出
                output                 downfloat   //向下溢出
                );

 reg    [:]   cnt_next;
 reg    [:]   data_shadow;

 always@(posedge clk,negedge rstn)
 begin
     if(!rstn)
         data_shadow <= 'b0;
     else
         data_shadow <= data;
 end

 always@(posedge clk,negedge rstn)
 begin
     if(!rstn)
         cnt <= 'b0;
     else
         cnt <= cnt_next;
 end

 always@(*)
 begin
     if(go)
     begin
         if(load && overfloat)
             cnt_next = 'b0;
         else if(load && downfloat)
             cnt_next = data_shadow;
         else
             if(dir)
                 cnt_next = cnt + 'b1;
             else
                 cnt_next = cnt - 'b1;
     end
     else
         cnt_next = cnt;
 end

 assign overfloat = (dir && (cnt == data_shadow));
 assign downfloat = (!dir && (cnt == 'b0));

 endmodule

2、testbench(counter_tb.v)

 module counter_tb;

 reg             clk;
 reg             rstn;
 reg             go;
 reg   [:]     data;
 reg             load;
 reg             dir;

 wire  [:]    cnt;
 wire           overfloat;
 wire           downfloat;

 initial
 begin
     clk =  ;

     rstn = ;
     repeat()  @(posedge clk);
     rstn = ;
     repeat()  @(posedge clk);
     rstn = ;

     go   = ;
     data = 'b0000;
     load = ;
     dir  = ;

     @(posedge clk);
     data = 'b0000;
     load = ;
     dir  = ;
     go   = ;

     repeat()  @(posedge clk);
     data = 'b0000;
     load = ;
     dir  = ;
     go   = ;

     repeat()  @(posedge clk);
     data = 'b1001;
     load = ;
     dir  = ;
     go   = ;

     repeat()  @(posedge clk);
     data = 'b1001;
     load = ;
     dir  = ;
     go   = ;

     repeat()  @(posedge clk);
     $finish;
 end

 always # clk = ~clk;

 counter u_counter(
                   .clk(clk),
                   .rstn(rstn),
                   .go(go),
                   .data(data),
                   .load(load),
                   .dir(dir),
                   .cnt(cnt),
                   .overfloat(overfloat),
                   .downfloat(downfloat)
                   );

 endmodule

二、仿真结果

向下计数

向上计数

预装载向下计数

预装载向上计数