【代码】verilog之：按键消抖

此模块完美运行

/*--------------------------------------------------------------------------------------
-- Filename ﹕ show_ctrl.v
-- Author ﹕tony-ning
-- Description ﹕按键消抖
-- Called by ﹕Top module
-- Revision History ﹕15-10-16
-- Revision 1.0
-- Company ﹕
-- Copyright(c)  All right reserved
---------------------------------------------------------------------------------------*/

module debounce_module
(
    CLK, //采集时钟，40Hz
    RSTn, //系统复位信号
    BUTTON_IN, //按键输入信号
    BUTTON_OUT //消抖后的输出信号
);
    input CLK;
    input RSTn;
    input BUTTON_IN;
    output BUTTON_OUT;

    reg key_reg1,key_reg2,key_out;
    reg [:]count2;

    always @( posedge CLK)//CLK 50M
        begin
        count2<=count2+;
        if(count2==)
        begin
            key_reg1<=BUTTON_IN;
            count2<=;
        end
        key_reg2<=key_reg1;
        key_out<=key_reg2&(!key_reg1);
     end

    assign BUTTON_OUT = key_out;

endmodule

此模块存在一个时钟匹配问题，下个接口按键动作只需要一个时钟脉冲，可此处产生的是10ms的脉冲

 /*--------------------------------------------------------------------------------------
 -- Filename ﹕ show_ctrl.v
 -- Author ﹕tony-ning
 -- Description ﹕按键消抖
 -- Called by ﹕Top module
 -- Revision History ﹕15-10-16
 -- Revision 1.0
 -- Company ﹕
 -- Copyright(c)  All right reserved
 ---------------------------------------------------------------------------------------*/
 module debounce_module
 (
     CLK, //采集时钟，40Hz
     RSTn, //系统复位信号
     BUTTON_IN, //按键输入信号
     BUTTON_OUT //消抖后的输出信号
 );
     input CLK;
     input RSTn;
     input BUTTON_IN;
     output BUTTON_OUT;
 reg [:]cnt;//分频计数器
     reg CLK40HZ;//分频时钟
     reg BUTTON_IN_Q, BUTTON_IN_2Q, BUTTON_IN_3Q;

     always@(posedge CLK ) //时钟分频
     begin
         if(!RSTn)
             cnt<=;
         else if(cnt=='d312_499)   //产生40Hz时钟脉冲
                 begin
                 cnt<=;
                 CLK40HZ<=~CLK40HZ;//40hz时钟输出
                 end
             else begin
                 cnt<=cnt+;
                 end
     end

     always @(posedge CLK40HZ or negedge RSTn)
     begin
         if(~RSTn)
             begin
             BUTTON_IN_Q <= 'b1;
             BUTTON_IN_2Q <= 'b1;
             BUTTON_IN_3Q <= 'b1;
             end
         else
             begin
             BUTTON_IN_Q <= BUTTON_IN;
             BUTTON_IN_2Q <= BUTTON_IN_Q;
             BUTTON_IN_3Q <= BUTTON_IN_2Q;
             end
     end

     wire BUTTON_OUT = BUTTON_IN_2Q | BUTTON_IN_3Q;
 endmodule

此模块想用状态机写，但仍有问题

 /*--------------------------------------------------------------------------------------
 -- Filename ﹕ show_ctrl.v
 -- Author ﹕tony-ning
 -- Description ﹕按键消抖
 -- Called by ﹕Top module
 -- Revision History ﹕15-10-16
 -- Revision 1.0
 -- Company ﹕
 -- Copyright(c)  All right reserved
 ---------------------------------------------------------------------------------------*/

 module debounce_module
 (
     CLK, RSTn, KEY_set,KEY_add,Pin_set, Pin_add
 );

      input CLK;
      input RSTn;
      input KEY_set;
      input KEY_add;
      output Pin_set;
      output Pin_add;

      reg p='b0;//按键状态
      reg [:]cntt;
      reg k1f1,k1f2;//KEY_set上升沿检测
      reg k2f1,k2f2;//KEY_add上升沿检测

      parameter s_wait='b0;//等待按键状态
      parameter s_delay='b1;//按下延时状态

      assign Pin_set=k1f2&!k1f1;//读取按键下降沿
      assign Pin_add=k2f2&!k2f1;

      always @ ( posedge CLK or negedge RSTn )//按键消抖状态机
          if( !RSTn )
               begin
                   cntt <= 'd0;
                   p <= s_wait;
                 end
         else case(p)
             s_wait: begin
                         k1f1<=KEY_set;//记录按键值
                         k1f2<=k1f1;

                         k2f1<=KEY_add;
                         k2f2<=k2f1;

                         if(Pin_set| Pin_add)//当按下，切换到延时并按键只输出一个时钟脉冲
                         begin
                             p<=s_delay;
                             k1f1<=;
                             k1f2<=;

                             k2f1<=;
                             k2f2<=;
                         end
                     end
             s_delay:if(cntt=='d249_999)   //延时T=10ms
                         begin
                         cntt<=;
                         p<=s_wait;
                         end
                     else begin
                         cntt<=cntt+;
                         end

             endcase

 endmodule