PW试验-----verilog

PWM，脉冲宽度调制。顾名思义，是通过调制脉冲的宽度，即占空比，来实现的。可是使占空比逐渐由最小增加到最大，也可以使占空比由最大减少到最小来实现不同的现象。若用LED灯来显示现象，则可以称作：LED呼吸灯；

简单的代码如下：

    /********************************Copyright**************************************
    **----------------------------File information--------------------------
    ** File name  :led_pwm.v
    ** CreateDate :2015.03
    ** Funtions   :pwm的试验，用led灯来显示pwm的效果
    ** Operate on :M5C06N3L114C7
    ** Copyright  :All rights reserved.
    ** Version    :V1.0
    **---------------------------Modify the file information----------------
    ** Modified by   :
    ** Modified data :
    ** Modify Content:
    *******************************************************************************/

     module  led_pwm  (
                 clk,
                 rst_n,

                             pwm_out
                 );
     input          clk;         /* 24Mhz */
     input          rst_n;
    // wire           rst_n;
     output         pwm_out;

    // assign  rst_n = 1;
     //-------------------------------------
     /* ius */
     localparam  t_1us = 'd23;
    // localparam  t_1us = 5'd6;     /* 用于测试 */
     reg      [:]    cnt1;
     always @(posedge clk or negedge rst_n)
     begin
      if(!rst_n)
       begin
          cnt1 <=  ;
        end
      else
        begin
           if(cnt1 == t_1us)
                    cnt1 <= ;
                  else
                        cnt1 <= cnt1 + ;
        end
      end

     /* 1ms */
     localparam  t_1ms = 'd999;
    // localparam  t_1ms = 10'd19;  /* 用于测试 */
     reg      [:]    cnt2;
     always @(posedge clk or negedge rst_n)
     begin
      if(!rst_n)
       begin
          cnt2 <=  ;
        end
      else
        begin
           if(cnt1 == t_1us)
                   begin
                          if(cnt2 == t_1ms)
                                cnt2 <= ;
                             else
                                 cnt2 <= cnt2 + ;
                        end
                  else
                        cnt2 <= cnt2;
        end
      end

     /* 1s */
     localparam  t_1s = 'd999;
    // localparam  t_1s = 10'd19;        /* 用于测试 */
     reg      [:]    cnt3;
     always @(posedge clk or negedge rst_n)
     begin
      if(!rst_n)
       begin
          cnt3 <= ;
        end
      else
        begin
           if((cnt1 == t_1us)&&(cnt2 == t_1ms))
                   begin
                          if(cnt3 == t_1s)
                                 cnt3 <= ;
                             else
                                 cnt3 <= cnt3 + ;
                        end
                  else
                        cnt3 <= cnt3;
        end
      end

     reg           flag;
     always @(posedge clk or negedge rst_n)
     begin
      if(!rst_n)
       begin
          flag <= ;
        end
      else if((cnt1 == t_1us)&&(cnt2 == t_1ms)&&(cnt3 == t_1s))
        begin
           flag <= ~flag;
        end
        else
            flag <= flag;
      end

     assign pwm_out = flag?((cnt2 < cnt3)?:):((cnt2 < cnt3)?:);

    endmodule

仿真验证代码：

    /********************************Copyright**************************************
    **----------------------------File information--------------------------
    ** File name  :led_pwm_tb.v
    ** CreateDate :2015.03
    ** Funtions   : led_pwm  的测试文件
    ** Operate on :M5C06N3L114C7
    ** Copyright  :All rights reserved.
    ** Version    :V1.0
    **---------------------------Modify the file information----------------
    ** Modified by   :
    ** Modified data :
    ** Modify Content:
    *******************************************************************************/

     module led_pwm_tb;
     reg        clk;
     reg        rst_n;

     wire       pwm_out;

    led_pwm  led_pwm_1(
                 .clk,
                 .rst_n,

                             .pwm_out
                 ); 

        localparam  tck = ;
        localparam  t = /tck;
        always
            #(t/)   clk = ~clk;

        initial
          begin
           clk = ;
             rst_n = ;

             #(*t)  rst_n = ;

          end

        endmodule

仿真结果：