基于FPGA的IIR滤波器

                                                        by方阳

版权声明：本文为博主原创文章，转载请指明转载地址

http://www.cnblogs.com/fydeblog/p/6748998.html

1.说明

写了那么多数字图像处理的，再写点其他的吧，今天写点FPGA的东西，是之前EDA做的综合大实验，拿出来和大家分享分享！

先说一下，此篇文章是基于你有IIR滤波器的原理和FPGA语言（也就是Verilog HDL）基础上的！至于IIR滤波器的原理和Verilog HDL语言，我这里就不说了，网上有一大堆的资料可以观看，IIR可以看数字信号处理的书或直接百度，Verilog HDL推荐《Hello,FPGA》!

申明一下，这边博客很长，请做好心理准备！！！

要感谢的人：感谢电子发烧网的牛哥哥要炸天的指导，感谢小梅哥的指导，感谢Hello FPGA团队的书籍！！！感谢，感谢，感谢！！！

说明：这个IIR滤波器我是用小梅哥的芯航线FPGA开发板——cyclone IV E EP4CE10F1708实现的，还用了他的ADDA模块——集成TLC1544 ADC采集芯片和TLC5620 DAC 输出芯片，软件平台是quartus13.0，测试用的是信号发生器和示波器。

这个共有一个顶层文件，十一个子文件，子文件其中一个是IIR滤波器的顶层文件。拓扑图如下：

2.参考代码

相应的代码如下

2.1 顶层文件

IIR_FY_TOP.V

  1. module IIR_FY_TOP
  2. (
  3.     Clk,
  4.     Rst_n,
  5.  
  6.     TLC5620_CLK,
  7.     TLC5620_DATA,
  8.     TLC5620_LOAD,
  9.     TLC5620_LDAC,
  10.  
  11.     TLV1544_SDO,
  12.     TLV1544_SDI,
  13.     TLV1544_SCLK,
  14.     TLV1544_NCS,
  15.     TLV1544_FS,
  16.     TLV1544_EOC
  17.  
  18. );
  19.  
  20.     input Clk;
  21.     input Rst_n;
  22.  
  23.     output TLC5620_CLK;
  24.     output TLC5620_DATA;
  25.     output TLC5620_LOAD;
  26.     output TLC5620_LDAC;
  27.  
  28.     input TLV1544_SDO;
  29.     output TLV1544_SDI;
  30.     output TLV1544_SCLK;
  31.     output TLV1544_NCS;
  32.     output TLV1544_FS;
  33.     input TLV1544_EOC;
  34.  
  35.     wire AD_DONE;
  36.     wire [:]ADC_DATA;
  37.     wire DATA_Valid;
  38.     wire [:]CtrlWord;
  39.     wire signed[:] din;
  40.     wire signed[:] dout;
  41.  
  42.     TLV1544_CTRL TLV1544_CTRL0(
  43.  
  44.         .Clk(Clk),
  45.         .Rst_n(Rst_n),
  46.  
  47.         .Do_Conv('b1),    //开始转换使能信号
  48.         .AD_DONE(AD_DONE),    //转换完成信号
  49.         .ADC_CHSEL('b0),    //通道选择
  50.  
  51.         .ADC_DATA(ADC_DATA),    //采样结果
  52.         .DATA_Valid(DATA_Valid),
  53.  
  54.         .TLV1544_SDO(TLV1544_SDO),
  55.         .TLV1544_SDI(TLV1544_SDI),
  56.         .TLV1544_SCLK(TLV1544_SCLK),
  57.         .TLV1544_NCS(TLV1544_NCS),
  58.         .TLV1544_FS(TLV1544_FS),
  59.         .TLV1544_EOC(TLV1544_EOC)
  60.     );
  61.  
  62.     ADC_to_filter ADC_to_filter0(
  63.  
  64.     .ADC_DATA(ADC_DATA),
  65.     .din(din)
  66.  
  67.     );
  68.  
  69.      myiir myiir0(
  70.         .rst(Rst_n),
  71.         .clk(Clk),
  72.         .din(din),
  73.         .dout(dout),
  74.         .din_valid(DATA_Valid),
  75.         .dout_valid()
  76.         );
  77.  
  78.     filter_to_DAC filter_to_DAC0(
  79.           .dout(dout),
  80.           .CtrlWord(CtrlWord)
  81.         );
  82.  
  83.         TLC5620_CTRL TLC5620_CTRL0(
  84.         .Clk(Clk),
  85.         .Rst_n(Rst_n),
  86.         .UpdateReq('b1),
  87.         .CtrlWord(CtrlWord),
  88.  
  89.         .UpdateDone(),
  90.         .TLC5620_CLK(TLC5620_CLK),
  91.         .TLC5620_DATA(TLC5620_DATA),
  92.         .TLC5620_LOAD(TLC5620_LOAD),
  93.         .TLC5620_LDAC(TLC5620_LDAC)
  94.     );        
  95.  
  96. endmodule

2.2 TLV1544驱动

TLV1544_CTRL.V

  1. module TLV1544_CTRL(
  2.  
  3.     Clk,
  4.     Rst_n,
  5.  
  6.     Do_Conv,    //开始转换使能信号
  7.     AD_DONE,    //转换完成信号
  8.     ADC_CHSEL,    //通道选择
  9.  
  10.     ADC_DATA,    //采样结果
  11.     DATA_Valid,
  12.  
  13.     TLV1544_SDO,
  14.     TLV1544_SDI,
  15.     TLV1544_SCLK,
  16.     TLV1544_NCS,
  17.     TLV1544_FS,
  18.     TLV1544_EOC
  19. );
  20.  
  21.     input Clk;
  22.     input Rst_n;
  23.     input Do_Conv;    //开始转换使能信号
  24.  
  25.     input [:]ADC_CHSEL;    //通道选择
  26.  
  27.     output reg [:]ADC_DATA;    //采样结果
  28.     output reg AD_DONE;    //转换完成信号
  29.     output reg DATA_Valid;
  30.  
  31.     input TLV1544_SDO;
  32.     input TLV1544_EOC;
  33.     output reg TLV1544_SDI;
  34.     output reg TLV1544_SCLK;
  35.     output reg TLV1544_NCS;
  36.     output wire TLV1544_FS;
  37.  
  38.     assign TLV1544_FS = 'b1;
  39.  
  40.     reg [:] LSM_CNT;//序列计数器
  41.     reg [:] rADC_DATA;
  42.  
  43.     always@(posedge Clk or negedge Rst_n)
  44.     if(!Rst_n)
  45.         LSM_CNT <= 'd0;
  46.     else if(LSM_CNT < && (TLV1544_EOC == 'b1) && (Do_Conv || LSM_CNT > 8'd0))
  47.         LSM_CNT <= LSM_CNT + 'b1;
  48.     else if(LSM_CNT <  && (TLV1544_EOC == 'b0))
  49.         LSM_CNT <= LSM_CNT;
  50.     else if(LSM_CNT ==  && (TLV1544_EOC == 'b1))
  51.         LSM_CNT <= 'd0;
  52.  
  53.     always@(posedge Clk or negedge Rst_n)
  54.     if(!Rst_n)begin
  55.         rADC_DATA <= 'd0;
  56.         TLV1544_SDI <= 'b0;
  57.         TLV1544_SCLK <= 'b0;
  58.         TLV1544_NCS <= 'b1;
  59.         AD_DONE <= 'b0;
  60.         DATA_Valid <= 'b0;
  61.         ADC_DATA <= 'd0;
  62.     end
  63.     else begin
  64.         case(LSM_CNT)
  65.             :
  66.                 begin
  67.                     rADC_DATA <= 'd0;
  68.                     TLV1544_SDI <= 'b0;
  69.                     TLV1544_SCLK <= 'b0;
  70.                     TLV1544_NCS <= 'b1;
  71.                     AD_DONE <= 'b0;
  72.                 end
  73.  
  74.             :
  75.                 begin
  76.                     TLV1544_NCS <= 'b0;
  77.                     TLV1544_SDI <= ADC_CHSEL[];
  78.                 end
  79.  
  80.             :
  81.                 begin
  82.                     TLV1544_SCLK <= 'b1;
  83.                     rADC_DATA[] <= TLV1544_SDO;
  84.                 end
  85.  
  86.             :
  87.                 begin
  88.                     TLV1544_SDI <= ADC_CHSEL[];
  89.                     TLV1544_SCLK <= 'b0;
  90.                 end
  91.  
  92.             :
  93.                 begin
  94.                     TLV1544_SCLK <= 'b1;
  95.                     rADC_DATA[] <= TLV1544_SDO;
  96.                 end
  97.  
  98.             :
  99.                 begin
  100.                     TLV1544_SDI <= ADC_CHSEL[];
  101.                     TLV1544_SCLK <= 'b0;
  102.                 end
  103.  
  104.             :
  105.                 begin
  106.                     TLV1544_SCLK <= 'b1;
  107.                     rADC_DATA[] <= TLV1544_SDO;
  108.                 end
  109.  
  110.             :
  111.                 begin
  112.                     TLV1544_SDI <= ADC_CHSEL[];
  113.                     TLV1544_SCLK <= 'b0;
  114.                 end
  115.  
  116.             :
  117.                 begin
  118.                     TLV1544_SCLK <= 'b1;
  119.                     rADC_DATA[] <= TLV1544_SDO;
  120.                 end
  121.  
  122.             :TLV1544_SCLK <= 'b0;
  123.  
  124.             :
  125.                 begin
  126.                     TLV1544_SCLK <= 'b1;
  127.                     rADC_DATA[] <= TLV1544_SDO;
  128.                 end
  129.             :TLV1544_SCLK <= 'b0;
  130.  
  131.             :
  132.                 begin
  133.                     TLV1544_SCLK <= 'b1;
  134.                     rADC_DATA[] <= TLV1544_SDO;
  135.                 end
  136.  
  137.             :TLV1544_SCLK <= 'b0;
  138.  
  139.             :
  140.                 begin
  141.                     TLV1544_SCLK <= 'b1;
  142.                     rADC_DATA[] <= TLV1544_SDO;
  143.                 end
  144.  
  145.            :TLV1544_SCLK <= 'b0;
  146.  
  147.            :
  148.                 begin
  149.                     TLV1544_SCLK <= 'b1;
  150.                     rADC_DATA[] <= TLV1544_SDO;
  151.                 end
  152.  
  153.             :TLV1544_SCLK <= 'b0;
  154.  
  155.             :
  156.                 begin
  157.                     TLV1544_SCLK <= 'b1;
  158.                     rADC_DATA[] <= TLV1544_SDO;
  159.                 end
  160.  
  161.            :TLV1544_SCLK <= 'b0;
  162.  
  163.           :
  164.                 begin
  165.                     TLV1544_SCLK <= 'b1;
  166.                     //rADC_DATA[0] <= TLV1544_SDO;
  167.                     if(TLV1544_EOC)
  168.                         DATA_Valid <= 'b1;
  169.                     else
  170.                         DATA_Valid <= 'b0;
  171.                     ADC_DATA <= {rADC_DATA[:],TLV1544_SDO};
  172.                 end
  173.  
  174.           :
  175.                 begin
  176.                     TLV1544_SCLK <= 'b0;
  177.                     TLV1544_NCS <= 'b1;
  178.                 end
  179.  
  180.             :AD_DONE <= 'b1;
  181.  
  182.             default:DATA_Valid <= 'b0;
  183.         endcase
  184.     end
  185.  
  186. endmodule

2.3 ADC转filter模块

ADC_to_filter.V

  1. module ADC_to_filter (
  2.  
  3. ADC_DATA,
  4. din
  5.  
  6. );
  7.  
  8. input        [:]ADC_DATA;
  9. output signed[:]din;
  10.  
  11. assign din = ADC_DATA<<;
  12.  
  13. endmodule

2.4 myiir模块

myiir.V

  1. module myiir(
  2. rst,
  3. clk,
  4. din,
  5. dout,
  6. din_valid,
  7. dout_valid,
  8. );
  9. input rst;
  10. input clk;
  11. input signed[:] din;
  12. input din_valid;
  13. output reg signed[:] dout;
  14. output reg dout_valid;
  15.  
  16. wire signed[:] dout1;
  17. wire signed[:] dout2;
  18. wire signed[:] dout3;
  19. wire signed[:] dout4;
  20. wire signed[:] dout5;
  21. wire signed[:] dout_reg;
  22.  
  23. wire din_valid1;
  24. wire dout_valid1;
  25. wire din_valid2;
  26. wire dout_valid2;
  27. wire din_valid3;
  28. wire dout_valid3;
  29. wire din_valid4;
  30. wire dout_valid4;
  31. wire din_valid5;
  32. wire dout_valid5;
  33. wire din_valid6;
  34. wire dout_valid6;
  35.  
  36. assign din_valid1=din_valid;
  37. assign din_valid2=dout_valid1;
  38. assign din_valid3=dout_valid2;
  39. assign din_valid4=dout_valid3;
  40. assign din_valid5=dout_valid4;
  41. assign din_valid6=dout_valid5;
  42.  
  43. //assign dout_prevalid=dout_valid1;
  44.  
  45. myiir_first_step U1(
  46. .rst(rst),
  47. .clk(clk),
  48. .din(din),
  49. .dout(dout1),
  50. .din_valid(din_valid1),
  51. .dout_valid(dout_valid1)
  52. );
  53.  
  54. myiir_second_step U2(
  55. .rst(rst),
  56. .clk(clk),
  57. .din(dout1),
  58. .dout(dout2),
  59. .din_valid(din_valid2),
  60. .dout_valid(dout_valid2)
  61. );
  62.  
  63. myiir_third_step U3(
  64. .rst(rst),
  65. .clk(clk),
  66. .din(dout2),
  67. .dout(dout3),
  68. .din_valid(din_valid3),
  69. .dout_valid(dout_valid3)
  70. );
  71.  
  72. myiir_fourth_step U4(
  73. .rst(rst),
  74. .clk(clk),
  75. .din(dout3),
  76. .dout(dout4),
  77. .din_valid(din_valid4),
  78. .dout_valid(dout_valid4)
  79. );
  80.  
  81. myiir_fifth_step U5(
  82. .rst(rst),
  83. .clk(clk),
  84. .din(dout4),
  85. .dout(dout5),
  86. .din_valid(din_valid5),
  87. .dout_valid(dout_valid5)
  88. );
  89.  
  90. myiir_sixth_step U6(
  91. .rst(rst),
  92. .clk(clk),
  93. .din(dout5),
  94. .dout(dout_reg),
  95. .din_valid(din_valid6),
  96. .dout_valid(dout_valid6)
  97. );
  98.  
  99. always @(negedge rst,posedge clk) begin
  100.         if(!rst) begin
  101.                 dout<='d0;
  102.                 dout_valid='b0;
  103.         end
  104.         else if(dout_valid6) begin
  105.                 dout_valid='b1;
  106.                 dout<=dout_reg;
  107.         end
  108.         else begin
  109.                 dout<=dout;
  110.                 dout_valid='b0;
  111.         end
  112. end
  113.  
  114. endmodule

2.5 filter转DAC模块

filter_to_DAC.V

  1. module filter_to_DAC
  2. (
  3.   dout,
  4.   CtrlWord
  5.  
  6. );
  7.  
  8. input signed[:] dout;
  9. output [:]CtrlWord;
  10.  
  11. assign CtrlWord[:]=dout[:];
  12. assign CtrlWord[:]='b0;
  13.  
  14. endmodule

2.6 TLC5620驱动

TLC5620_CTRL.V

  1. module TLC5620_CTRL(
  2.     Clk,
  3.     Rst_n,
  4.     UpdateReq,
  5.     CtrlWord,
  6.  
  7.     UpdateDone,
  8.     TLC5620_CLK,
  9.     TLC5620_DATA,
  10.     TLC5620_LOAD,
  11.     TLC5620_LDAC
  12. );
  13.  
  14.     input Clk;
  15.     input Rst_n;
  16.     input UpdateReq;
  17.     input [:]CtrlWord;
  18.  
  19.     output reg UpdateDone;
  20.     output reg TLC5620_CLK;
  21.     output reg TLC5620_DATA;
  22.     output reg TLC5620_LOAD;
  23.     output reg TLC5620_LDAC;
  24.  
  25.     reg [:] Cnt;
  26.  
  27.     always@(posedge Clk or negedge Rst_n)
  28.     if(!Rst_n)
  29.         Cnt <= 'd0;
  30.     else if(UpdateReq ==  | (Cnt != 'd0))begin
  31.         if(Cnt == 'd820)
  32.             Cnt <= 'd0;
  33.         else
  34.             Cnt <= Cnt + 'd1;
  35.     end
  36.     else
  37.         Cnt <= 'd0;
  38.  
  39.     always@(posedge Clk or negedge Rst_n)
  40.     if(!Rst_n)begin
  41.         TLC5620_CLK <= 'b0;
  42.         TLC5620_DATA <= 'b0;
  43.         TLC5620_LOAD <= 'b0;
  44.         TLC5620_LDAC <= 'b0;
  45.         UpdateDone <= 'b0;
  46.     end
  47.     else begin
  48.         case(Cnt)
  49.             :
  50.                 begin
  51.                     TLC5620_CLK <= 'b0;
  52.                     TLC5620_DATA <= 'b0;
  53.                     TLC5620_LOAD <= 'b1;
  54.                     TLC5620_LDAC <= 'b0;
  55.                     UpdateDone <= 'b0;
  56.                 end
  57.             :
  58.                 begin
  59.                     TLC5620_CLK <= 'b1;
  60.                     TLC5620_DATA <= CtrlWord[];
  61.                 end
  62.             : TLC5620_CLK <= 'b0;
  63.  
  64.             :
  65.                 begin
  66.                     TLC5620_CLK <= 'b1;
  67.                     TLC5620_DATA <= CtrlWord[];
  68.                 end
  69.  
  70.             : TLC5620_CLK <= 'b0;
  71.             :
  72.                 begin
  73.                     TLC5620_CLK <= 'b1;
  74.                     TLC5620_DATA <= CtrlWord[];
  75.                 end
  76.             : TLC5620_CLK <= 'b0;
  77.             :
  78.                 begin
  79.                     TLC5620_CLK <= 'b1;
  80.                     TLC5620_DATA <= CtrlWord[];
  81.                 end
  82.             : TLC5620_CLK <= 'b0;
  83.             :
  84.                 begin
  85.                     TLC5620_CLK <= 'b1;
  86.                     TLC5620_DATA <= CtrlWord[];
  87.                 end
  88.             : TLC5620_CLK <= 'b0;
  89.             :
  90.                 begin
  91.                     TLC5620_CLK <= 'b1;
  92.                     TLC5620_DATA <= CtrlWord[];
  93.                 end
  94.             : TLC5620_CLK <= 'b0;
  95.             :
  96.                 begin
  97.                     TLC5620_CLK <= 'b1;
  98.                     TLC5620_DATA <= CtrlWord[];
  99.                 end
  100.             : TLC5620_CLK <= 'b0;
  101.             :
  102.                 begin
  103.                     TLC5620_CLK <= 'b1;
  104.                     TLC5620_DATA <= CtrlWord[];
  105.                 end
  106.             : TLC5620_CLK <= 'b0;
  107.             :
  108.                 begin
  109.                     TLC5620_CLK <= 'b1;
  110.                     TLC5620_DATA <= CtrlWord[];
  111.                 end
  112.             : TLC5620_CLK <= 'b0;
  113.             :
  114.                 begin
  115.                     TLC5620_CLK <= 'b1;
  116.                     TLC5620_DATA <= CtrlWord[];
  117.                 end
  118.             : TLC5620_CLK <= 'b0;
  119.             :
  120.                 begin
  121.                     TLC5620_CLK <= 'b1;
  122.                     TLC5620_DATA <= CtrlWord[];
  123.                 end
  124.             : TLC5620_CLK <= 'b0;
  125.             :TLC5620_LOAD <= 'b0;
  126.             :TLC5620_LOAD <= 'b1;
  127.             :UpdateDone <= 'b1;
  128.             default:;
  129.         endcase
  130.     end
  131.  
  132. endmodule

2.7 myiir_first_step模块

myiir_first_step.V

  1. module myiir_first_step(
  2. rst,
  3. clk,
  4. din,
  5. dout,
  6. din_valid,
  7. dout_valid
  8. );
  9.  
  10. parameter b0=;
  11. parameter b1=-;
  12. parameter b2=;
  13. parameter a1=-;
  14. parameter a2=;
  15.  
  16. input rst;
  17. input clk;
  18. input signed[:] din;
  19. input din_valid;
  20.  
  21. output signed[:] dout;
  22. output dout_valid;
  23.  
  24. reg[:] cState,nState;
  25. reg signed[:] x_reg0;
  26. reg signed[:] x_reg1;
  27.  
  28. reg signed[:] x_mul1;
  29. reg signed[:] x_mul2;
  30. reg signed[:] x_mul3;
  31.  
  32. wire signed[:] x_int_mul1;
  33. wire signed[:] x_int_mul2;
  34. wire signed[:] x_int_mul3;
  35.  
  36. reg signed[:] x_sum;
  37. wire signed[:] x_temp;
  38.  
  39. reg signed[:] y_reg0;
  40. reg signed[:] y_reg1;
  41.  
  42. reg signed[:] y_mul1;
  43. reg signed[:] y_mul2;
  44.  
  45. wire signed[:] y_int_mul1;
  46. wire signed[:] y_int_mul2;
  47.  
  48. reg signed[:] y_sum;
  49. wire signed[:] y_temp;
  50.  
  51. reg signed[:] dout_sum;
  52. wire signed[:] dout_temp;
  53.  
  54. always @(negedge rst,posedge clk) begin
  55.         if(!rst) begin
  56.                 cState<=;
  57.         end
  58.         else begin
  59.                 cState<=nState;
  60.         end
  61. end
  62.  
  63. always @(*) begin
  64.         case(cState)
  65.                 :if(din_valid) begin
  66.                         nState<=;
  67.                   end
  68.                   else begin
  69.                         nState<=;
  70.                   end
  71.                 :nState<=;
  72.                 :nState<=;
  73.                 :nState<=;
  74.                 :nState<=;
  75.                 :nState<=;
  76.                 :nState<=;
  77.                 default:nState<=nState;
  78.         endcase
  79. end
  80.  
  81. always @(*) begin
  82.         if(rst) begin
  83.                 case(cState)
  84.                         :x_mul1=b0*din;
  85.                         :begin
  86.                                 x_mul2=b1*x_reg0;
  87.                                 y_mul1=a1*y_reg0;
  88.                         end
  89.                         :begin
  90.                                 x_mul3=b2*x_reg1;
  91.                                 y_mul2=a2*y_reg1;
  92.                         end
  93.                         :begin
  94.                                 x_sum=x_int_mul1+x_int_mul2+x_int_mul3;
  95.                                 y_sum=y_int_mul1+y_int_mul2;
  96.                         end
  97.                         :dout_sum=x_temp-y_temp;
  98.                         default:;
  99.                 endcase
  100.         end
  101. end
  102.  
  103. always @(cState) begin
  104.         if(rst) begin
  105.                 if(cState==) begin
  106.                         x_reg0<=din;
  107.                         x_reg1<=x_reg0;
  108.                 end
  109.                 else begin
  110.                         x_reg0<=x_reg0;
  111.                         x_reg1<=x_reg1;
  112.                 end
  113.         end
  114.         else begin
  115.                 x_reg0<='d0;
  116.                 x_reg1<='d0;
  117.         end
  118. end
  119.  
  120. always @(cState) begin
  121.         if(rst) begin
  122.                 if(cState==) begin
  123.                         y_reg0<=dout;
  124.                         y_reg1<=y_reg0;
  125.                 end
  126.                 else begin
  127.                         y_reg0<=y_reg0;
  128.                         y_reg1<=y_reg1;
  129.                 end
  130.         end
  131.         else begin
  132.                 y_reg0<='d0;
  133.                 y_reg1<='d0;
  134.         end
  135. end
  136.  
  137. assign x_int_mul1=(x_mul1[]^x_mul1[])?x_mul1[:]:x_mul1[:];
  138. assign x_int_mul2=(x_mul2[]^x_mul2[])?x_mul2[:]:x_mul2[:];
  139. assign x_int_mul3=(x_mul3[]^x_mul3[])?x_mul3[:]:x_mul3[:];
  140. assign x_temp=(x_sum[:]=='b000||x_sum[17:15]==3'b111)?x_sum[:]:(x_sum[])?'h8000:16'h7fff;
  141.  
  142. assign y_int_mul1=(y_mul1[]^y_mul1[])?y_mul1[:]:y_mul1[:];
  143. assign y_int_mul2=(y_mul2[]^y_mul2[])?y_mul2[:]:y_mul2[:];
  144. assign y_temp=(y_sum[:]=='b00||y_sum[16:15]==2'b11)?y_sum[:]:(y_sum[])?'h8000:16'h7fff;
  145.  
  146. assign dout_temp=(dout_sum[:]=='b00||dout_sum[16:15]==2'b11)?dout_sum[:]:(dout_sum[])?'h8000:16'h7fff;
  147. assign dout=(!rst)?'d0:dout_temp;
  148.  
  149. assign dout_valid=(cState== && nState==)?'b1:1'b0;
  150.  
  151. endmodule

2.8 myiir_second_step模块

myiir_second_step.V

  1. module myiir_second_step(
  2. rst,
  3. clk,
  4. din,
  5. dout,
  6. din_valid,
  7. dout_valid
  8. );
  9.  
  10. parameter b0=;
  11. parameter b1=-;
  12. parameter b2=;
  13. parameter a1=-;
  14. parameter a2=;
  15.  
  16. input rst;
  17. input clk;
  18. input signed[:] din;
  19. input din_valid;
  20.  
  21. output signed[:] dout;
  22. output dout_valid;
  23.  
  24. reg[:] cState,nState;
  25. reg signed[:] x_reg0;
  26. reg signed[:] x_reg1;
  27.  
  28. reg signed[:] x_mul1;
  29. reg signed[:] x_mul2;
  30. reg signed[:] x_mul3;
  31.  
  32. wire signed[:] x_int_mul1;
  33. wire signed[:] x_int_mul2;
  34. wire signed[:] x_int_mul3;
  35.  
  36. reg signed[:] x_sum;
  37. wire signed[:] x_temp;
  38.  
  39. reg signed[:] y_reg0;
  40. reg signed[:] y_reg1;
  41.  
  42. reg signed[:] y_mul1;
  43. reg signed[:] y_mul2;
  44.  
  45. wire signed[:] y_int_mul1;
  46. wire signed[:] y_int_mul2;
  47.  
  48. reg signed[:] y_sum;
  49. wire signed[:] y_temp;
  50.  
  51. reg signed[:] dout_sum;
  52. wire signed[:] dout_temp;
  53.  
  54. always @(negedge rst,posedge clk) begin
  55.         if(!rst) begin
  56.                 cState<=;
  57.         end
  58.         else begin
  59.                 cState<=nState;
  60.         end
  61. end
  62.  
  63. always @(*) begin
  64.         case(cState)
  65.                 :if(din_valid) begin
  66.                         nState<=;
  67.                   end
  68.                   else begin
  69.                         nState<=;
  70.                   end
  71.                 :nState<=;
  72.                 :nState<=;
  73.                 :nState<=;
  74.                 :nState<=;
  75.                 :nState<=;
  76.                 :nState<=;
  77.                 default:nState<=nState;
  78.         endcase
  79. end
  80.  
  81. always @(*) begin
  82.         if(rst) begin
  83.                 case(cState)
  84.                         :x_mul1=b0*din;
  85.                         :begin
  86.                                 x_mul2=b1*x_reg0;
  87.                                 y_mul1=a1*y_reg0;
  88.                         end
  89.                         :begin
  90.                                 x_mul3=b2*x_reg1;
  91.                                 y_mul2=a2*y_reg1;
  92.                         end
  93.                         :begin
  94.                                 x_sum=x_int_mul1+x_int_mul2+x_int_mul3;
  95.                                 y_sum=y_int_mul1+y_int_mul2;
  96.                         end
  97.                         : dout_sum=x_temp-y_temp;
  98.                         default:;
  99.                 endcase
  100.         end
  101. end
  102.  
  103. assign x_int_mul1=(x_mul1[]^x_mul1[])?x_mul1[:]:x_mul1[:];
  104. assign x_int_mul2=(x_mul2[]^x_mul2[])?x_mul2[:]:x_mul2[:];
  105. assign x_int_mul3=(x_mul3[]^x_mul3[])?x_mul3[:]:x_mul3[:];
  106. assign x_temp=(x_sum[:]=='b000||x_sum[17:15]==3'b111)?x_sum[:]:(x_sum[])?'h8000:16'h7fff;
  107.  
  108. assign y_int_mul1=(y_mul1[]^y_mul1[])?y_mul1[:]:y_mul1[:];
  109. assign y_int_mul2=(y_mul2[]^y_mul2[])?y_mul2[:]:y_mul2[:];
  110. assign y_temp=(y_sum[:]=='b00||y_sum[16:15]==2'b11)?y_sum[:]:(y_sum[])?'h8000:16'h7fff;
  111.  
  112. assign dout_temp=(dout_sum[:]=='b00||dout_sum[16:15]==2'b11)?dout_sum[:]:(dout_sum[])?'h8000:16'h7fff;
  113. assign dout=(!rst)?'d0:dout_temp;
  114.  
  115. always @(cState) begin
  116.         if(rst) begin
  117.                 if(cState==) begin
  118.                         x_reg0<=din;
  119.                         x_reg1<=x_reg0;
  120.                 end
  121.                 else begin
  122.                         x_reg0<=x_reg0;
  123.                         x_reg1<=x_reg1;
  124.                 end
  125.         end
  126.         else begin
  127.                 x_reg0<='d0;
  128.                 x_reg1<='d0;
  129.         end
  130. end
  131.  
  132. always @(cState) begin
  133.         if(rst) begin
  134.                 if(cState==) begin
  135.                         y_reg0<=dout;
  136.                         y_reg1<=y_reg0;
  137.                 end
  138.                 else begin
  139.                         y_reg0<=y_reg0;
  140.                         y_reg1<=y_reg1;
  141.                 end
  142.         end
  143.         else begin
  144.                 y_reg0<='d0;
  145.                 y_reg1<='d0;
  146.         end
  147. end
  148.  
  149. assign dout_valid=(cState== && nState==)?'b1:1'b0;
  150.  
  151. endmodule

2.9 myiir_third_step模块

myiir_third_step.V

  1. module myiir_third_step(
  2. rst,
  3. clk,
  4. din,
  5. dout,
  6. din_valid,
  7. dout_valid
  8. );
  9.  
  10. parameter b0=;
  11. parameter b1=-;
  12. parameter b2=;
  13. parameter a1=-;
  14. parameter a2=;
  15.  
  16. input rst;
  17. input clk;
  18. input signed[:] din;
  19. input din_valid;
  20.  
  21. output signed[:] dout;
  22. output dout_valid;
  23.  
  24. reg[:] cState,nState;
  25. reg signed[:] x_reg0;
  26. reg signed[:] x_reg1;
  27.  
  28. reg signed[:] x_mul1;
  29. reg signed[:] x_mul2;
  30. reg signed[:] x_mul3;
  31.  
  32. wire signed[:] x_int_mul1;
  33. wire signed[:] x_int_mul2;
  34. wire signed[:] x_int_mul3;
  35.  
  36. reg signed[:] x_sum;
  37. wire signed[:] x_temp;
  38.  
  39. reg signed[:] y_reg0;
  40. reg signed[:] y_reg1;
  41.  
  42. reg signed[:] y_mul1;
  43. reg signed[:] y_mul2;
  44.  
  45. wire signed[:] y_int_mul1;
  46. wire signed[:] y_int_mul2;
  47.  
  48. reg signed[:] y_sum;
  49. wire signed[:] y_temp;
  50.  
  51. reg signed[:] dout_sum;
  52. wire signed[:] dout_temp;
  53.  
  54. always @(negedge rst,posedge clk) begin
  55.         if(!rst) begin
  56.                 cState<=;
  57.         end
  58.         else begin
  59.                 cState<=nState;
  60.         end
  61. end
  62.  
  63. always @(*) begin
  64.         case(cState)
  65.                 :if(din_valid) begin
  66.                         nState<=;
  67.                   end
  68.                   else begin
  69.                         nState<=;
  70.                   end
  71.                 :nState<=;
  72.                 :nState<=;
  73.                 :nState<=;
  74.                 :nState<=;
  75.                 :nState<=;
  76.                 :nState<=;
  77.                 default:nState<=nState;
  78.         endcase
  79. end
  80.  
  81. always @(*) begin
  82.         if(rst) begin
  83.                 case(cState)
  84.                         :x_mul1=b0*din;
  85.                         :begin
  86.                                 x_mul2=b1*x_reg0;
  87.                                 y_mul1=a1*y_reg0;
  88.                         end
  89.                         :begin
  90.                                 x_mul3=b2*x_reg1;
  91.                                 y_mul2=a2*y_reg1;
  92.                         end
  93.                         :begin
  94.                                 x_sum=x_int_mul1+x_int_mul2+x_int_mul3;
  95.                                 y_sum=y_int_mul1+y_int_mul2;
  96.                         end
  97.                         : dout_sum=x_temp-y_temp;
  98.                         default:;
  99.                 endcase
  100.         end
  101. end
  102.  
  103. assign x_int_mul1=(x_mul1[]^x_mul1[])?x_mul1[:]:x_mul1[:];
  104. assign x_int_mul2=(x_mul2[]^x_mul2[])?x_mul2[:]:x_mul2[:];
  105. assign x_int_mul3=(x_mul3[]^x_mul3[])?x_mul3[:]:x_mul3[:];
  106. assign x_temp=(x_sum[:]=='b000||x_sum[17:15]==3'b111)?x_sum[:]:(x_sum[])?'h8000:16'h7fff;
  107.  
  108. assign y_int_mul1=(y_mul1[]^y_mul1[])?y_mul1[:]:y_mul1[:];
  109. assign y_int_mul2=(y_mul2[]^y_mul2[])?y_mul2[:]:y_mul2[:];
  110. assign y_temp=(y_sum[:]=='b00||y_sum[16:15]==2'b11)?y_sum[:]:(y_sum[])?'h8000:16'h7fff;
  111.  
  112. assign dout_temp=(dout_sum[:]=='b00||dout_sum[16:15]==2'b11)?dout_sum[:]:(dout_sum[])?'h8000:16'h7fff;
  113. assign dout=(!rst)?'d0:dout_temp;
  114.  
  115. always @(cState) begin
  116.         if(rst) begin
  117.                 if(cState==) begin
  118.                                 x_reg0<=din;
  119.                                 x_reg1<=x_reg0;
  120.                 end
  121.                 else begin
  122.                                 x_reg0<=x_reg0;
  123.                                 x_reg1<=x_reg1;
  124.                 end
  125.         end
  126.         else begin
  127.                 x_reg0<='d0;
  128.                 x_reg1<='d0;
  129.         end
  130. end
  131.  
  132. always @(cState) begin
  133.         if(rst) begin
  134.                 if(cState==) begin
  135.                         y_reg0<=dout;
  136.                         y_reg1<=y_reg0;
  137.                 end
  138.                 else begin
  139.                         y_reg0<=y_reg0;
  140.                         y_reg1<=y_reg1;
  141.                 end
  142.         end
  143.         else begin
  144.                 y_reg0<='d0;
  145.                 y_reg1<='d0;
  146.         end
  147. end
  148.  
  149. assign dout_valid=(cState== && nState==)?'b1:1'b0;
  150.  
  151. endmodule

2.10 myiir_fourth_step模块

myiir_fourth_step.V

  1. module myiir_fourth_step(
  2. rst,
  3. clk,
  4. din,
  5. dout,
  6. din_valid,
  7. dout_valid
  8. );
  9.  
  10. parameter b0=;
  11. parameter b1=-;
  12. parameter b2=;
  13. parameter a1=-;
  14. parameter a2=;
  15.  
  16. input rst;
  17. input clk;
  18. input signed[:] din;
  19. input din_valid;
  20.  
  21. output signed[:] dout;
  22. output dout_valid;
  23.  
  24. reg[:] cState,nState;
  25. reg signed[:] x_reg0;
  26. reg signed[:] x_reg1;
  27.  
  28. reg signed[:] x_mul1;
  29. reg signed[:] x_mul2;
  30. reg signed[:] x_mul3;
  31.  
  32. wire signed[:] x_int_mul1;
  33. wire signed[:] x_int_mul2;
  34. wire signed[:] x_int_mul3;
  35.  
  36. reg signed[:] x_sum;
  37. wire signed[:] x_temp;
  38.  
  39. reg signed[:] y_reg0;
  40. reg signed[:] y_reg1;
  41.  
  42. reg signed[:] y_mul1;
  43. reg signed[:] y_mul2;
  44.  
  45. wire signed[:] y_int_mul1;
  46. wire signed[:] y_int_mul2;
  47.  
  48. reg signed[:] y_sum;
  49. wire signed[:] y_temp;
  50.  
  51. reg signed[:] dout_sum;
  52. wire signed[:] dout_temp;
  53.  
  54. always @(negedge rst,posedge clk) begin
  55.         if(!rst) begin
  56.                 cState<=;
  57.         end
  58.         else begin
  59.                 cState<=nState;
  60.         end
  61. end
  62.  
  63. always @(*) begin
  64.         case(cState)
  65.                 :if(din_valid) begin
  66.                         nState<=;
  67.                   end
  68.                   else begin
  69.                         nState<=;
  70.                   end
  71.                 :nState<=;
  72.                 :nState<=;
  73.                 :nState<=;
  74.                 :nState<=;
  75.                 :nState<=;
  76.                 :nState<=;
  77.                 default:nState<=nState;
  78.         endcase
  79. end
  80.  
  81. always @(*) begin
  82.         if(rst) begin
  83.                 case(cState)
  84.                         :x_mul1=b0*din;
  85.                         :begin
  86.                                 x_mul2=b1*x_reg0;
  87.                                 y_mul1=a1*y_reg0;
  88.                         end
  89.                         :begin
  90.                                 x_mul3=b2*x_reg1;
  91.                                 y_mul2=a2*y_reg1;
  92.                         end
  93.                         :begin
  94.                                 x_sum=x_int_mul1+x_int_mul2+x_int_mul3;
  95.                                 y_sum=y_int_mul1+y_int_mul2;
  96.                         end
  97.                         : dout_sum=x_temp-y_temp;
  98.                         default:;
  99.                 endcase
  100.         end
  101. end
  102.  
  103. assign x_int_mul1=(x_mul1[]^x_mul1[])?x_mul1[:]:x_mul1[:];
  104. assign x_int_mul2=(x_mul2[]^x_mul2[])?x_mul2[:]:x_mul2[:];
  105. assign x_int_mul3=(x_mul3[]^x_mul3[])?x_mul3[:]:x_mul3[:];
  106. assign x_temp=(x_sum[:]=='b000||x_sum[17:15]==3'b111)?x_sum[:]:(x_sum[])?'h8000:16'h7fff;
  107.  
  108. assign y_int_mul1=(y_mul1[]^y_mul1[])?y_mul1[:]:y_mul1[:];
  109. assign y_int_mul2=(y_mul2[]^y_mul2[])?y_mul2[:]:y_mul2[:];
  110. assign y_temp=(y_sum[:]=='b00||y_sum[16:15]==2'b11)?y_sum[:]:(y_sum[])?'h8000:16'h7fff;
  111.  
  112. assign dout_temp=(dout_sum[:]=='b00||dout_sum[16:15]==2'b11)?dout_sum[:]:(dout_sum[])?'h8000:16'h7fff;
  113. assign dout=(!rst)?'d0:dout_temp;
  114.  
  115. always @(cState) begin
  116.         if(rst) begin
  117.                 case(cState)
  118.                         : begin
  119.                                 x_reg0<=din;
  120.                                 x_reg1<=x_reg0;
  121.                         end
  122.                         default:begin
  123.                                 x_reg0<=x_reg0;
  124.                                 x_reg1<=x_reg1;
  125.                         end
  126.                 endcase
  127.         end
  128.         else begin
  129.                 x_reg0<='d0;
  130.                 x_reg1<='d0;
  131.         end
  132. end
  133.  
  134. always @(cState) begin
  135.         if(rst) begin
  136.                 if(cState==) begin
  137.                         y_reg0<=dout;
  138.                         y_reg1<=y_reg0;
  139.                 end
  140.                 else begin
  141.                         y_reg0<=y_reg0;
  142.                         y_reg1<=y_reg1;
  143.                 end
  144.         end
  145.         else begin
  146.                 y_reg0<='d0;
  147.                 y_reg1<='d0;
  148.         end
  149. end
  150.  
  151. assign dout_valid=(cState== && nState==)?'b1:1'b0;
  152.  
  153. endmodule

2.11 myiir_fifth_step模块

myiir_fifth_step.V

  1. module myiir_fifth_step(
  2. rst,
  3. clk,
  4. din,
  5. dout,
  6. din_valid,
  7. dout_valid
  8. );
  9.  
  10. parameter b0=;
  11. parameter b1=-;
  12. parameter b2=;
  13. parameter a1=-;
  14. parameter a2=;
  15.  
  16. input rst;
  17. input clk;
  18. input signed[:] din;
  19. input din_valid;
  20.  
  21. output signed[:] dout;
  22. output dout_valid;
  23.  
  24. reg[:] cState,nState;
  25. reg signed[:] x_reg0;
  26. reg signed[:] x_reg1;
  27.  
  28. reg signed[:] x_mul1;
  29. reg signed[:] x_mul2;
  30. reg signed[:] x_mul3;
  31.  
  32. wire signed[:] x_int_mul1;
  33. wire signed[:] x_int_mul2;
  34. wire signed[:] x_int_mul3;
  35.  
  36. reg signed[:] x_sum;
  37. wire signed[:] x_temp;
  38.  
  39. reg signed[:] y_reg0;
  40. reg signed[:] y_reg1;
  41.  
  42. reg signed[:] y_mul1;
  43. reg signed[:] y_mul2;
  44.  
  45. wire signed[:] y_int_mul1;
  46. wire signed[:] y_int_mul2;
  47.  
  48. reg signed[:] y_sum;
  49. wire signed[:] y_temp;
  50.  
  51. reg signed[:] dout_sum;
  52. wire signed[:] dout_temp;
  53.  
  54. always @(negedge rst,posedge clk) begin
  55.         if(!rst) begin
  56.                 cState<=;
  57.         end
  58.         else begin
  59.                 cState<=nState;
  60.         end
  61. end
  62.  
  63. always @(*) begin
  64.         case(cState)
  65.                 :if(din_valid) begin
  66.                         nState<=;
  67.                   end
  68.                   else begin
  69.                         nState<=;
  70.                   end
  71.                 :nState<=;
  72.                 :nState<=;
  73.                 :nState<=;
  74.                 :nState<=;
  75.                 :nState<=;
  76.                 :nState<=;
  77.                 default:nState<=nState;
  78.         endcase
  79. end
  80.  
  81. always @(*) begin
  82.         if(rst) begin
  83.                 case(cState)
  84.                         :x_mul1=b0*din;
  85.                         :begin
  86.                                 x_mul2=b1*x_reg0;
  87.                                 y_mul1=a1*y_reg0;
  88.                         end
  89.                         :begin
  90.                                 x_mul3=b2*x_reg1;
  91.                                 y_mul2=a2*y_reg1;
  92.                         end
  93.                         :begin
  94.                                 x_sum=x_int_mul1+x_int_mul2+x_int_mul3;
  95.                                 y_sum=y_int_mul1+y_int_mul2;
  96.                         end
  97.                         : dout_sum=x_temp-y_temp;
  98.                         default:;
  99.                 endcase
  100.         end
  101. end
  102.  
  103. assign x_int_mul1=(x_mul1[]^x_mul1[])?x_mul1[:]:x_mul1[:];
  104. assign x_int_mul2=(x_mul2[]^x_mul2[])?x_mul2[:]:x_mul2[:];
  105. assign x_int_mul3=(x_mul3[]^x_mul3[])?x_mul3[:]:x_mul3[:];
  106. assign x_temp=(x_sum[:]=='b000||x_sum[17:15]==3'b111)?x_sum[:]:(x_sum[])?'h8000:16'h7fff;
  107.  
  108. assign y_int_mul1=(y_mul1[]^y_mul1[])?y_mul1[:]:y_mul1[:];
  109. assign y_int_mul2=(y_mul2[]^y_mul2[])?y_mul2[:]:y_mul2[:];
  110. assign y_temp=(y_sum[:]=='b00||y_sum[16:15]==2'b11)?y_sum[:]:(y_sum[])?'h8000:16'h7fff;
  111.  
  112. assign dout_temp=(dout_sum[:]=='b00||dout_sum[16:15]==2'b11)?dout_sum[:]:(dout_sum[])?'h8000:16'h7fff;
  113. assign dout=(!rst)?'d0:dout_temp;
  114.  
  115. always @(cState) begin
  116.         if(rst) begin
  117.                 case(cState)
  118.                         : begin
  119.                                 x_reg0<=din;
  120.                                 x_reg1<=x_reg0;
  121.                         end
  122.                         default:begin
  123.                                 x_reg0<=x_reg0;
  124.                                 x_reg1<=x_reg1;
  125.                         end
  126.                 endcase
  127.         end
  128.         else begin
  129.                 x_reg0<='d0;
  130.                 x_reg1<='d0;
  131.         end
  132. end
  133.  
  134. always @(cState) begin
  135.         if(rst) begin
  136.                 if(cState==) begin
  137.                         y_reg0<=dout;
  138.                         y_reg1<=y_reg0;
  139.                 end
  140.                 else begin
  141.                         y_reg0<=y_reg0;
  142.                         y_reg1<=y_reg1;
  143.                 end
  144.         end
  145.         else begin
  146.                 y_reg0<='d0;
  147.                 y_reg1<='d0;
  148.         end
  149. end
  150.  
  151. assign dout_valid=(cState== && nState==)?'b1:1'b0;
  152.  
  153. endmodule

2.12 myiir_sixth_step模块

myiir_sixth_step.V

  1. module myiir_sixth_step(
  2. rst,
  3. clk,
  4. din,
  5. dout,
  6. din_valid,
  7. dout_valid
  8. );
  9.  
  10. parameter b0=;
  11. parameter b1=;
  12. parameter a1=-;
  13.  
  14. input rst;
  15. input clk;
  16. input signed[:] din;
  17. input din_valid;
  18.  
  19. output signed[:] dout;
  20. output dout_valid;
  21.  
  22. reg[:] cState,nState;
  23.  
  24. reg signed[:] x_reg0;
  25.  
  26. reg signed[:] x_mul1;
  27. reg signed[:] x_mul2;
  28.  
  29. wire signed[:] x_int_mul1;
  30. wire signed[:] x_int_mul2;
  31.  
  32. reg signed[:] x_sum;
  33. wire signed[:] x_temp;
  34.  
  35. reg signed[:] y_reg0;
  36.  
  37. reg signed[:] y_mul1;
  38. wire signed[:] y_int_mul1;
  39.  
  40. reg signed[:] dout_sum;
  41. wire signed[:] dout_temp;
  42.  
  43. always @(negedge rst,posedge clk) begin
  44.         if(!rst) begin
  45.                 cState<=;
  46.         end
  47.         else begin
  48.                 cState<=nState;
  49.         end
  50. end
  51.  
  52. always @(*) begin
  53.         case(cState)
  54.                 :if(din_valid) begin
  55.                         nState<=;
  56.                   end
  57.                   else begin
  58.                         nState<=;
  59.                   end
  60.                 :nState<=;
  61.                 :nState<=;
  62.                 :nState<=;
  63.                 :nState<=;
  64.                 :nState<=;
  65.                 default:nState<=;
  66.         endcase
  67. end
  68.  
  69. always @(*) begin
  70.         if(rst) begin
  71.                 case(cState)
  72.                         :x_mul1=b0*din;
  73.                         :begin
  74.                                 x_mul2=b1*x_reg0;
  75.                                 y_mul1=a1*y_reg0;
  76.                         end
  77.                         :begin
  78.                                 x_sum=x_int_mul1+x_int_mul2;
  79.                         end
  80.                         :begin
  81.                                 dout_sum=x_temp-y_int_mul1;
  82.                         end
  83.                         default:;
  84.                 endcase
  85.         end
  86. end
  87.  
  88. assign x_int_mul1=(x_mul1[]^x_mul1[])?x_mul1[:]:x_mul1[:];
  89. assign x_int_mul2=(x_mul2[]^x_mul2[])?x_mul2[:]:x_mul2[:];
  90. assign x_temp=(x_sum[:]=='b00||x_sum[16:15]==2'b11)?x_sum[:]:(x_sum[])?'h8000:16'h7fff;
  91.  
  92. assign y_int_mul1=(y_mul1[]^y_mul1[])?y_mul1[:]:y_mul1[:];
  93.  
  94. assign dout_temp=(dout_sum[:]=='b00||dout_sum[16:15]==2'b11)?dout_sum[:]:(dout_sum[])?'h8000:16'h7fff;
  95. assign dout=(!rst)?'d0:dout_temp;
  96.  
  97. always @(cState) begin
  98.         if(rst) begin
  99.                 if(cState==) begin
  100.                         x_reg0<=din;
  101.                 end
  102.                 else begin
  103.                         x_reg0<=x_reg0;
  104.                 end
  105.         end
  106.         else begin
  107.                 x_reg0<='d0;
  108.         end
  109. end
  110.  
  111. always @(cState) begin
  112.         if(rst) begin
  113.                 if(cState==) begin
  114.                         y_reg0<=dout;
  115.                 end
  116.                 else begin
  117.                         y_reg0<=y_reg0;
  118.                 end
  119.         end
  120.         else begin
  121.                 y_reg0<='d0;
  122.         end
  123. end
  124.  
  125. assign dout_valid=(cState== && nState==)?'b1:1'b0;
  126.  
  127. endmodule

代码到这里终于结束了！辛苦观看。。

3.仿真与引脚分配

 3.1 仿真

实验使用modelsim进行仿真，从matlab获得量化后的输入波形文件，经过仿真后得到滤波后的波形。

3.2 引脚分配

4.心得

本次实验好艰辛啊！从最开始的晕头晕脑，到最后有效果，时间挺长的，但确实学到了许多！通过这次实验，不仅更加熟练地学习到了FPGA设计的流程，更加深了数字信号处理滤波器的设计和实现！重要是坚持!!!

5.视频地址

前篇

http://v.youku.com/v_show/id_XMjcyMjkwNDY3Mg==.html

后篇

http://v.youku.com/v_show/id_XMjcyMjkyOTYzMg==.html

end

基于FPGA的IIR滤波器的更多相关文章

  1. 基于FPGA的图像去噪

    目录 结构图 其中FPGA 控制模块为核心,通过它实现视频图像数据的获取.缓存.处理和控制各模块间通讯［1］.由CCD 相机对目标成像,高速图像数据由camera link 实时传输［2］,经信号转换 ...

  2. 基于FPGA的16阶级联型iir带通滤波器实现

    警告 此文章将耗费你成吨的流量,请wifi下阅读,造成的流量浪费本人不承担任何责任.初版源代码获取(请勿用作他用,仅供学习):https://gitee.com/kingstacker/iir.git ...

  3. 基于FPGA dspbuilder的DNLMS滤波器实现

          自适应滤波器一直是信号处理领域的研究热点之一,经过多年的发展,已经被广泛应用于数字通信.回声消除.图像处理等领域.自适应滤波算法的研究始于20世纪50年代末,Widrow和Hoff等人最早 ...

  4. 基于FPGA的音频信号的FIR滤波（Matlab+Modelsim验证）

    1 设计内容 本设计是基于FPGA的音频信号FIR低通滤波,根据要求,采用Matlab对WAV音频文件进行读取和添加噪声信号.FFT分析.FIR滤波处理,并分析滤波的效果.通过Matlab的分析验证滤 ...

  5. FIR滤波器和IIR滤波器的区别

    数字滤波器广泛应用于硬件电路设计,在离散系统中尤为常见,一般可以分为FIR滤波器和IIR滤波器,那么他们有什么区别和联系呢. FIR滤波器 定义: FIR滤波器是有限长单位冲激响应滤波器,又称为非递归 ...

  6. 基于FPGA的DDS设计（一）

    最近在学习基于FPGA的DDS设计,借此机会把学习过程记录下来,当作自己的学习笔记也希望能够帮助到学习DDS的小伙伴. DDS(Direct Digital Synthesizer)直接数字合成器,这 ...

  7. IIR滤波器设计（调用MATLAB IIR函数来实现）

    转载请注明文章来源 – http://blog.csdn.net/v_hyx ,请勿用于任何商业用途         对于滤波器设计,以前虽然学过相关的理论(现代数字信号处理和DSP设计),但一直不求 ...

  8. IIR滤波器和FIR滤波器的区别与联系zz

      -------------------------------------------------------------------------------------------------- ...

  9. 基于FPGA的飞机的小游戏

    基于FPGA的飞机的小游戏 实验原理 该实验主要分为4个模块,采用至上而下的设计方法进行设计.由50M的晶振电路提供时钟源,VGA显示控制模块.图形显示控制模块.移动模块的时钟为25M,由时钟分频电路 ...

随机推荐

  1. mysql sql语句

    1.数据库和表的操作 创建 create修改 alter删除 drop查看 show 1.1创建数据库 CREATE DATABASE [IF NOT EXISTS] db_name    [crea ...

  2. [转载]PHP检测一个元素是否存在于数组中

  3. hdu1541 Stars 树状数组

    题目链接:http://acm.hdu.edu.cn/showproblem.php?pid=1541 题目大意就是统计其左上位置的星星的个数 由于y已经按升序排列,因此只用按照x坐标生成一维树状数组 ...

  4. Unite'17 Shanghai再一次问候

    Unite'17 Shanghai再一次问候 --暨Unity2017年度大会 2017年5月11日,主题为"再一次问候"的Unity年度盛会在上海国际会议中心举行,这是Unity ...

  5. Springmvc+mybatis+restful+bootstrap框架整合

    框架整合: Springmvc + Mybatis + Shiro(权限) + REST(服务) + WebService(服务) + JMS(消息) + Lucene(搜搜引擎) + Quartz( ...

  6. js事件中的event对象

    addEvent(oDiv,"click",function(event){ console.log(event.bubbles+"事件是否冒泡"); cons ...

  7. 开涛spring3(6.3) - AOP 之 6.3 基于Schema的AOP

    6.3  基于Schema的AOP 基于Schema的AOP从Spring2.0之后通过“aop”命名空间来定义切面.切入点及声明通知. 在Spring配置文件中,所以AOP相关定义必须放在<a ...

  8. python利用selenium和safari浏览器驱动实现新浪微博自动点赞 Demo

    import time from selenium import webdriver browser = webdriver.Safari() browser.get('http://weibo.co ...

  9. TCP--telnet为何在127s后返回？

    背景 近期编写了监控业务服务器的脚本,主要原理是用shell脚本(运行shell的机器称之为监控机)调用项目组专用的接口测试工具,对指定的业务服务器进行业务操作,根据接口测试工具的返回结果判断业务服务 ...

  10. YII缓存依赖的应用

    YII缓存依赖的应用 缓存 缓存依赖 Yii 缓存是提升Web应用性能的简便有效的方式.当我们在加载网页需要过多的时间,比如说查询时间过久,抑或是调用接口占用过多I/O,建立缓存是一个行之有效的方法, ...