每天进步一点点------DE2-70-TV例子说明

 module Reset_Delay(iCLK,iRST,oRST_0,oRST_1,oRST_2);
 input  iCLK;
 input  iRST;
 output reg oRST_0;
 output reg oRST_1;
 output reg oRST_2;

 reg [:] Cont;

 always@(posedge iCLK or negedge iRST)
 begin
  if(!iRST)
  begin
   Cont <= ;
   oRST_0 <= ;
   oRST_1 <= ;
   oRST_2 <= ;
  end
  else
  begin
   if(Cont!='h3FFFFF)
             Cont <= Cont + 'b1;
   if(Cont>='h1FFFFF)
             oRST_0 <= ;
   if(Cont>='h2FFFFF)
             oRST_1 <= ;
   if(Cont>='h3FFFFF)
             oRST_2 <= ;
  end
 end

 endmodule 

//-------------------------------------------------------------------------------
//  TD_Detect： 通过检测消隐的iTD_HS的个数判断数据是否稳定;iTD_VS高电平有效.
//VSYNC(低电平有效)    ------                                        ------
//                            ---      -----------------------------        -------------------
//HREF 高电平有效    --------------------------------------------------------------- 
//-------------------------------------------------------------------------------

 module TD_Detect
 (
    oTD_Stable,
    iTD_VS,//
    iTD_HS,
    iRST_N
 );
 input    iTD_VS;
 input    iTD_HS;
 input    iRST_N;
 output   oTD_Stable;
 reg    TD_Stable;
 reg    Pre_VS;
 reg [:]  Stable_Cont;
 //
 assign TD_Stable = iRST_N;
 assign oTD_Stable = TD_Stable;
 always@(posedge iTD_HS or negedge iRST_N)begin
  if(!iRST_N)
  begin
   TD_Stable <= 'b0;
   Stable_Cont <= 'h0;
   Pre_VS  <= 'b0;
  end
  else
  begin
   //
   Pre_VS <= iTD_VS;
   //
   if(!iTD_VS)//表示进入消隐区域
    Stable_Cont <= Stable_Cont+'b1;
   else
    Stable_Cont <= ;
   //
   if({Pre_VS,iTD_VS}=='b01)//表示从消隐去进入数据有效区
   begin
    if ((Stable_Cont==) || (Stable_Cont==))//24、25(PAL制式)分别是顶场和低场消隐的行数 通过判断消隐去的行数
     TD_Stable <= 'b1;          //判断数来据时PAL or NTSC制式 //GMK (Stable_Cont==9)NTSC制
    else
    TD_Stable <= 'b0;//数据不稳定产生复位
   end
  end
 end
 endmodule

//-------------------------------------------------------------------------------
//  Reset_Delay： TD_Detect 模块的TD_STABLE(低电平复位)信号做为复位信号，检测不到正常的格式则复位。
//      　　　　　　oDLY0(低电平复位)最先恢复正常，sdram、linebuffer等
//      　　　　　　oDLY1(低电平复位)第二恢复正常，ITU_656 Decoder等
//      　　　　　　oDLY2(低电平复位)最后恢复正常, 其他模块等
//-------------------------------------------------------------------------------

 module ITU_656_Decoder
 (
  // Control Signals
  input       iRST_N,
  input       iTD_CLK27,
  input       iSwap_CbCr,
  input       iSkip,
  // TV Decoder Input
  input   [:]   iTD_DAT,
  // Position Output
  output     [:]   oTV_X,
  output     [:]   oTV_Y,
  output   [:]  oTV_Cont,
  // YUV 4:2:2 Output
  output     [:]  oYCbCr,
  output        oDVAL
 );
 assign oTV_X  = Count>>;
 assign oTV_Y  = TV_Y;
 assign oYCbCr = YCbCr;
 assign oDVAL  = Data_Valid;
 assign oTV_Cont = Data_Cont;

 //
 reg   [:]  Window;
 wire  [:]  Window_N;
 always@(posedge iTD_CLK27 or negedge iRST_N)begin
  if(!iRST_N)
   Window <= 'h0;
  else
   Window <= Window_N;
 end
 assign Window_N = {Window[:],iTD_DAT};  

 //
 wire SAV;
 assign SAV = ((Window == 'hff0000) && (iTD_DAT[4] == 1'h0));

 reg  [:]  Count,Count_N;
 always@(posedge iTD_CLK27 or negedge iRST_N)begin
  if(!iRST_N)
   Count <= 'h0;
  else
   Count <= Count_N;
 end
 always@(*)begin
  if(SAV)
   Count_N = 'h0;
  else if(Count == )
   Count_N = Count;
  else
   Count_N = Count + 'h1;
 end

 reg  Active_Video,Active_Video_N;
 always@(posedge iTD_CLK27 or negedge iRST_N)begin
  if(!iRST_N)
   Active_Video <= 'h0;
  else
   Active_Video <= Active_Video_N;
 end
 always@(*)begin
  if(SAV)
   Active_Video_N = 'h1;
  else if(Count == )
   Active_Video_N = 'h0;
  else
   Active_Video_N = Active_Video;
 end 

 reg  Field,Field_N;
 always@(posedge iTD_CLK27 or negedge iRST_N)begin
  if(!iRST_N)
   Field <= 'h0;
  else
   Field <= Field_N;
 end
 always@(*)begin
  if(Window == 'hff0000)
   Field_N = iTD_DAT[];
  else
   Field_N = Field;
 end

 reg  Pre_Field;
 always@(posedge iTD_CLK27 or negedge iRST_N)begin
  if(!iRST_N)
   Pre_Field <= 'h0;
  else
   Pre_Field <= Field;
 end 

 reg  FVAL,FVAL_N;
 always@(posedge iTD_CLK27 or negedge iRST_N)begin
  if(!iRST_N)
   FVAL <= 'h0;
  else
   FVAL <= FVAL_N;
 end
 always@(*)begin
  if(Window == 'hff0000)
   FVAL_N = !iTD_DAT[];
  else
   FVAL_N = FVAL;
 end 

 reg  Start,Start_N;
 always@(posedge iTD_CLK27 or negedge iRST_N)begin
  if(!iRST_N)
   Start <= 'h0;
  else
   Start <= Start_N;
 end
 always@(*)begin
  if({Pre_Field,Field} == 'b10)
   Start_N = 'h1;
  else
   Start_N = Start;
 end 

 reg  Data_Valid,Data_Valid_N;
 always@(posedge iTD_CLK27 or negedge iRST_N)begin
  if(!iRST_N)
   Data_Valid <= 'h0;
  else
   Data_Valid <= Data_Valid_N;
 end
 always@(*)begin
  if(Start && Active_Video && FVAL && Count[] && !iSkip)
   Data_Valid_N = 'h1;
  else
   Data_Valid_N = 'h0;
 end 

 reg [:]  TV_Y,TV_Y_N;
 always@(posedge iTD_CLK27 or negedge iRST_N)begin
  if(!iRST_N)
   TV_Y <= 'h0;
  else
   TV_Y <= TV_Y_N;
 end
 always@(*)begin
  if(!FVAL)
   TV_Y_N = 'h0;
  else if(FVAL && SAV)
   TV_Y_N = TV_Y + 'h1;
  else
   TV_Y_N = TV_Y;
 end

 reg  [:]  Data_Cont,Data_Cont_N;
 always@(posedge iTD_CLK27 or negedge iRST_N)begin
  if(!iRST_N)
   Data_Cont <= 'h0;
  else
   Data_Cont <= Data_Cont_N;
 end
 always@(*)begin
  if(!FVAL)
   Data_Cont_N = 'h0;
  else if(Data_Valid)
   Data_Cont_N = Data_Cont + 'h1;
  else
   Data_Cont_N = Data_Cont;
 end

 reg  [:]  Cb,Cb_N;
 reg  [:]  Cr,Cr_N;
 reg  [:] YCbCr,YCbCr_N;

 always@(posedge iTD_CLK27 or negedge iRST_N)begin
  if(!iRST_N)
   begin
   Cb  <= ;
   Cr  <= ;
   YCbCr <= ;
   end
  else begin
   if(iSwap_CbCr)//商=1440/9
    case(Count[:])
     : Cb  = iTD_DAT;
     : YCbCr = {iTD_DAT,Cr};
     : Cr  = iTD_DAT;
     : YCbCr = {iTD_DAT,Cb};
    endcase
   else
    case(Count[:])
     : Cb  = iTD_DAT;
     : YCbCr = {iTD_DAT,Cb};
     : Cr  = iTD_DAT;
     : YCbCr = {iTD_DAT,Cr};
   endcase
  end
 end

 endmodule 

//------------------------------------------------------------------------------
//  ITU_656_Decoder ：本模块实现去除消隐区,并将一行720个像素减为640个
//                               oRESET_1(低电平复位)第二恢复正常，ITU_656 Decoder等
//                              “XY”为控制字。“XY”的8个bit含义如下：
//                               • Bit7（Const），常数，总为1。
//                               • Bit6（F）,场同步信号，表示该行数据处于奇场还是偶场。
//                               • Bit5（V）,垂直同步信号，表示处于场消隐区间还是正程区间（有效数据行）。
//                               • Bit4（H）,水平同步信号，表示是“SAV”还是“EAV”。
//                               • Bit3-0（P3P2P1P0,纠错位。P3=V(XOR)H;P2=F(XOR)H;P1=F(XOR)V;P0=F(XOR)V(XOR)H。
//                              其中， F：标记场信息，传输顶场时为0，传输底场时为1
//                                       V：标记消隐信息，传输消隐数据时为1，传输有效视频数据时为0
//                                       H：标记EAV还是SAV，SAV为0，EAV为1
//-------------------------------------------------------------------------------