vhdl基础---分频

偶数分频

 ibrary IEEE;
 use IEEE.STD_LOGIC_1164.ALL;
 use ieee.std_logic_arith;
 use ieee.std_logic_unsigned;

 entity test_1 is
     generic (n: integer:=);
     port(
             clkin: in std_logic;-----rate=n,n is odd;
             clkout: out std_logic ---relative FPGA,clkout is out signal;
     );
 end test_1;

 architecture Behavioral of test_1 is
     signal cnt:integer range  to n-;
 begin
     process (clkin)------count
     begin
         if (clkin'event and clkin='') then
             if(cnt<n-) then
                 cnt<=cnt+;
             else
                 cnt<=;
             end if;
         end if;
     end process;

     process(cnt) -----根据计数值，控制输出始终脉冲的高低电平
     begin
         if(cnt<n/) then
             clkout<='';
         else
             clkout<='';
         end if;
     end process;

 end Behavioral;

 library IEEE;
 use IEEE.STD_LOGIC_1164.ALL;
 use ieee.std_logic_arith;
 use ieee.std_logic_unsigned;

 -- Uncomment the following library declaration if using
 -- arithmetic functions with Signed or Unsigned values
 --use IEEE.NUMERIC_STD.ALL;

 -- Uncomment the following library declaration if instantiating
 -- any Xilinx primitives in this code.
 --library UNISIM;
 --use UNISIM.VComponents.all;

 entity test_1 is
     generic (n: integer:=);
     port(
             clkin: in std_logic;-----rate=n,n is odd;
             clkout: out std_logic ---relative FPGA,clkout is out signal;
     );
 end test_1;

 architecture Behavioral of test_1 is
     signal cnt:integer range  to n/-;
     signal temp :std_logic;
 begin
     process (clkin)------count
     begin
         if (clkin'event and clkin='') then
             if(cnt=n/-) then
                 cnt<=;
                 temp<=not temp;
             else
                 cnt<=cnt+;
             end if;
         end if;
     end process;

     clkout<=temp;---clkout和temp都是信号，均可传出来

 end Behavioral;

奇偶分频

 entity test_1 is
     generic (n: integer:=);
     port(
             clkin: in std_logic;-----rate=n,n is 偶数;
             clkout: out std_logic ---relative FPGA,clkout is out signal;
     );
 end test_1;

 architecture Behavioral of test_1 is
     signal cnt1,cnt2:integer range  to n/-;

 begin
     process (clkin)------count
     begin
     if (clkin'event and clkin='') then ------上升沿计数
         if(cnt1<n-) then
                 cnt1<=cnt1+;

             else
                 cnt1<=;
             end if;
         end if;
     end process;

     process (clkin)------count
     begin
     if (clkin'event and clkin='') then ------下升沿计数
         if(cnt2<n-) then
                 cnt2<=cnt2+;

             else
                 cnt2<=;
             end if;
         end if;
     end process;

     clkout<='' when cnt1<(n-)/ else
                 '' when cnt2<(n-)/;

 end Behavioral;

占空标准

 entity test_1 is----占空比3：: 的偶数分频器
                     -----当计数值为0-2时，输出高电平，到计数值为
                     ----9时，输出低电平
     generic (
                 n: integer:=;
                 m: integer:=  ----占空比为m:n,rate=n;
                 );
     port(
             clkin: in std_logic;-----rate=n,n is 偶数;
             clkout: out std_logic ---relative FPGA,clkout is out signal;
     );
 end test_1;

 architecture Behavioral of test_1 is
     signal cnt1:integer range  to n-;

 begin
     process (clkin)------count
     begin
     if (clkin'event and clkin='') then ------上升沿计数
         if(cnt1<n-) then
                 cnt1<=cnt1+;

             else
                 cnt1<=;
             end if;
         end if;
     end process;

     clkout<='' when cnt1<m else
                 '' ;

 end Behavioral;