【基本知识】UART接口

1.简介

　　（1）UART一种通用异步串口数据总线，最低采用两路信号（TX/RX）即可实现全双工通信，十分简单；

　　（2）UART采用LSB模式传输，串口数据传输格式如下图所示：

　　　　起始位：长度为1位的时间，用于表示发送字符的开始；

　　　　数据位：长度长度不固定，一般是8位；

　　　　校验位：可以加也可以不加。

　　　　停止位：一般是1位、1.5位、2位长度，用于告知接收端字符传输结束；

　　（3）每个字符的发送都需要有起始位和停止位，对于连续数据也是如此；

2.内部结构

3.实现

　　发送模块代码如下：

 module uart_tx_path #
 (
 parameter BAUD_DIV     = 'd9,      //baud
 parameter BAUD_DIV_CAP = 'd4       //baud capture point
 )
 (
    input      clk,           //main clk
    input      rst_n,             //reset
    input      uart_tx_en,        //send one byte data enable
    input[:] uart_tx_byte,         //one byte data
    output     uart_txd,          //the txd pin
    output     uart_tx_done     //send one byte data done
 );
 
 //-------------------------   Baud rate generator   -------------------------
 reg[:] cnt_baud_div;
 reg      baud_cap;
 reg      baud_start;
 
 always@(posedge clk or negedge rst_n)
 begin
    if(!rst_n) begin
       cnt_baud_div <= 'd0;
       end
    else begin
       if(baud_start) begin
          if(cnt_baud_div >= BAUD_DIV) begin
             cnt_baud_div <= 'd0;
             end
          else begin
             cnt_baud_div <= cnt_baud_div + 'b1;
             end
          end
       else begin
          cnt_baud_div <= 'd0;
          end
       end
 end
 
 always@(posedge clk or negedge rst_n)
 begin
    if(!rst_n) begin
       baud_cap <= 'b0;
       end
    else begin
       if(cnt_baud_div==BAUD_DIV_CAP) begin
          baud_cap <= 'b1;
          end
       else begin
          baud_cap <= 'b0;
          end
       end
 end
 
 //-------------------------capture the uart_tx_en posedge-------------------------
 reg  uart_tx_en_r0,uart_tx_en_r1;
 wire uart_tx_en_p;
 
 always@(posedge clk or negedge rst_n)
 begin
    if(!rst_n) begin
       uart_tx_en_r0 <= 'b0;      //uart_tx_en of the idle state is low
       uart_tx_en_r1 <= 'b0;
       end
     else begin
       uart_tx_en_r0 <= uart_tx_en;
       uart_tx_en_r1 <= uart_tx_en_r0;
       end
 end
 
 assign uart_tx_en_p = (~uart_tx_en_r1 & uart_tx_en_r0)? 'b1:1'b0;      //capture the uart_tx_en posedge
 
 //-------------------------   capture the txd data   -------------------------
 localparam TX_IDLE = 'b0;
 localparam TX_WORK = 'b1;
 
 reg      state_tx;
 reg         uart_tx_done_r;
 reg[:] send_data;
 reg[:] tx_bit;
 
 always@(posedge clk or negedge rst_n)
 begin
    if(!rst_n) begin
       state_tx <= TX_IDLE;
       send_data <= 'b1111_1111_11;
       uart_tx_done_r <= 'b0;
       end
    else begin
       case(state_tx)
          TX_IDLE: if(uart_tx_en_p) begin
                      baud_start <= 'b1;
                      send_data <= {'b1,uart_tx_byte,1'b0};
                      state_tx <= TX_WORK;
                      uart_tx_done_r <= 'b0;
                      end
                   else begin
                      baud_start <= 'b0;
                      send_data <= 'b1111_1111_11;
                      state_tx <= TX_IDLE;
                      uart_tx_done_r <= 'b0;
                      end
          TX_WORK: if(tx_bit == 'd10) begin
                      baud_start <= 'b1;
                      send_data <= 'b1111_1111_11;
                      state_tx <= TX_WORK;
                      uart_tx_done_r <= 'b0;
                      end
                   else if(tx_bit>='d11) begin
                      baud_start <= 'b0;
                      send_data <= 'b1111_1111_11;
                      state_tx <= TX_IDLE;
                      uart_tx_done_r <= 'b1;
                      end
                   else begin
                      baud_start <= 'b1;
                      send_data <= send_data;
                      state_tx <= TX_WORK;
                      uart_tx_done_r <= 'b0;
                      end
          default: ;
       endcase
       end
 end
 //-------------------------   the uart txd work   -------------------------
 reg      uart_txd_r;
 
 always@(posedge clk or negedge rst_n)
 begin
    if(!rst_n) begin
       uart_txd_r <= 'b1;      //uart_txd of the idle state is high
       tx_bit <= 'd0;
       end
    else begin
       if(state_tx == TX_WORK) begin
          if(baud_cap) begin
             if (tx_bit <= 'd9)
             uart_txd_r <= send_data[tx_bit];
             else
             uart_txd_r <= 'b1;
             tx_bit <= tx_bit + 'b1;
             end
          else begin
             uart_txd_r <= uart_txd_r;
             tx_bit <= tx_bit;
             end
          end
       else begin
          uart_txd_r <= 'b1;
          tx_bit <= 'd0;
          end
       end
 end
 
 assign uart_tx_done = uart_tx_done_r;
 assign uart_txd = uart_txd_r;
 
 endmodule

UART_TX_PATH

　　接收模块代码如下：

 module uart_rx_path #
 (
 parameter BAUD_DIV     = 'd9,      //baud
 parameter BAUD_DIV_CAP = 'd4       //baud capture point
 )
 (
    input        clk,           //main clk
    input        rst_n,             //reset
    input        uart_rxd,          //the rxd pin
    output       uart_rx_done,      //receive one byte data done
    output[:]  uart_rx_byte       //one byte data
    );
 
 //-------------------------   Baud rate generator   -------------------------
 reg[:] cnt_baud_div;
 reg      baud_cap;
 reg      baud_start;
 
 always@(posedge clk or negedge rst_n)
 begin
    if(!rst_n) begin
       cnt_baud_div <= 'd0;
       end
    else begin
       if(baud_start) begin
          if(cnt_baud_div >= BAUD_DIV) begin
             cnt_baud_div <= 'd0;
             end
          else begin
             cnt_baud_div <= cnt_baud_div + 'b1;
             end
          end
       else begin
          cnt_baud_div <= 'd0;
          end
       end
 end
 
 always@(posedge clk or negedge rst_n)
 begin
    if(!rst_n) begin
       baud_cap <= 'b0;
       end
    else begin
       if(cnt_baud_div==BAUD_DIV_CAP) begin
          baud_cap <= 'b1;
          end
       else begin
          baud_cap <= 'b0;
          end
       end
 end
 
 //-------------------------   capture the uart start bit   -------------------------
 reg uart_rxd_r0,uart_rxd_r1,uart_rxd_r2,uart_rxd_r3;
 wire uart_rxd_n;
 
 always@(posedge clk or negedge rst_n)
 begin
    if(!rst_n) begin
       uart_rxd_r0 <= 'b1;      //uart_rxd of the idle state is high
       uart_rxd_r1 <= 'b1;
       uart_rxd_r2 <= 'b1;
       uart_rxd_r3 <= 'b1;
       end
     else begin
       uart_rxd_r0 <= uart_rxd;
       uart_rxd_r1 <= uart_rxd_r0;
       uart_rxd_r2 <= uart_rxd_r1;
       uart_rxd_r3 <= uart_rxd_r2;
       end
 end
 
 assign uart_rxd_n = (uart_rxd_r3 & uart_rxd_r2 & ~uart_rxd_r1 & ~uart_rxd_r0)? 'b1 : 1'b0;      //capture the uart_rxd negedge
 
 //-------------------------   the uart rxd work   -------------------------
 localparam[:] UART_IDLE = 'd0;      //IDLE
 localparam[:] UART_START= 'd1;      //START BIT
 localparam[:] UART_BIT0 = 'd2;      //BIT0
 localparam[:] UART_BIT1 = 'd3;      //BIT1
 localparam[:] UART_BIT2 = 'd4;      //BIT2
 localparam[:] UART_BIT3 = 'd5;      //BIT3
 localparam[:] UART_BIT4 = 'd6;      //BIT4
 localparam[:] UART_BIT5 = 'd7;      //BIT5
 localparam[:] UART_BIT6 = 'd8;      //BIT6
 localparam[:] UART_BIT7 = 'd9;      //BIT7
 localparam[:] UART_STOP = 'd10;     //STOP BIT
 
 reg[:] state_rx;
 reg      uart_rx_done_r;
 reg[:] uart_rx_byte_r0;
 reg[:] uart_rx_byte_r1;
 
 always@(posedge clk or negedge rst_n)
 begin
    if(!rst_n) begin
       state_rx <= UART_IDLE;
       uart_rx_done_r <= 'b0;
       uart_rx_byte_r0 <= 'd0;
       uart_rx_byte_r1 <= 'd0;
       baud_start <= 'b0;
       end
    else begin
       case(state_rx)
          UART_IDLE: if(uart_rxd_n) begin
                        uart_rx_done_r <= 'b0;
                        baud_start <= 'b1;
                        state_rx <= UART_START;
                        end
                     else begin
                        uart_rx_done_r <= 'b0;
                        baud_start <= 'b0;
                        state_rx <= UART_IDLE;
                        end
          UART_START: if(baud_cap) begin
                         state_rx <= UART_BIT0;
                         end
                      else begin
                         state_rx <= UART_START;
                         end
          UART_BIT0: if(baud_cap) begin
                         uart_rx_byte_r0[] <= uart_rxd;
                         state_rx <= UART_BIT1;
                         end
                      else begin
                         uart_rx_byte_r0 <= uart_rx_byte_r0;
                         state_rx <= UART_BIT0;
                         end
          UART_BIT1: if(baud_cap) begin
                         uart_rx_byte_r0[] <= uart_rxd;
                         state_rx <= UART_BIT2;
                         end
                      else begin
                         uart_rx_byte_r0 <= uart_rx_byte_r0;
                         state_rx <= UART_BIT1;
                         end
          UART_BIT2: if(baud_cap) begin
                         uart_rx_byte_r0[] <= uart_rxd;
                         state_rx <= UART_BIT3;
                         end
                      else begin
                         uart_rx_byte_r0 <= uart_rx_byte_r0;
                         state_rx <= UART_BIT2;
                         end
          UART_BIT3: if(baud_cap) begin
                         uart_rx_byte_r0[] <= uart_rxd;
                         state_rx <= UART_BIT4;
                         end
                      else begin
                         uart_rx_byte_r0 <= uart_rx_byte_r0;
                         state_rx <= UART_BIT3;
                         end
          UART_BIT4: if(baud_cap) begin
                         uart_rx_byte_r0[] <= uart_rxd;
                         state_rx <= UART_BIT5;
                         end
                      else begin
                         uart_rx_byte_r0 <= uart_rx_byte_r0;
                         state_rx <= UART_BIT4;
                         end
          UART_BIT5: if(baud_cap) begin
                         uart_rx_byte_r0[] <= uart_rxd;
                         state_rx <= UART_BIT6;
                         end
                      else begin
                         uart_rx_byte_r0 <= uart_rx_byte_r0;
                         state_rx <= UART_BIT5;
                         end
          UART_BIT6: if(baud_cap) begin
                         uart_rx_byte_r0[] <= uart_rxd;
                         state_rx <= UART_BIT7;
                         end
                      else begin
                         uart_rx_byte_r0 <= uart_rx_byte_r0;
                         state_rx <= UART_BIT6;
                         end
          UART_BIT7: if(baud_cap) begin
                         uart_rx_byte_r0[] <= uart_rxd;
                         state_rx <= UART_STOP;
                         end
                      else begin
                         uart_rx_byte_r0 <= uart_rx_byte_r0;
                         state_rx <= UART_BIT7;
                         end
          UART_STOP: if(baud_cap) begin
                        uart_rx_done_r <= 'b1;
                        uart_rx_byte_r1 <= uart_rx_byte_r0;
                        baud_start <= 'b0;
                        state_rx <= UART_IDLE;
                        end
                     else begin
                        uart_rx_done_r <= 'b0;
                        uart_rx_byte_r1 <= uart_rx_byte_r1;
                        baud_start <= 'b1;
                        state_rx <= UART_STOP;
                        end
          default: state_rx <= UART_IDLE;
       endcase
       end
 end
 
 assign uart_rx_done = uart_rx_done_r;
 assign uart_rx_byte = uart_rx_byte_r1;
 endmodule

UART_RX_PATH

4.参考资料

　　《通信IC设计》李庆华著

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