s3c2440 移值u-boot-2016.03 第6篇支持mtd yaffs 烧写

1, 解决启动时的错误
Warning - bad CRC, using default environment
搜索发现在 /tools/env/fw_env.c 中
/* 放在NAND FLASH 中大小 128K 开始地址 */
#define CONFIG_ENV_IS_IN_NAND
#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10)
#define CONFIG_ENV_OFFSET (256<<10)
#define CONFIG_ENV_SIZE CONFIG_SYS_ENV_SECT_SIZE

2, 添加 MTD
#define CONFIG_CMD_MTDPARTS /* Enable MTD parts commands */
#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
#define MTDIDS_DEFAULT "nand0=nand"
#define MTDPARTS_DEFAULT "mtdparts=nand:256k(uboot),"\
"128k(env),"\
"2m(kernel),-(fs)"

在 /common/board_r.c
man_loop 中添加
run_command("mtdparts default", 0);

擦除 nand flash
nand erase.part uboot
nand write 0x30000000 uboot

3, 下载试验

nfs 0x30000000 192.168.1.10:/nfs/fs.yaffs2
nand erase.part fs
nand write.yaffs 0x30000000 0x00260000 0x8607c0 (文件大小)
set bootargs noinitrd root=/dev/mtdblock3 init=/linuxrc console=ttySAC0
boot 启动

写入出错
Unknown nand command suffix '.yaffs2'

4, 支持 yaffs2

在 smdk2440.h 发现有个，配置后 #define CONFIG_YAFFS2

编译后，大了很多，有 335K ，菜单多了几个功能
yls - yaffs ls
ymkdir - YAFFS mkdir
ymount - mount yaffs
ymv - YAFFS mv
yrd - read file from yaffs
yrdm - read file to memory from yaffs
yrm - YAFFS rm
yrmdir - YAFFS rmdir
ytrace - show/set yaffs trace mask
yumount - unmount yaffs
ywr - write file to yaffs
ywrm - write file from memory to yaffs

试着挂载，失败，文档也没有找到，导致 u-boot 也非常大，换一种方法。

之前可以使用 #define CONFIG_CMD_NAND_YAFFS
对比了 u-boot 2013 2014 2015 都有这个功能，但从 2015-10 移除了
参考u-boot 2015修改代码添加支持
/* 添加兼容 yaffs2 烧写支持 */
/include/configs/smdk2440.h
#define CONFIG_CMD_NAND_YAFFS
/cmd/nand.c
在543line:
if (strncmp(cmd, "read", 4) == 0 || strncmp(cmd, "write", 5) == 0) {
里面添加 622line:
#ifdef CONFIG_CMD_NAND_YAFFS
} else if (!strcmp(s, ".yaffs")) {
if (read) {
printf("Unknown nand command suffix '%s'.\n", s);
return 1;
}
ret = nand_write_skip_bad(nand, off, &rwsize, NULL,
maxsize, (u_char *)addr,
WITH_YAFFS_OOB);
#endif

/include/nand.h 101line: 添加
#define WITH_YAFFS_OOB (1 << 0) /* whether write with yaffs format. This flag * is a 'mode' meaning it cannot be mixed with * other flags */

/drivers/mtd/nand/nand_util.c 583line:
#ifdef CONFIG_CMD_NAND_YAFFS
if (flags & WITH_YAFFS_OOB) {
if (flags & ~WITH_YAFFS_OOB)
return -EINVAL;

int pages;
pages = nand->erasesize / nand->writesize;
blocksize = (pages * nand->oobsize) + nand->erasesize;
if (*length % (nand->writesize + nand->oobsize)) {
printf("Attempt to write incomplete page"
" in yaffs mode\n");
return -EINVAL;
}
} else
#endif

666line:
#ifdef CONFIG_CMD_NAND_YAFFS
if (flags & WITH_YAFFS_OOB) {
int page, pages;
size_t pagesize = nand->writesize;
size_t pagesize_oob = pagesize + nand->oobsize;
struct mtd_oob_ops ops;

ops.len = pagesize;
ops.ooblen = nand->oobsize;
ops.mode = MTD_OPS_AUTO_OOB;
ops.ooboffs = 0;

pages = write_size / pagesize_oob;
for (page = 0; page < pages; page++) {
WATCHDOG_RESET();

ops.datbuf = p_buffer;
ops.oobbuf = ops.datbuf + pagesize;

rval = mtd_write_oob(nand, offset, &ops);
if (rval != 0)
break;

offset += pagesize;
p_buffer += pagesize_oob;
}
}
else
#endif
{
这里要包含下面的部分。最后 u-boot 改完后，会有大补丁。大家可以下载比较。
..............
}
编译后，252K
重新烧写出错
NAND write to offset 2a1000 failed -22 0 bytes written: ERROR
ops.mode = MTD_OPS_RAW; 这里也要改。

最终完成了，可以烧写 yaffs2 ，也能使用 NAND FLASH NOR FLASH ，网卡， u-boot 差不多结束了。

2016.03.u-boot 补丁

 diff -urN u-boot-2016.03/arch/arm/cpu/arm920t/init.c u-boot-.03ok/arch/arm/cpu/arm920t/init.c
 --- u-boot-2016.03/arch/arm/cpu/arm920t/init.c    -- ::00.000000000 +
 +++ u-boot-.03ok/arch/arm/cpu/arm920t/init.c    -- ::00.645377559 +
 @@ -, +, @@
 +/* NAND FLASH控制器 */
 +#define NFCONF (*((volatile unsigned long *)0x4E000000))
 +#define NFCONT (*((volatile unsigned long *)0x4E000004))
 +#define NFCMMD (*((volatile unsigned char *)0x4E000008))
 +#define NFADDR (*((volatile unsigned char *)0x4E00000C))
 +#define NFDATA (*((volatile unsigned char *)0x4E000010))
 +#define NFSTAT (*((volatile unsigned char *)0x4E000020))
 +
 +/* CLK */
 +#define CLKDIVN  (*(volatile unsigned long *)0x4C000014)
 +#define MPLLCON  (*(volatile unsigned long *)0x4C000004)
 +
 +/* SDRAM */
 +#define BWSCON    (*(volatile unsigned long *)0x48000000)
 +#define BANKCON4  (*(volatile unsigned long *)0x48000014)
 +#define BANKCON6  (*(volatile unsigned long *)0x4800001c)
 +#define REFRESH   (*(volatile unsigned long *)0x48000024)
 +#define BANKSIZE  (*(volatile unsigned long *)0x48000028)
 +#define MRSRB6    (*(volatile unsigned long *)0x4800002c)
 +
 +void init_clock(void)
 +{
 +    //Mpll = 400M
 +    MPLLCON = (0x5c<<) | (<<) | ;
 +    //FCLK 400M HCLK 100M PCLK 50M
 +    CLKDIVN = << | <<;
 +    __asm__(
 +        "mrc  p15,0,r0,c1,c0,0\n"
 +        "orr  r0,r0,#0xc0000000\n"
 +        "mcr  p15,0,r0,c1,c0,0\n"
 +    );
 +}
 +
 +void init_sdram(void)
 +{
 +    #if 0
 +    BWSCON   = <<;
 +    BANKCON6 = << | << | ;
 +    REFRESH  = (<<) + ;
 +    BANKSIZE = << | << | ;
 +    MRSRB6   = 0x30;
 +    #else
 +    BWSCON   = << | <<;
 +    BANKCON4 = 0x00000740;
 +    BANKCON6 = << | << | ;
 +    REFRESH  = (<<) + ;
 +    BANKSIZE = << | << | ;
 +    MRSRB6   = 0x30;
 +    #endif
 +}
 +
 +void clear_bss(void)
 +{
 +    extern int __bss_start, __bss_end;
 +    int *p = &__bss_start;
 +
 +    for (; p < &__bss_end; p++)
 +    {
 +        *p = ;
 +    }
 +}
 +
 +static void nand_latency(void)
 +{
 +    int i=;
 +    while(i--);
 +}
 +
 +static void nand_is_ready(void)
 +{
 +    //bit 0 : 1 不忙了
 +    while(! (NFSTAT & ));
 +}
 +
 +static void nand_write_addr(unsigned int addr)
 +{
 +    int col, page;
 +    col = addr % ;
 +    page = addr / ;
 +
 +    NFADDR = col & 0xff;            /* Column Address A0~A7 */
 +    nand_latency();
 +    NFADDR = (col >> ) & 0x0f;     /* Column Address A8~A11 */
 +    nand_latency();
 +    NFADDR = page & 0xff;            /* Row Address A12~A19 */
 +    nand_latency();
 +    NFADDR = (page >> ) & 0xff;    /* Row Address A20~A27 */
 +    nand_latency();
 +    NFADDR = (page >> ) & 0x03;    /* Row Address A28~A29 */
 +    nand_latency();
 +}
 +
 +static unsigned char nand_read_char(void)
 +{
 +    //只保留8个bit
 +    return NFDATA & 0xff;
 +}
 +
 +static void nand_cmd(unsigned char cmd)
 +{
 +    NFCMMD = cmd;
 +    nand_latency();
 +}
 +
 +static void nand_select_chip(void)
 +{
 +    //1bit : 0 选中
 +    NFCONT &= ~(<<);
 +}
 +
 +static void nand_deselect_chip(void)
 +{
 +    //1bit : 1 选中
 +    NFCONT |= (<<);
 +}
 +
 +static void nand_reset(void)
 +{
 +    nand_select_chip();
 +    nand_cmd(0xff);
 +    nand_deselect_chip();
 +}
 +
 +void nand_init_ll(void)
 +{
 +    //TACLS 3.3v 时 12ns
 +    #define TACLS   0
 +    //12ns
 +    #define TWRPH0  1
 +    //5ns
 +    #define TWRPH1  0
 +    NFCONF = TACLS<< | TWRPH0<< |  TWRPH1<<;
 +    /* 4 ECC
 +     * 1 CE 先不选中，用的时候在选中
 +     * 0 启动 flash controller
 +     */
 +    NFCONT = << | << | ;
 +    nand_reset();
 +}
 +
 +static void nand_read(unsigned int addr, unsigned char *buf, int len)
 +{
 +    //选中
 +    nand_select_chip();
 +    //j 地址可能不是从0对齐开始读的
 +    unsigned int i = addr,j = addr % ;
 +    for(; i<(addr + len);)
 +    {
 +        //读命令
 +        nand_cmd(0x00);
 +        nand_is_ready();
 +
 +        //发送地址
 +        nand_write_addr(i);
 +        nand_is_ready();
 +
 +        //在次发出读命令
 +        nand_cmd(0x30);
 +        nand_is_ready();
 +        //读2K
 +        for(; j<; j++)
 +        {
 +            *buf = nand_read_char();
 +            buf++;
 +            i++;
 +        }
 +        j=;
 +        nand_latency();
 +    }
 +    //取消选中
 +    nand_deselect_chip();
 +}
 +
 +static int boot_is_nor()
 +{
 +    //利用 NOR 不能写的特点判断
 +    volatile unsigned int *p = (volatile unsigned int *);
 +    unsigned int val;
 +    val = *p;
 +    *p = 0x12345678;
 +    if(0x12345678 == *p)
 +    {
 +        *p = val;
 +        return ;
 +    }
 +    return ;
 +}
 +
 +//片内4K 的程序要复制到链接SDRAM中去
 +void copy_code_to_sdram(unsigned char *src,unsigned char *dst,int len)
 +{
 +    int i = ;
 +    if(boot_is_nor())
 +    {
 +        while(i < len)
 +        {
 +            dst[i] = src[i];
 +            i++;
 +        }
 +    }
 +    else
 +    {
 +        nand_read((int)src, dst, len);
 +    }
 +}
 +
 diff -urN u-boot-2016.03/arch/arm/cpu/arm920t/Makefile u-boot-.03ok/arch/arm/cpu/arm920t/Makefile
 --- u-boot-2016.03/arch/arm/cpu/arm920t/Makefile    -- ::21.000000000 +
 +++ u-boot-.03ok/arch/arm/cpu/arm920t/Makefile    -- ::31.767626866 +
 @@ -, +, @@
  extra-y    = start.o
 
  obj-y    += cpu.o
 +obj-y    += init.o
  obj-$(CONFIG_USE_IRQ)    += interrupts.o
 
  obj-$(CONFIG_EP93XX) += ep93xx/
 diff -urN u-boot-2016.03/arch/arm/cpu/arm920t/start.S u-boot-.03ok/arch/arm/cpu/arm920t/start.S
 --- u-boot-2016.03/arch/arm/cpu/arm920t/start.S    -- ::21.000000000 +
 +++ u-boot-.03ok/arch/arm/cpu/arm920t/start.S    -- ::31.782641369 +
 @@ -, +, @@
 
      /* FCLK:HCLK:PCLK = 1:2:4 */
      /* default FCLK is 120 MHz ! */
 -    ldr    r0, =CLKDIVN
 -    mov    r1, #
 -    str    r1, [r0]
 +    //ldr    r0, =CLKDIVN
 +    //mov    r1, #3
 +     //str    r1, [r0]
 +
 +    /* 设置分频参数 */
 +    ldr r0, =CLKDIVN
 +    mov r1, #0x05;    /* FCLK:HCLK:PCLK=1:4:8 */
 +    str r1, [r0]
 +
 +    /* 如果HDIVN非0，CPU的总线模式应该从“fast bus mode”变为“asynchronous bus mode” */
 +    mrc    p15, , r1, c1, c0,         /* 读出控制寄存器 */
 +    orr    r1, r1, #0xc0000000            /* 设置为“asynchronous bus mode” */
 +    mcr    p15, , r1, c1, c0,         /* 写入控制寄存器 */
 +
 +    /* 配置时钟 */
 +    #define S3C2440_MPLL_400MHZ     ((0x5c<<12)|(0x01<<4)|(0x01))
 +    ldr r0, =0x4c000004
 +    ldr r1, =S3C2440_MPLL_400MHZ
 +    str r1, [r0]
 +
  #endif    /* CONFIG_S3C24X0 */
 
 +    /**
 +         * 调用 init.c 中的初始化
 +         * 因为已经初始化好内存 所以 sp 在 顶部
 +         * 在 NOR 时不能用片内 4K
 +         */
 +        ldr sp, =
 +        bl init_sdram
 +        ldr sp, =0x34000000
 +        bl nand_init_ll
 +        /**
 +         * 从 0 地址开始复制 到 SDRAM 中
 +         * 在 smdk2440.h 中定义 #define CONFIG_SYS_TEXT_BASE
 +         * u-boot 的加载地址
 +         */
 +        mov r0,#
 +        ldr r1, =CONFIG_SYS_TEXT_BASE
 +        ldr r2, =__bss_start
 +        sub r2, r2, r1
 +        bl copy_code_to_sdram
 +        bl clear_bss
 +        ldr pc, =_main
 +
      /*
       * we do sys-critical inits only at reboot,
       * not when booting from ram!
 @@ -95,8 +134,6 @@
      bl    cpu_init_crit
  #endif
 
 -    bl    _main
 -
  /*------------------------------------------------------------------------------*/
 
      .globl    c_runtime_cpu_setup
 diff -urN u-boot-2016.03/arch/arm/cpu/u-boot.lds u-boot-.03ok/arch/arm/cpu/u-boot.lds
 --- u-boot-2016.03/arch/arm/cpu/u-boot.lds    -- ::21.000000000 +
 +++ u-boot-.03ok/arch/arm/cpu/u-boot.lds    -- ::12.338040880 +
 @@ -, +, @@
       */
      /DISCARD/ : { *(.rel._secure*) }
  #endif
 -    . = 0x00000000;
 +    . = ;
 
      . = ALIGN();
      .text :
 diff -urN u-boot-2016.03/arch/arm/Kconfig u-boot-.03ok/arch/arm/Kconfig
 --- u-boot-2016.03/arch/arm/Kconfig    -- ::21.000000000 +
 +++ u-boot-.03ok/arch/arm/Kconfig    -- ::52.118143749 +
 @@ -, +, @@
  config TARGET_SMDK2410
      bool "Support smdk2410"
      select CPU_ARM920T
 +
 +config TARGET_SMDK2440
 +    bool "Support smdk2440"
 +    select CPU_ARM920T
 
  config TARGET_ASPENITE
      bool "Support aspenite"
 @@ -, +, @@
  source "board/phytec/pcm052/Kconfig"
  source "board/ppcag/bg0900/Kconfig"
  source "board/samsung/smdk2410/Kconfig"
 +source "board/samsung/smdk2440/Kconfig"
  source "board/sandisk/sansa_fuze_plus/Kconfig"
  source "board/schulercontrol/sc_sps_1/Kconfig"
  source "board/siemens/draco/Kconfig"
 diff -urN u-boot-2016.03/arch/arm/lib/crt0.S u-boot-.03ok/arch/arm/lib/crt0.S
 --- u-boot-2016.03/arch/arm/lib/crt0.S    -- ::21.000000000 +
 +++ u-boot-.03ok/arch/arm/lib/crt0.S    -- ::44.287690421 +
 @@ -, +, @@
   * relocate_code(addr_moni). Trick here is that we'll return
   * 'here' but relocated.
   */
 -
      ldr    sp, [r9, #GD_START_ADDR_SP]    /* sp = gd->start_addr_sp */
  #if defined(CONFIG_CPU_V7M)    /* v7M forbids using SP as BIC destination */
      mov    r3, sp
 @@ -, +, @@
 
      bl    c_runtime_cpu_setup    /* we still call old routine here */
  #endif
 +
 +
  #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_FRAMEWORK)
 -# ifdef CONFIG_SPL_BUILD
 +#ifdef CONFIG_SPL_BUILD
      /* Use a DRAM stack for the rest of SPL, if requested */
      bl    spl_relocate_stack_gd
      cmp    r0, #
      movne    sp, r0
      movne    r9, r0
 -# endif
 +#endif
 +
      ldr    r0, =__bss_start    /* this is auto-relocated! */
 
  #ifdef CONFIG_USE_ARCH_MEMSET
 @@ -, +, @@
  #endif
 
  ENDPROC(_main)
 +
 diff -urN u-boot-2016.03/arch/arm/lib/relocate.S u-boot-.03ok/arch/arm/lib/relocate.S
 --- u-boot-2016.03/arch/arm/lib/relocate.S    -- ::21.000000000 +
 +++ u-boot-.03ok/arch/arm/lib/relocate.S    -- ::48.481661370 +
 @@ -, +, @@
 
  ENTRY(relocate_vectors)
 
 +
  #ifdef CONFIG_CPU_V7M
      /*
       * On ARMv7-M we only have to write the new vector address
 diff -urN u-boot-2016.03/board/samsung/smdk2440/Kconfig u-boot-2016.03ok/board/samsung/smdk2440/Kconfig
 --- u-boot-2016.03/board/samsung/smdk2440/Kconfig    1970-01-01 07:00:00.000000000 +0700
 +++ u-boot-2016.03ok/board/samsung/smdk2440/Kconfig    2016-05-18 15:00:45.794906725 +0800
 @@ -0,0 +1,15 @@
 +if TARGET_SMDK2440
 +
 +config SYS_BOARD
 +    default "smdk2440"
 +
 +config SYS_VENDOR
 +    default "samsung"
 +
 +config SYS_SOC
 +    default "s3c24x0"
 +
 +config SYS_CONFIG_NAME
 +    default "smdk2440"
 +
 +endif
 diff -urN u-boot-2016.03/board/samsung/smdk2440/lowlevel_init.S u-boot-2016.03ok/board/samsung/smdk2440/lowlevel_init.S
 --- u-boot-2016.03/board/samsung/smdk2440/lowlevel_init.S    1970-01-01 07:00:00.000000000 +0700
 +++ u-boot-2016.03ok/board/samsung/smdk2440/lowlevel_init.S    2016-05-18 15:00:45.654313065 +0800
 @@ -0,0 +1,147 @@
 +/*
 + * Memory Setup stuff - taken from blob memsetup.S
 + *
 + * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and
 + *                     Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl)
 + *
 + * Modified for the Samsung SMDK2410 by
 + * (C) Copyright 2002
 + * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
 + *
 + * SPDX-License-Identifier:    GPL-2.0+
 + */
 +
 +
 +#include <config.h>
 +
 +/* some parameters for the board */
 +
 +/*
 + *
 + * Taken from linux/arch/arm/boot/compressed/head-s3c2410.S
 + *
 + * Copyright (C) 2002 Samsung Electronics SW.LEE  <hitchcar@sec.samsung.com>
 + *
 + */
 +
 +#define BWSCON    0x48000000
 +
 +/* BWSCON */
 +#define DW8            (0x0)
 +#define DW16            (0x1)
 +#define DW32            (0x2)
 +#define WAIT            (0x1<<2)
 +#define UBLB            (0x1<<3)
 +
 +#define B1_BWSCON        (DW32)
 +#define B2_BWSCON        (DW16)
 +#define B3_BWSCON        (DW16 + WAIT + UBLB)
 +#define B4_BWSCON        (DW16)
 +#define B5_BWSCON        (DW16)
 +#define B6_BWSCON        (DW32)
 +#define B7_BWSCON        (DW32)
 +
 +/* BANK0CON */
 +#define B0_Tacs            0x0    /*  0clk */
 +#define B0_Tcos            0x0    /*  0clk */
 +#define B0_Tacc            0x7    /* 14clk */
 +#define B0_Tcoh            0x0    /*  0clk */
 +#define B0_Tah            0x0    /*  0clk */
 +#define B0_Tacp            0x0
 +#define B0_PMC            0x0    /* normal */
 +
 +/* BANK1CON */
 +#define B1_Tacs            0x0    /*  0clk */
 +#define B1_Tcos            0x0    /*  0clk */
 +#define B1_Tacc            0x7    /* 14clk */
 +#define B1_Tcoh            0x0    /*  0clk */
 +#define B1_Tah            0x0    /*  0clk */
 +#define B1_Tacp            0x0
 +#define B1_PMC            0x0
 +
 +#define B2_Tacs            0x0
 +#define B2_Tcos            0x0
 +#define B2_Tacc            0x7
 +#define B2_Tcoh            0x0
 +#define B2_Tah            0x0
 +#define B2_Tacp            0x0
 +#define B2_PMC            0x0
 +
 +#define B3_Tacs            0x0    /*  0clk */
 +#define B3_Tcos            0x3    /*  4clk */
 +#define B3_Tacc            0x7    /* 14clk */
 +#define B3_Tcoh            0x1    /*  1clk */
 +#define B3_Tah            0x0    /*  0clk */
 +#define B3_Tacp            0x3     /*  6clk */
 +#define B3_PMC            0x0    /* normal */
 +
 +#define B4_Tacs            0x0    /*  0clk */
 +#define B4_Tcos            0x0    /*  0clk */
 +#define B4_Tacc            0x7    /* 14clk */
 +#define B4_Tcoh            0x0    /*  0clk */
 +#define B4_Tah            0x0    /*  0clk */
 +#define B4_Tacp            0x0
 +#define B4_PMC            0x0    /* normal */
 +
 +#define B5_Tacs            0x0    /*  0clk */
 +#define B5_Tcos            0x0    /*  0clk */
 +#define B5_Tacc            0x7    /* 14clk */
 +#define B5_Tcoh            0x0    /*  0clk */
 +#define B5_Tah            0x0    /*  0clk */
 +#define B5_Tacp            0x0
 +#define B5_PMC            0x0    /* normal */
 +
 +#define B6_MT            0x3    /* SDRAM */
 +#define B6_Trcd            0x1
 +#define B6_SCAN            0x1    /* 9bit */
 +
 +#define B7_MT            0x3    /* SDRAM */
 +#define B7_Trcd            0x1    /* 3clk */
 +#define B7_SCAN            0x1    /* 9bit */
 +
 +/* REFRESH parameter */
 +#define REFEN            0x1    /* Refresh enable */
 +#define TREFMD            0x0    /* CBR(CAS before RAS)/Auto refresh */
 +#define Trp            0x0    /* 2clk */
 +#define Trc            0x3    /* 7clk */
 +#define Tchr            0x2    /* 3clk */
 +#define REFCNT            1113    /* period=15.6us, HCLK=60Mhz, (2048+1-15.6*60) */
 +/**************************************/
 +
 +.globl lowlevel_init
 +lowlevel_init:
 +    /* memory control configuration */
 +    /* make r0 relative the current location so that it */
 +    /* reads SMRDATA out of FLASH rather than memory ! */
 +    ldr     r0, =SMRDATA
 +    ldr    r1, =CONFIG_SYS_TEXT_BASE
 +    sub    r0, r0, r1
 +    ldr    r1, =BWSCON    /* Bus Width Status Controller */
 +    add     r2, r0, #*
 +:
 +    ldr     r3, [r0], #
 +    str     r3, [r1], #
 +    cmp     r2, r0
 +    bne     0b
 +
 +    /* everything is fine now */
 +    mov    pc, lr
 +
 +    .ltorg
 +/* the literal pools origin */
 +
 +SMRDATA:
 +    .long 0x22011110     //BWSCON
 +    .long 0x00000700     //BANKCON0
 +    .long 0x00000700     //BANKCON1
 +    .long 0x00000700     //BANKCON2
 +    .long 0x00000700     //BANKCON3
 +    .long 0x00000740     //BANKCON4
 +    .long 0x00000700     //BANKCON5
 +    .long 0x00018005     //BANKCON6
 +    .long 0x00018005     //BANKCON7
 +    .long 0x008C04F4     // REFRESH
 +    .long 0x000000B1     //BANKSIZE
 +    .long 0x00000030     //MRSRB6
 +    .long 0x00000030     //MRSRB7
 +
 diff -urN u-boot-2016.03/board/samsung/smdk2440/MAINTAINERS u-boot-.03ok/board/samsung/smdk2440/MAINTAINERS
 --- u-boot-2016.03/board/samsung/smdk2440/MAINTAINERS    -- ::00.000000000 +
 +++ u-boot-.03ok/board/samsung/smdk2440/MAINTAINERS    -- ::45.729857753 +
 @@ -, +, @@
 +SMDK2440 BOARD
 +M:    David M眉ller <d.mueller@elsoft.ch>
 +S:    Maintained
 +F:    board/samsung/smdk2440/
 +F:    include/configs/smdk2440.h
 +F:    configs/smdk2440_defconfig
 diff -urN u-boot-2016.03/board/samsung/smdk2440/Makefile u-boot-.03ok/board/samsung/smdk2440/Makefile
 --- u-boot-2016.03/board/samsung/smdk2440/Makefile    -- ::00.000000000 +
 +++ u-boot-.03ok/board/samsung/smdk2440/Makefile    -- ::45.849850303 +
 @@ -, +, @@
 +#
 +# (C) Copyright -
 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 +#
 +# SPDX-License-Identifier:    GPL-2.0+
 +#
 +
 +obj-y    := smdk2440.o
 +obj-y    += lowlevel_init.o
 diff -urN u-boot-2016.03/board/samsung/smdk2440/smdk2440.c u-boot-.03ok/board/samsung/smdk2440/smdk2440.c
 --- u-boot-2016.03/board/samsung/smdk2440/smdk2440.c    -- ::00.000000000 +
 +++ u-boot-.03ok/board/samsung/smdk2440/smdk2440.c    -- ::45.625917593 +
 @@ -, +, @@
 +/*
 + * (C) Copyright 2002
 + * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
 + * Marius Groeger <mgroeger@sysgo.de>
 + *
 + * (C) Copyright 2002, 2010
 + * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
 + *
 + * SPDX-License-Identifier:    GPL-2.0+
 + */
 +
 +#include <common.h>
 +#include <netdev.h>
 +#include <asm/io.h>
 +#include <asm/arch/s3c24x0_cpu.h>
 +
 +DECLARE_GLOBAL_DATA_PTR;
 +
 +#define FCLK_SPEED 1
 +
 +#if (FCLK_SPEED == 0)        /* Fout = 203MHz, Fin = 12MHz for Audio */
 +#define M_MDIV    0xC3
 +#define M_PDIV    0x4
 +#define M_SDIV    0x1
 +#elif (FCLK_SPEED == 1)        /* Fout = 202.8MHz */
 +#define M_MDIV    0xA1
 +#define M_PDIV    0x3
 +#define M_SDIV    0x1
 +#endif
 +
 +#define USB_CLOCK 1
 +
 +#if (USB_CLOCK == 0)
 +#define U_M_MDIV    0xA1
 +#define U_M_PDIV    0x3
 +#define U_M_SDIV    0x1
 +#elif (USB_CLOCK == 1)
 +#define U_M_MDIV    0x48
 +#define U_M_PDIV    0x3
 +#define U_M_SDIV    0x2
 +#endif
 +
 +static inline void pll_delay(unsigned long loops)
 +{
 +    __asm__ volatile ("1:\n"
 +      "subs %0, %1, #1\n"
 +      "bne 1b" : "=r" (loops) : "" (loops));
 +}
 +
 +/*
 + * Miscellaneous platform dependent initialisations
 + */
 +
 +int board_early_init_f(void)
 +{
 +    struct s3c24x0_clock_power * const clk_power =
 +                    s3c24x0_get_base_clock_power();
 +    struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
 +
 +    /* to reduce PLL lock time, adjust the LOCKTIME register */
 +    writel(0xFFFFFF, &clk_power->locktime);
 +
 +    /* configure MPLL */
 +    //writel((M_MDIV << 12) + (M_PDIV << 4) + M_SDIV, &clk_power->mpllcon);
 +
 +    /* some delay between MPLL and UPLL */
 +    //pll_delay(4000);
 +
 +    /* configure UPLL */
 +    writel((U_M_MDIV << ) + (U_M_PDIV << ) + U_M_SDIV,
 +           &clk_power->upllcon);
 +
 +    /* some delay between MPLL and UPLL */
 +    pll_delay();
 +
 +    /* set up the I/O ports */
 +    writel(0x007FFFFF, &gpio->gpacon);
 +    writel(0x00044555, &gpio->gpbcon);
 +    writel(0x000007FF, &gpio->gpbup);
 +    writel(0xAAAAAAAA, &gpio->gpccon);
 +    writel(0x0000FFFF, &gpio->gpcup);
 +    writel(0xAAAAAAAA, &gpio->gpdcon);
 +    writel(0x0000FFFF, &gpio->gpdup);
 +    writel(0xAAAAAAAA, &gpio->gpecon);
 +    writel(0x0000FFFF, &gpio->gpeup);
 +    writel(0x000055AA, &gpio->gpfcon);
 +    writel(0x000000FF, &gpio->gpfup);
 +    writel(0xFF95FFBA, &gpio->gpgcon);
 +    writel(0x0000FFFF, &gpio->gpgup);
 +    writel(0x002AFAAA, &gpio->gphcon);
 +    writel(0x000007FF, &gpio->gphup);
 +
 +    return ;
 +}
 +
 +int board_init(void)
 +{
 +    /* arch number of SMDK2410-Board */
 +    gd->bd->bi_arch_number = MACH_TYPE_SMDK2410;
 +
 +    /* adress of boot parameters */
 +    gd->bd->bi_boot_params = 0x30000100;
 +
 +    icache_enable();
 +    dcache_enable();
 +
 +    return ;
 +}
 +
 +int dram_init(void)
 +{
 +    /* dram_init must store complete ramsize in gd->ram_size */
 +    gd->ram_size = PHYS_SDRAM_1_SIZE;
 +    return ;
 +}
 +
 +#ifdef CONFIG_CMD_NET
 +int board_eth_init(bd_t *bis)
 +{
 +    int rc = ;
 +#ifdef CONFIG_CS8900
 +    rc = cs8900_initialize(, CONFIG_CS8900_BASE);
 +#endif
 +
 +#ifdef CONFIG_DRIVER_DM9000
 +    rc = dm9000_initialize(bis);
 +#endif
 +    return rc;
 +}
 +#endif
 +
 +/*
 + * Hardcoded flash setup:
 + * Flash 0 is a non-CFI AMD AM29LV800BB flash.
 + */
 +ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info)
 +{
 +    info->portwidth = FLASH_CFI_16BIT;
 +    info->chipwidth = FLASH_CFI_BY16;
 +    info->interface = FLASH_CFI_X16;
 +    return ;
 +}
 diff -urN u-boot-2016.03/cmd/nand.c u-boot-.03ok/cmd/nand.c
 --- u-boot-2016.03/cmd/nand.c    -- ::21.000000000 +
 +++ u-boot-.03ok/cmd/nand.c    -- ::47.371697445 +
 @@ -, +, @@
                          maxsize, (u_char *)addr,
                          WITH_DROP_FFS | WITH_WR_VERIFY);
  #endif
 +#ifdef CONFIG_CMD_NAND_YAFFS
 +        } else if (!strcmp(s, ".yaffs")) {
 +            if (read) {
 +                printf("Unknown nand command suffix '%s'.\n", s);
 +                return ;
 +            }
 +            ret = nand_write_skip_bad(nand, off, &rwsize, NULL,
 +                        maxsize, (u_char *)addr,
 +                        WITH_YAFFS_OOB);
 +#endif
 +
 +
          } else if (!strcmp(s, ".oob")) {
              /* out-of-band data */
              mtd_oob_ops_t ops = {
 diff -urN u-boot-2016.03/common/board_r.c u-boot-.03ok/common/board_r.c
 --- u-boot-2016.03/common/board_r.c    -- ::21.000000000 +
 +++ u-boot-.03ok/common/board_r.c    -- ::22.083443762 +
 @@ -, +, @@
      sandbox_main_loop_init();
  #endif
      /* main_loop() can return to retry autoboot, if so just run it again */
 +    run_command("mtdparts default", );
      for (;;)
          main_loop();
      return ;
 diff -urN u-boot-2016.03/configs/smdk2440_defconfig u-boot-.03ok/configs/smdk2440_defconfig
 --- u-boot-2016.03/configs/smdk2440_defconfig    -- ::00.000000000 +
 +++ u-boot-.03ok/configs/smdk2440_defconfig    -- ::48.822806092 +
 @@ -, +, @@
 +CONFIG_ARM=y
 +CONFIG_TARGET_SMDK2440=y
 +CONFIG_SYS_PROMPT="SMDK2440 # "
 +# CONFIG_CMD_SETEXPR is not set
 diff -urN u-boot-2016.03/drivers/mtd/cfi_flash.c u-boot-.03ok/drivers/mtd/cfi_flash.c
 --- u-boot-2016.03/drivers/mtd/cfi_flash.c    -- ::21.000000000 +
 +++ u-boot-.03ok/drivers/mtd/cfi_flash.c    -- ::45.155765043 +
 @@ -, +, @@
 
  /* The DEBUG define must be before common to enable debugging */
  /* #define DEBUG    */
 -
  #include <common.h>
  #include <console.h>
  #include <dm.h>
 diff -urN u-boot-2016.03/drivers/mtd/jedec_flash.c u-boot-.03ok/drivers/mtd/jedec_flash.c
 --- u-boot-2016.03/drivers/mtd/jedec_flash.c    -- ::21.000000000 +
 +++ u-boot-.03ok/drivers/mtd/jedec_flash.c    -- ::45.174882256 +
 @@ -, +, @@
          }
      },
  #endif
 +    {
 +        .mfr_id        = (u16)MX_MANUFACT,
 +        .dev_id        = AM29LV160DB,
 +        .name        = "MX 29LV160DB",
 +        .uaddr        = {
 +            [] = MTD_UADDR_0x0555_0x02AA /* x16 */
 +        },
 +        .DevSize    = SIZE_2MiB,
 +        .CmdSet        = CFI_CMDSET_AMD_LEGACY,
 +        .NumEraseRegions= ,
 +        .regions    = {
 +            ERASEINFO(*, ),
 +            ERASEINFO(*,  ),
 +            ERASEINFO(*, ),
 +            ERASEINFO(*, ),
 +        }
 +    },
 +
  };
 
  static inline void fill_info(flash_info_t *info, const struct amd_flash_info *jedec_entry, ulong base)
 diff -urN u-boot-2016.03/drivers/mtd/nand/Makefile u-boot-.03ok/drivers/mtd/nand/Makefile
 --- u-boot-2016.03/drivers/mtd/nand/Makefile    -- ::21.000000000 +
 +++ u-boot-.03ok/drivers/mtd/nand/Makefile    -- ::22.449544201 +
 @@ -, +, @@
  obj-$(CONFIG_NAND_NDFC) += ndfc.o
  obj-$(CONFIG_NAND_PXA3XX) += pxa3xx_nand.o
  obj-$(CONFIG_NAND_S3C2410) += s3c2410_nand.o
 +obj-$(CONFIG_NAND_S3C2440) += s3c2440_nand.o
  obj-$(CONFIG_NAND_SPEAR) += spr_nand.o
  obj-$(CONFIG_TEGRA_NAND) += tegra_nand.o
  obj-$(CONFIG_NAND_OMAP_GPMC) += omap_gpmc.o
 diff -urN u-boot-2016.03/drivers/mtd/nand/nand_util.c u-boot-.03ok/drivers/mtd/nand/nand_util.c
 --- u-boot-2016.03/drivers/mtd/nand/nand_util.c    -- ::21.000000000 +
 +++ u-boot-.03ok/drivers/mtd/nand/nand_util.c    -- ::19.582988542 +
 @@ -, +, @@
 
      if (actual)
          *actual = ;
 +#ifdef CONFIG_CMD_NAND_YAFFS
 +        if (flags & WITH_YAFFS_OOB) {
 +            if (flags & ~WITH_YAFFS_OOB)
 +                return -EINVAL;
 +
 +            int pages;
 +            pages = nand->erasesize / nand->writesize;
 +            blocksize = (pages * nand->oobsize) + nand->erasesize;
 +            if (*length % (nand->writesize + nand->oobsize)) {
 +                printf("Attempt to write incomplete page"
 +                    " in yaffs mode\n");
 +                return -EINVAL;
 +            }
 +        } else
 +#endif
 
      blocksize = nand->erasesize;
 
 @@ -, +, @@
              write_size = left_to_write;
          else
              write_size = blocksize - block_offset;
 +#ifdef CONFIG_CMD_NAND_YAFFS
 +        if (flags & WITH_YAFFS_OOB) {
 +            int page, pages;
 +            size_t pagesize = nand->writesize;
 +            size_t pagesize_oob = pagesize + nand->oobsize;
 +            struct mtd_oob_ops ops;
 +
 +            ops.len = pagesize;
 +            ops.ooblen = nand->oobsize;
 +            ops.mode = MTD_OPS_RAW;
 +            ops.ooboffs = ;
 +
 +            pages = write_size / pagesize_oob;
 +            for (page = ; page < pages; page++) {
 +                WATCHDOG_RESET();
 +
 +                ops.datbuf = p_buffer;
 +                ops.oobbuf = ops.datbuf + pagesize;
 +
 +                rval = mtd_write_oob(nand, offset, &ops);
 +                if (rval != )
 +                    break;
 +
 +                offset += pagesize;
 +                p_buffer += pagesize_oob;
 +            }
 +        }
 +        else
 +        {
 +#endif
 
          truncated_write_size = write_size;
  #ifdef CONFIG_CMD_NAND_TRIMFFS
 @@ -, +, @@
 
          offset += write_size;
          p_buffer += write_size;
 -
 +          }
 +
          if (rval != ) {
              printf("NAND write to offset %llx failed %d\n",
                  offset, rval);
 diff -urN u-boot-2016.03/drivers/mtd/nand/s3c2440_nand.c u-boot-.03ok/drivers/mtd/nand/s3c2440_nand.c
 --- u-boot-2016.03/drivers/mtd/nand/s3c2440_nand.c    -- ::00.000000000 +
 +++ u-boot-.03ok/drivers/mtd/nand/s3c2440_nand.c    -- ::21.900454122 +
 @@ -, +, @@
 +/*
 + * (C) Copyright 2006 OpenMoko, Inc.
 + * Author: Harald Welte <laforge@openmoko.org>
 + *
 + * SPDX-License-Identifier:    GPL-2.0+
 + */
 +
 +//#define DEBUG
 +#include <common.h>
 +
 +#include <nand.h>
 +#include <asm/arch/s3c24x0_cpu.h>
 +#include <asm/io.h>
 +
 +#define S3C2440_NFCONF_EN          (1<<15)
 +#define S3C2440_NFCONF_512BYTE     (1<<14)
 +#define S3C2440_NFCONF_4STEP       (1<<13)
 +#define S3C2440_NFCONF_INITECC     (1<<12)
 +#define S3C2440_NFCONF_nFCE        (1<<1)
 +#define S3C2440_NFCONF_TACLS(x)    ((x)<<12)
 +#define S3C2440_NFCONF_TWRPH0(x)   ((x)<<8)
 +#define S3C2440_NFCONF_TWRPH1(x)   ((x)<<4)
 +
 +#define S3C2440_ADDR_NALE 8
 +#define S3C2440_ADDR_NCLE 0xc
 +
 +#ifdef CONFIG_NAND_SPL
 +
 +/* in the early stage of NAND flash booting, printf() is not available */
 +#define printf(fmt, args...)
 +
 +static void nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
 +{
 +    int i;
 +    struct nand_chip *this = mtd->priv;
 +
 +    for (i = ; i < len; i++)
 +        buf[i] = readb(this->IO_ADDR_R);
 +}
 +#endif
 +
 +static void s3c24x0_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
 +{
 +    struct nand_chip *chip = mtd->priv;
 +    struct s3c24x0_nand *nand = s3c24x0_get_base_nand();
 +
 +    debug("hwcontrol(): 0x%02x 0x%02x\n", cmd, ctrl);
 +
 +    if (ctrl & NAND_CLE)
 +        nand->nfcmd = cmd;
 +    if (ctrl & NAND_ALE)
 +        nand->nfaddr = cmd;
 +
 +}
 +
 +static void s3c2440_nand_select(struct mtd_info *mtd, int chipnr)
 +{
 +    struct s3c24x0_nand *nand = s3c24x0_get_base_nand();
 +
 +    switch (chipnr) {
 +    case -: /* 取消选中 */
 +        nand->nfcont |= (<<);
 +        break;
 +    case :  /* 选中 */
 +        nand->nfcont &= ~(<<);
 +        break;
 +
 +    default:
 +        BUG();
 +    }
 +}
 +
 +
 +static int s3c24x0_dev_ready(struct mtd_info *mtd)
 +{
 +    struct s3c24x0_nand *nand = s3c24x0_get_base_nand();
 +    debug("dev_ready\n");
 +    return readl(&nand->nfstat) & 0x01;
 +}
 +
 +#ifdef CONFIG_S3C2440_NAND_HWECC
 +void s3c24x0_nand_enable_hwecc(struct mtd_info *mtd, int mode)
 +{
 +    struct s3c24x0_nand *nand = s3c24x0_get_base_nand();
 +    debug("s3c24x0_nand_enable_hwecc(%p, %d)\n", mtd, mode);
 +    writel(readl(&nand->nfconf) | S3C2440_NFCONF_INITECC, &nand->nfconf);
 +}
 +
 +static int s3c24x0_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
 +                      u_char *ecc_code)
 +{
 +    struct s3c24x0_nand *nand = s3c24x0_get_base_nand();
 +    ecc_code[] = readb(&nand->nfecc);
 +    ecc_code[] = readb(&nand->nfecc + );
 +    ecc_code[] = readb(&nand->nfecc + );
 +    debug("s3c24x0_nand_calculate_hwecc(%p,): 0x%02x 0x%02x 0x%02x\n",
 +          mtd , ecc_code[], ecc_code[], ecc_code[]);
 +
 +    return ;
 +}
 +
 +static int s3c24x0_nand_correct_data(struct mtd_info *mtd, u_char *dat,
 +                     u_char *read_ecc, u_char *calc_ecc)
 +{
 +    if (read_ecc[] == calc_ecc[] &&
 +        read_ecc[] == calc_ecc[] &&
 +        read_ecc[] == calc_ecc[])
 +        return ;
 +
 +    printf("s3c24x0_nand_correct_data: not implemented\n");
 +    return -;
 +}
 +#endif
 +
 +int board_nand_init(struct nand_chip *nand)
 +{
 +    u_int32_t cfg;
 +    u_int8_t tacls, twrph0, twrph1;
 +    struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power();
 +    struct s3c24x0_nand *nand_reg = s3c24x0_get_base_nand();
 +
 +    debug("board_nand_init()\n");
 +
 +    writel(readl(&clk_power->clkcon) | ( << ), &clk_power->clkcon);
 +
 +    /* initialize hardware */
 +#if defined(CONFIG_S3C24XX_CUSTOM_NAND_TIMING)
 +    tacls  = CONFIG_S3C24XX_TACLS;
 +    twrph0 = CONFIG_S3C24XX_TWRPH0;
 +    twrph1 =  CONFIG_S3C24XX_TWRPH1;
 +#else
 +    tacls = ;
 +    twrph0 = ;
 +    twrph1 = ;
 +#endif
 +    //cfg = S3C2440_NFCONF_EN;
 +    cfg = S3C2440_NFCONF_TACLS(tacls - );
 +    cfg |= S3C2440_NFCONF_TWRPH0(twrph0 - );
 +    cfg |= S3C2440_NFCONF_TWRPH1(twrph1 - );
 +    writel(cfg, &nand_reg->nfconf);
 +
 +    /* initialize nand_chip data structure */
 +    nand->IO_ADDR_R = (void *)&nand_reg->nfdata;
 +    nand->IO_ADDR_W = (void *)&nand_reg->nfdata;
 +
 +    /* read_buf and write_buf are default */
 +    /* read_byte and write_byte are default */
 +#ifdef CONFIG_NAND_SPL
 +    nand->read_buf = nand_read_buf;
 +#endif
 +
 +    /* hwcontrol always must be implemented */
 +    nand->cmd_ctrl = s3c24x0_hwcontrol;
 +
 +    nand->dev_ready = s3c24x0_dev_ready;
 +
 +#ifdef CONFIG_S3C2440_NAND_HWECC
 +    nand->ecc.hwctl = s3c24x0_nand_enable_hwecc;
 +    nand->ecc.calculate = s3c24x0_nand_calculate_ecc;
 +    nand->ecc.correct = s3c24x0_nand_correct_data;
 +    nand->ecc.mode = NAND_ECC_HW;
 +    nand->ecc.size = CONFIG_SYS_NAND_ECCSIZE;
 +    nand->ecc.bytes = CONFIG_SYS_NAND_ECCBYTES;
 +    nand->ecc.strength = ;
 +#else
 +    nand->ecc.mode = NAND_ECC_SOFT;
 +#endif
 +
 +#ifdef CONFIG_S3C2440_NAND_BBT
 +    nand->bbt_options |= NAND_BBT_USE_FLASH;
 +#endif
 +
 +    /* 4 ECC
 +     * 1 CE 先不选中，用的时候在选中
 +     * 0 启动 flash controller
 +     */
 +    writel(<< | << | , &nand_reg->nfcont);
 +    nand->select_chip = s3c2440_nand_select;
 +
 +
 +    debug("end of nand_init\n");
 +
 +    return ;
 +}
 +
 diff -urN u-boot-2016.03/include/configs/smdk2410.h u-boot-.03ok/include/configs/smdk2410.h
 --- u-boot-2016.03/include/configs/smdk2410.h    -- ::21.000000000 +
 +++ u-boot-.03ok/include/configs/smdk2410.h    -- ::46.907513241 +
 @@ -, +, @@
   * (easy to change)
   */
  #define CONFIG_S3C24X0        /* This is a SAMSUNG S3C24x0-type SoC */
 -#define CONFIG_S3C2410        /* specifically a SAMSUNG S3C2410 SoC */
 +#define CONFIG_S3C2440
  #define CONFIG_SMDK2410        /* on a SAMSUNG SMDK2410 Board */
 
 -#define CONFIG_SYS_TEXT_BASE    0x0
 +#define CONFIG_SYS_TEXT_BASE    0x33f00000
 
  #define CONFIG_SYS_ARM_CACHE_WRITETHROUGH
 @@ -, +, @@
  /************************************************************
   * USB support (currently only works with D-cache off)
   ************************************************************/
 -#define CONFIG_USB_OHCI
 -#define CONFIG_USB_OHCI_S3C24XX
 -#define CONFIG_USB_KEYBOARD
 -#define CONFIG_USB_STORAGE
 -#define CONFIG_DOS_PARTITION
 +/*#define CONFIG_USB_OHCI */
 +/*#define CONFIG_USB_OHCI_S3C24XX */
 +/*#define CONFIG_USB_KEYBOARD */
 +/*#define CONFIG_USB_STORAGE */
 +/*#define CONFIG_DOS_PARTITION */
 
  /************************************************************
   * RTC
   ************************************************************/
 -#define CONFIG_RTC_S3C24X0
 +/*#define CONFIG_RTC_S3C24X0*/
 
  #define CONFIG_BAUDRATE        115200
 @@ -, +, @@
  /*
   * BOOTP options
   */
 -#define CONFIG_BOOTP_BOOTFILESIZE
 -#define CONFIG_BOOTP_BOOTPATH
 -#define CONFIG_BOOTP_GATEWAY
 -#define CONFIG_BOOTP_HOSTNAME
 +/*#define CONFIG_BOOTP_BOOTFILESIZE*/
 +/*#define CONFIG_BOOTP_BOOTPATH*/
 +/*#define CONFIG_BOOTP_GATEWAY*/
 +/*#define CONFIG_BOOTP_HOSTNAME*/
 
  /*
   * Command line configuration.
   */
 -#define CONFIG_CMD_BSP
 +/*#define CONFIG_CMD_BSP*/
  #define CONFIG_CMD_CACHE
 -#define CONFIG_CMD_DATE
 -#define CONFIG_CMD_DHCP
 +/*#define CONFIG_CMD_DATE*/
 +/*#define CONFIG_CMD_DHCP*/
  #define CONFIG_CMD_NAND
  #define CONFIG_CMD_PING
 -#define CONFIG_CMD_REGINFO
 -#define CONFIG_CMD_USB
 +/*#define CONFIG_CMD_REGINFO*/
 +/*#define CONFIG_CMD_USB*/
 
  #define CONFIG_SYS_HUSH_PARSER
  #define CONFIG_CMDLINE_EDITING
 @@ -, +, @@
  #define CONFIG_ZERO_BOOTDELAY_CHECK
 
  #define CONFIG_NETMASK        255.255.255.0
 -#define CONFIG_IPADDR        10.0.0.110
 -#define CONFIG_SERVERIP        10.0.0.1
 +#define CONFIG_IPADDR        192.168.1.88
 +#define CONFIG_SERVERIP        192.168.1.1
 
  #if defined(CONFIG_CMD_KGDB)
  #define CONFIG_KGDB_BAUDRATE    115200    /* speed to run kgdb serial port */
 @@ -, +, @@
   * NAND configuration
   */
  #ifdef CONFIG_CMD_NAND
 -#define CONFIG_NAND_S3C2410
 -#define CONFIG_SYS_S3C2410_NAND_HWECC
  #define CONFIG_SYS_MAX_NAND_DEVICE    1
  #define CONFIG_SYS_NAND_BASE        0x4E000000
 +#define CONFIG_NAND_S3C2440
 +#define CONFIG_S3C24XX_CUSTOM_NAND_TIMING
 +#define CONFIG_S3C24XX_TACLS        1
 +#define CONFIG_S3C24XX_TWRPH0        2
 +#define CONFIG_S3C24XX_TWRPH1        1
  #endif
 
  /*
   * File system
   */
 -#define CONFIG_CMD_FAT
 -#define CONFIG_CMD_EXT2
 -#define CONFIG_CMD_UBI
 -#define CONFIG_CMD_UBIFS
 +/*#define CONFIG_CMD_FAT*/
 +/*#define CONFIG_CMD_EXT2*/
 +/*#define CONFIG_CMD_UBI*/
 +/*#define CONFIG_CMD_UBIFS*/
  #define CONFIG_CMD_MTDPARTS
  #define CONFIG_MTD_DEVICE
  #define CONFIG_MTD_PARTITIONS
  #define CONFIG_YAFFS2
 -#define CONFIG_RBTREE
 +/*#define CONFIG_RBTREE*/
 
  /* additions for new relocation code, must be added to all boards */
  #define CONFIG_SYS_SDRAM_BASE    PHYS_SDRAM_1
 diff -urN u-boot-2016.03/include/configs/smdk2440.h u-boot-.03ok/include/configs/smdk2440.h
 --- u-boot-2016.03/include/configs/smdk2440.h    -- ::00.000000000 +
 +++ u-boot-.03ok/include/configs/smdk2440.h    -- ::46.556075095 +
 @@ -, +, @@
 +/*
 + * (C) Copyright 2002
 + * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
 + * Marius Groeger <mgroeger@sysgo.de>
 + * Gary Jennejohn <garyj@denx.de>
 + * David Mueller <d.mueller@elsoft.ch>
 + *
 + * Configuation settings for the SAMSUNG SMDK2440 board.
 + *
 + * SPDX-License-Identifier:    GPL-2.0+
 + */
 +
 +#ifndef __CONFIG_H
 +#define __CONFIG_H
 +
 +/*
 + * High Level Configuration Options
 + * (easy to change)
 + */
 +#define CONFIG_S3C24X0        /* This is a SAMSUNG S3C24x0-type SoC */
 +#define CONFIG_S3C2440        /* specifically a SAMSUNG S3C2440 SoC */
 +#define CONFIG_SMDK2440        /* on a SAMSUNG SMDK2440 Board */
 +
 +#define CONFIG_SYS_TEXT_BASE    0x30a00000/*0x33f00000*/
 +
 +
 +#define CONFIG_SYS_ARM_CACHE_WRITETHROUGH
 +
 +/* input clock of PLL (the SMDK2440 has 12MHz input clock) */
 +#define CONFIG_SYS_CLK_FREQ    12000000
 +
 +#define CONFIG_CMDLINE_TAG    /* enable passing of ATAGs */
 +#define CONFIG_SETUP_MEMORY_TAGS
 +#define CONFIG_INITRD_TAG
 +
 +/* 放在NAND FLASH 中 大小 128K 开始地址  */
 +#define CONFIG_ENV_IS_IN_NAND
 +#define CONFIG_SYS_ENV_SECT_SIZE    (128 << 10)
 +#define CONFIG_ENV_OFFSET            (256<<10)
 +#define CONFIG_ENV_SIZE    CONFIG_SYS_ENV_SECT_SIZE
 +
 +
 +/* 添加兼容 yaffs2 烧写支持 */
 +#define CONFIG_CMD_NAND_YAFFS
 +#define CONFIG_CMD_MTDPARTS    /* Enable MTD parts commands */
 +#define CONFIG_MTD_DEVICE    /* needed for mtdparts commands */
 +#define MTDIDS_DEFAULT            "nand0=nand"
 +#define MTDPARTS_DEFAULT        "mtdparts=nand:256k(bootloader),"\
 +                                "128k(params),"\
 +                                "2m(kernel),-(root)"
 +
 +#define CONFIG_BOOTARGS "noinitrd root=/dev/mtdblock3 init=/linuxrc console=ttySAC0"
 +#define CONFIG_BOOTCOMMAND "nand read.jffs2 0x30007FC0 kernel; bootm 0x30007FC0"
 +
 +/*
 + * Hardware drivers
 + */
 +#define CONFIG_DRIVER_DM9000
 +#define CONFIG_DM9000_BASE 0x20000000
 +#define DM9000_IO        CONFIG_DM9000_BASE
 +#define DM9000_DATA        (CONFIG_DM9000_BASE+4)
 +#define CONFIG_NETMASK        255.255.255.0
 +#define CONFIG_IPADDR        192.168.1.123
 +#define CONFIG_SERVERIP        192.168.1.100
 +#define CONFIG_ETHADDR "00:50:56:C0:00:08"
 +
 +/*
 + * select serial console configuration
 + */
 +#define CONFIG_S3C24X0_SERIAL
 +#define CONFIG_SERIAL1        1    /* we use SERIAL 1 on SMDK2440 */
 +
 +
 +
 +#define CONFIG_BAUDRATE        115200
 +
 +
 +#define CONFIG_CMD_PING
 +
 +/* autoboot */
 +#define CONFIG_BOOTDELAY    5
 +#define CONFIG_BOOT_RETRY_TIME    -1
 +#define CONFIG_RESET_TO_RETRY
 +#define CONFIG_ZERO_BOOTDELAY_CHECK
 +
 +
 +#if defined(CONFIG_CMD_KGDB)
 +#define CONFIG_KGDB_BAUDRATE    115200    /* speed to run kgdb serial port */
 +#endif
 +
 +/*
 + * Miscellaneous configurable options
 + */
 +#define CONFIG_SYS_LONGHELP        /* undef to save memory */
 +#define CONFIG_SYS_CBSIZE    256
 +/* Print Buffer Size */
 +#define CONFIG_SYS_PBSIZE    (CONFIG_SYS_CBSIZE + \
 +                sizeof(CONFIG_SYS_PROMPT)+)
 +#define CONFIG_SYS_MAXARGS    16
 +#define CONFIG_SYS_BARGSIZE    CONFIG_SYS_CBSIZE
 +
 +#define CONFIG_DISPLAY_CPUINFO                /* Display cpu info */
 +
 +#define CONFIG_SYS_MEMTEST_START    0x30000000    /* memtest works on */
 +#define CONFIG_SYS_MEMTEST_END        0x33F00000    /* 63 MB in DRAM */
 +
 +#define CONFIG_SYS_LOAD_ADDR        0x30800000
 +
 +/* support additional compression methods */
 +#define CONFIG_BZIP2
 +#define CONFIG_LZO
 +#define CONFIG_LZMA
 +
 +/*-----------------------------------------------------------------------
 + * Physical Memory Map
 + */
 +#define CONFIG_NR_DRAM_BANKS    1          /* we have 1 bank of DRAM */
 +#define PHYS_SDRAM_1        0x30000000 /* SDRAM Bank #1 */
 +#define PHYS_SDRAM_1_SIZE    0x04000000 /* 64 MB */
 +
 +#define PHYS_FLASH_1        0x00000000 /* Flash Bank #0 */
 +
 +#define CONFIG_SYS_FLASH_BASE    PHYS_FLASH_1
 +
 +/*-----------------------------------------------------------------------
 + * FLASH and environment organization
 + */
 +
 +#define CONFIG_SYS_FLASH_CFI
 +#define CONFIG_FLASH_CFI_DRIVER
 +#define CONFIG_FLASH_CFI_LEGACY
 +#define CONFIG_SYS_FLASH_LEGACY_512Kx16
 +#define CONFIG_FLASH_SHOW_PROGRESS    45
 +
 +#define CONFIG_SYS_MAX_FLASH_BANKS    1
 +#define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_FLASH_BASE }
 +#define CONFIG_SYS_MAX_FLASH_SECT    (35)
 +
 +
 +/*
 + * Size of malloc() pool
 + * BZIP2 / LZO / LZMA need a lot of RAM
 + */
 +#define CONFIG_SYS_MALLOC_LEN    (4 * 1024 * 1024)
 +
 +#define CONFIG_SYS_MONITOR_LEN    (448 * 1024)
 +#define CONFIG_SYS_MONITOR_BASE    CONFIG_SYS_FLASH_BASE
 +
 +#define CONFIG_CMD_NAND
 +/*
 + * NAND configuration
 + */
 +#ifdef CONFIG_CMD_NAND
 +#define CONFIG_NAND_S3C2440
 +#define CONFIG_SYS_MAX_NAND_DEVICE    1
 +#define CONFIG_SYS_NAND_BASE        0x4E000000
 +#define CONFIG_S3C24XX_CUSTOM_NAND_TIMING
 +#define CONFIG_S3C24XX_TACLS  1
 +#define CONFIG_S3C24XX_TWRPH0 2
 +#define CONFIG_S3C24XX_TWRPH1 1
 +
 +#endif
 +
 +/* additions for new relocation code, must be added to all boards */
 +#define CONFIG_SYS_SDRAM_BASE    PHYS_SDRAM_1
 +#define CONFIG_SYS_INIT_SP_ADDR    (CONFIG_SYS_SDRAM_BASE + 0x1000 - \
 +                GENERATED_GBL_DATA_SIZE)
 +
 +#define CONFIG_BOARD_EARLY_INIT_F
 +
 +#endif /* __CONFIG_H */
 diff -urN u-boot-2016.03/include/env_default.h u-boot-.03ok/include/env_default.h
 --- u-boot-2016.03/include/env_default.h    -- ::21.000000000 +
 +++ u-boot-.03ok/include/env_default.h    -- ::50.860466037 +
 @@ -, +, @@
  #else
  const uchar default_environment[] = {
  #endif
 +#ifdef    CONFIG_ETHADDR
 +    "ethaddr=" CONFIG_ETHADDR "\0"
 +#endif
 +
  #ifdef    CONFIG_ENV_CALLBACK_LIST_DEFAULT
      ENV_CALLBACK_VAR "=" CONFIG_ENV_CALLBACK_LIST_DEFAULT "\0"
  #endif
 diff -urN u-boot-2016.03/include/nand.h u-boot-.03ok/include/nand.h
 --- u-boot-2016.03/include/nand.h    -- ::21.000000000 +
 +++ u-boot-.03ok/include/nand.h    -- ::57.399450808 +
 @@ -, +, @@
  int nand_read_skip_bad(nand_info_t *nand, loff_t offset, size_t *length,
                 size_t *actual, loff_t lim, u_char *buffer);
 
 +#define WITH_YAFFS_OOB    (1 << 0) /* whether write with yaffs format. This flag                  * is a 'mode' meaning it cannot be mixed with                  * other flags */
 +
  #define WITH_DROP_FFS    (1 << 0) /* drop trailing all-0xff pages */
  #define WITH_WR_VERIFY    (1 << 1) /* verify data was written correctly */
 
 diff -urN u-boot-2016.03/Makefile u-boot-.03ok/Makefile
 --- u-boot-2016.03/Makefile    -- ::21.000000000 +
 +++ u-boot-.03ok/Makefile    -- ::00.046292963 +
 @@ -, +, @@
  SUBLEVEL =
  EXTRAVERSION =
  NAME =
 -
 +ARCH=arm
 +CROSS_COMPILE=arm-linux-
  # *DOCUMENTATION*
  # To see a list of typical targets execute "make help"
  # More info can be located in ./README
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