将ADS1.2的工程迁移到KEIL上-基于2440

新版的MDK支持2440相关芯片,但是很多人的工程都是基于ADS1.2开发,文字不好看,兼容性不好等等问题,而且电脑上装太多开发工具切换起来也麻烦,所以切换到MDK开发2440裸机程序应该是一个很好的选择

1.       新建MDK工程,芯片选择2440

不拷贝启动代码,因为我们用自己的启动代码

2.       建立工程目录分级,建立完成后如下所示

拷贝相应代码到对应目录中

Option中拷贝

Core中拷贝

建立新的main文件

将文件加入工程

路径中建立包含

还要为asm文件建立包含

修改2440init.s文件

首先,MDK默认放在最前面的段是RESET段,将2440init.s第84行(可能你的不是)
AREA    Init,CODE,READONLY修改为 AREA    RESET,CODE,READONLY

这样编译器就能找到入口点了

在上面这句下面加上一行

PRESERVE8    ;8 字对齐(为了让汇编代码8字节对齐)

修改

IMPORT  |Image$$RO$$Base| ; Base of ROM code

IMPORT  |Image$$RO$$Limit|  ; End of ROM code (=start of ROM data)

IMPORT  |Image$$RW$$Base|   ; Base of RAM to initialise

IMPORT  |Image$$ZI$$Base|   ; Base and limit of area

IMPORT  |Image$$ZI$$Limit|  ; to zero initialise

这些是通过ADS的工程设置里面设定的RO Base和RW Base设定的,在MDK中的名称不叫这个

修改为

IMPORT  |Image$$ER_ROM1$$RO$$Base|   ; Base of ROM code

IMPORT  |Image$$ER_ROM1$$RO$$Limit|  ; End of ROM code (=start of ROM data)

IMPORT  |Image$$RW_RAM1$$RW$$Base|   ; Base of RAM to initialise

IMPORT  |Image$$RW_RAM1$$ZI$$Base|   ; Base and limit of area

IMPORT  |Image$$RW_RAM1$$ZI$$Limit|  ; to zero initialize

上面的改了下面的这个也要改

BaseOfROM DCD |Image$$RO$$Base|

TopOfROM DCD |Image$$RO$$Limit|

BaseOfBSS DCD |Image$$RW$$Base|

BaseOfZero DCD |Image$$ZI$$Base|

EndOfBSS DCD |Image$$ZI$$Limit|

修改为

BaseOfROM  DCD  |Image$$ER_ROM1$$RO$$Base|

TopOfROM  DCD  |Image$$ER_ROM1$$RO$$Limit|

BaseOfBSS  DCD  |Image$$RW_RAM1$$RW$$Base|

BaseOfZero  DCD  |Image$$RW_RAM1$$ZI$$Base|

EndOfBSS  DCD  |Image$$RW_RAM1$$ZI$$Limit|

此时还需要设置代码运行区和存放区

ROM区域需要打开nand.c中的RdNF2SDRAM函数查看起始地址

我的起始地址为0x30000000
大小为0x100000

Size必须大于0x100000,RAM空间大于ROM空间且少于最大物理空间即可(不要忘了打钩勾)

编写Main函数,记住是首字母大写

此时编译就可以通过了

随意将一个ADS1.2编写好的led驱动放进去,最终修改如下

Led.h

#ifndef __LED_H
#define __LED_H
#include "2440addr.h"

typedef enum
{
	LED1 = 0,	//GPB5
	LED2 = 1,	//GPB6
	LED3 = 2,	//GPB5
	LED4 = 3	//GPB8
}LEDn;

void ledInit(LEDn led);
void ledInitAll(void);
void ledOn(LEDn led);
void ledOff(LEDn led);
void ledTurn(LEDn led);
unsigned char getLedStatus(LEDn led);

//TQ2440led引脚 B5 B6 B7 B8

#endif

Led.c

#include "led.h"

void ledInit(LEDn led)
{
	if(led == LED1)
	{
		rGPBCON &= ~(3<<10);	//端口写入01设置为输出模式，先清零
		rGPBCON |= (1<<10);		//设置为输出
		rGPBUP &= ~(1<<5);		//禁止上拉
		rGPBDAT |= (1<<5);		//设置初始值为1，灯灭
	}
	else if(led == LED2)
	{
		rGPBCON &= ~(3<<12);
		rGPBCON |= (1<<12);
		rGPBUP &= ~(1<<6);
		rGPBDAT |= (1<<6);
	}
	else if(led == LED3)
	{
		rGPBCON &= ~(3<<14);
		rGPBCON |= (1<<14);
		rGPBUP &= ~(1<<7);
		rGPBDAT |= (1<<7);
	}
	else if(led == LED4)
	{
		rGPBCON &= ~(3<<16);
		rGPBCON |= (1<<16);
		rGPBUP &= ~(1<<8);
		rGPBDAT |= (1<<8);
	}
}

void ledInitAll(void)
{
	rGPBCON &=~((3<<10)|(3<<12)|(3<<14)|(3<<16));	//对GPBCON[10:17]清零
	rGPBCON |=((1<<10)|(1<<12)|(1<<14)|(1<<16));	//设置GPB5~8为输出
	rGPBUP &=~((1<<5)|(1<<6)|(1<<7)|(1<<8));		//设置GPB5~8的上拉功能
	rGPBDAT |=(1<<5)|(1<<6)|(1<<7)|(1<<8);			//关闭LED
}

void ledOn(LEDn led)
{
	rGPBDAT &= ~(1<<(5+led));
}

void ledOff(LEDn led)
{
	rGPBDAT |= (1<<(5+led));
}

void ledTurn(LEDn led)
{
	if(getLedStatus(led))ledOn(led);
	else ledOff(led);
}

unsigned char getLedStatus(LEDn led)//获取led状态，灭为1亮为0
{
	if((rGPBDAT & (1<<(5+led))))return 1;
	else return 0;
}

Main.c

#include "2440addr.h"
#include "led.h"
void Delay(void)
{
	int i;
	for(i=0;i<1000000;i++);
}

int Main()
{
	ledInitAll();
	while(1)
	{
		ledTurn(LED1);
		Delay();
		ledTurn(LED2);
		Delay();
		ledTurn(LED3);
		Delay();
		ledTurn(LED4);
		Delay();
	}
}

最后编译,结果如下

但是生成的是HEX,我们需要指令转换成BIN文件

在这里写入指令

记住对勾!

编译,提示如下

BIN文件生成OK了

下载进去,流水灯完全正常,收工!

最后附带修改好了2440init.s文件

2440init.s

;=========================================
; NAME: 2440INIT.S
; DESC: C start up codes
;       Configure memory, ISR ,stacks
;	Initialize C-variables
;=========================================

	GET option.inc
	GET memcfg.inc
	GET 2440addr.inc

BIT_SELFREFRESH EQU	(1<<22)

;Pre-defined constants
USERMODE    EQU 	0x10
FIQMODE     EQU 	0x11
IRQMODE     EQU 	0x12
SVCMODE     EQU 	0x13
ABORTMODE   EQU 	0x17
UNDEFMODE   EQU 	0x1b
MODEMASK    EQU 	0x1f
NOINT       EQU 	0xc0

;The location of stacks
UserStack	EQU	(_STACK_BASEADDRESS-0x3800)	;0x33ff4800 ~
SVCStack	EQU	(_STACK_BASEADDRESS-0x2800)	;0x33ff5800 ~
UndefStack	EQU	(_STACK_BASEADDRESS-0x2400)	;0x33ff5c00 ~
AbortStack	EQU	(_STACK_BASEADDRESS-0x2000)	;0x33ff6000 ~
IRQStack	EQU	(_STACK_BASEADDRESS-0x1000)	;0x33ff7000 ~
FIQStack	EQU	(_STACK_BASEADDRESS-0x0)	;0x33ff8000 ~

;Check if tasm.exe(armasm -16 ...@ADS 1.0) is used.
	GBLL    THUMBCODE
	[ {CONFIG} = 16
THUMBCODE SETL  {TRUE}
	    CODE32
 		|
THUMBCODE SETL  {FALSE}
    ]

 		MACRO
	MOV_PC_LR
 		[ THUMBCODE
	    bx lr
 		|
	    mov	pc,lr
 		]
	MEND

 		MACRO
	MOVEQ_PC_LR
 		[ THUMBCODE
        bxeq lr
 		|
	    moveq pc,lr
 		]
	MEND

 		MACRO
$HandlerLabel HANDLER $HandleLabel

$HandlerLabel
	sub	sp,sp,#4	;decrement sp(to store jump address)
	stmfd	sp!,{r0}	;PUSH the work register to stack(lr does not push because it return to original address)
	ldr     r0,=$HandleLabel;load the address of HandleXXX to r0
	ldr     r0,[r0]	 ;load the contents(service routine start address) of HandleXXX
	str     r0,[sp,#4]      ;store the contents(ISR) of HandleXXX to stack
	ldmfd   sp!,{r0,pc}     ;POP the work register and pc(jump to ISR)
	MEND

	IMPORT  |Image$$ER_ROM1$$RO$$Base|   ; Base of ROM code
	IMPORT  |Image$$ER_ROM1$$RO$$Limit|  ; End of ROM code (=start of ROM data)
	IMPORT  |Image$$RW_RAM1$$RW$$Base|   ; Base of RAM to initialise
	IMPORT  |Image$$RW_RAM1$$ZI$$Base|   ; Base and limit of area
	IMPORT  |Image$$RW_RAM1$$ZI$$Limit|  ; to zero initialise 

	IMPORT	MMU_SetAsyncBusMode
	IMPORT	MMU_SetFastBusMode	;

	IMPORT  Main		; The main entry of mon program
	IMPORT  RdNF2SDRAM	; Copy Image from Nand Flash to SDRAM

	AREA    RESET,CODE,READONLY
	PRESERVE8    ;8 字对齐 

	ENTRY

	EXPORT	__ENTRY
__ENTRY
ResetEntry
	;1)The code, which converts to Big-endian, should be in little endian code.
	;2)The following little endian code will be compiled in Big-Endian mode.
	;  The code byte order should be changed as the memory bus width.
	;3)The pseudo instruction,DCD can not be used here because the linker generates error.
	ASSERT	:DEF:ENDIAN_CHANGE
	[ ENDIAN_CHANGE
		ASSERT  :DEF:ENTRY_BUS_WIDTH
		[ ENTRY_BUS_WIDTH=32
			b	ChangeBigEndian	    ;DCD 0xea000007
		]

		[ ENTRY_BUS_WIDTH=16
			andeq	r14,r7,r0,lsl #20   ;DCD 0x0007ea00
		]

		[ ENTRY_BUS_WIDTH=8
			streq	r0,[r0,-r10,ror #1] ;DCD 0x070000ea
		]
		|
		b	ResetHandler
	]
	b	HandlerUndef	;handler for Undefined mode
	b	HandlerSWI	;handler for SWI interrupt
	b	HandlerPabort	;handler for PAbort
	b	HandlerDabort	;handler for DAbort
	b	.		;reserved
	b	HandlerIRQ	;handler for IRQ interrupt
	b	HandlerFIQ	;handler for FIQ interrupt

;@0x20
	b	EnterPWDN	; Must be @0x20.
ChangeBigEndian
;@0x24
	[ ENTRY_BUS_WIDTH=32
		DCD	0xee110f10	;0xee110f10 => mrc p15,0,r0,c1,c0,0
		DCD	0xe3800080	;0xe3800080 => orr r0,r0,#0x80;  //Big-endian
		DCD	0xee010f10	;0xee010f10 => mcr p15,0,r0,c1,c0,0
	]
	[ ENTRY_BUS_WIDTH=16
		DCD 0x0f10ee11
		DCD 0x0080e380
		DCD 0x0f10ee01
	]
	[ ENTRY_BUS_WIDTH=8
		DCD 0x100f11ee
		DCD 0x800080e3
		DCD 0x100f01ee
	]
	DCD 0xffffffff  ;swinv 0xffffff is similar with NOP and run well in both endian mode.
	DCD 0xffffffff
	DCD 0xffffffff
	DCD 0xffffffff
	DCD 0xffffffff
	b ResetHandler

HandlerFIQ	HANDLER HandleFIQ
HandlerIRQ	HANDLER HandleIRQ
HandlerUndef	HANDLER HandleUndef
HandlerSWI	HANDLER HandleSWI
HandlerDabort	HANDLER HandleDabort
HandlerPabort	HANDLER HandlePabort

IsrIRQ
	sub	sp,sp,#4       ;reserved for PC
	stmfd	sp!,{r8-r9}

	ldr	r9,=INTOFFSET
	ldr	r9,[r9]
	ldr	r8,=HandleEINT0
	add	r8,r8,r9,lsl #2
	ldr	r8,[r8]
	str	r8,[sp,#8]
	ldmfd	sp!,{r8-r9,pc}

	LTORG

;=======
; ENTRY
;=======
ResetHandler
	ldr	r0,=WTCON       ;watch dog disable
	ldr	r1,=0x0
	str	r1,[r0]

	ldr	r0,=INTMSK
	ldr	r1,=0xffffffff  ;all interrupt disable
	str	r1,[r0]

	ldr	r0,=INTSUBMSK
	ldr	r1,=0x7fff		;all sub interrupt disable
	str	r1,[r0]

	[ {FALSE}
		; GPBDAT = (rGPFDAT & ~(0xf<<4)) | ((~data & 0xf)<<4);
		; Led_Display
		ldr	r0,=GPBCON
		ldr	r1,=0x00555555
		str	r1,[r0]
		ldr	r0,=GPBDAT
		ldr	r1,=0x07fe
		str	r1,[r0]
	]

	;To reduce PLL lock time, adjust the LOCKTIME register.
	ldr	r0,=LOCKTIME
	ldr	r1,=0xffffff
	str	r1,[r0]

	[ PLL_ON_START
		; Added for confirm clock divide. for 2440.
		; Setting value Fclk:Hclk:Pclk
		ldr	r0,=CLKDIVN
		ldr	r1,=CLKDIV_VAL		; 0=1:1:1, 1=1:1:2, 2=1:2:2, 3=1:2:4, 4=1:4:4, 5=1:4:8, 6=1:3:3, 7=1:3:6.
		str	r1,[r0]

	;program has not been copied, so use these directly
		[ CLKDIV_VAL>1 		; means Fclk:Hclk is not 1:1.
			mrc p15,0,r0,c1,c0,0
			orr r0,r0,#0xc0000000;R1_nF:OR:R1_iA
			mcr p15,0,r0,c1,c0,0
			|
			mrc p15,0,r0,c1,c0,0
			bic r0,r0,#0xc0000000;R1_iA:OR:R1_nF
			mcr p15,0,r0,c1,c0,0
		]

		;Configure UPLL
		ldr	r0,=UPLLCON
		ldr	r1,=((U_MDIV<<12)+(U_PDIV<<4)+U_SDIV)				;Fin = 12.0MHz, UCLK = 48MHz
		str	r1,[r0]
		nop	; Caution: After UPLL setting, at least 7-clocks delay must be inserted for setting hardware be completed.
		nop
		nop
		nop
		nop
		nop
		nop
		;Configure MPLL
		ldr	r0,=MPLLCON
		ldr	r1,=((M_MDIV<<12)+(M_PDIV<<4)+M_SDIV)				;Fin = 12.0MHz, FCLK = 400MHz
		str	r1,[r0]
	]

	;Check if the boot is caused by the wake-up from SLEEP mode.
	ldr	r1,=GSTATUS2
	ldr	r0,[r1]
	tst	r0,#0x2
	;In case of the wake-up from SLEEP mode, go to SLEEP_WAKEUP handler.
	bne	WAKEUP_SLEEP

	EXPORT StartPointAfterSleepWakeUp
StartPointAfterSleepWakeUp

	;Set memory control registers
 	adrl	r0,SMRDATA
	ldr	r1,=BWSCON	;BWSCON Address
	add	r2, r0, #52	;End address of SMRDATA

0
	ldr	r3, [r0], #4
	str	r3, [r1], #4
	cmp	r2, r0
	bne	%B0

;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;;;;;;;;;;;;       When EINT0 is pressed,  Clear SDRAM
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; check if EIN0 button is pressed

	ldr	r0,=GPFCON
	ldr	r1,=0x0
	str	r1,[r0]
	ldr	r0,=GPFUP
	ldr	r1,=0xff
	str	r1,[r0]

	ldr	r1,=GPFDAT
	ldr	r0,[r1]
	bic	r0,r0,#(0x1e<<1)  ; bit clear
	tst	r0,#0x1
	bne %F1

; Clear SDRAM Start

	ldr	r0,=GPFCON
	ldr	r1,=0x55aa
	str	r1,[r0]
	ldr	r0,=GPFDAT
	ldr	r1,=0x0
	str	r1,[r0]	;LED=****

	mov r1,#0
	mov r2,#0
	mov r3,#0
	mov r4,#0
	mov r5,#0
	mov r6,#0
	mov r7,#0
	mov r8,#0

	ldr	r9,=0x4000000   ;64MB
	ldr	r0,=0x30000000
0
	stmia	r0!,{r1-r8}
	subs	r9,r9,#32
	bne	%B0

;Clear SDRAM End

1

	;Initialize stacks
	bl	InitStacks

;===========================================================

	ldr	r0, =BWSCON
	ldr	r0, [r0]
	ands	r0, r0, #6		;OM[1:0] != 0, NOR FLash boot
	bne	copy_proc_beg		;do not read nand flash
	adr	r0, ResetEntry		;OM[1:0] == 0, NAND FLash boot
	cmp	r0, #0			;if use Multi-ice,
	bne	copy_proc_beg		;do not read nand flash for boot
	;nop
;===========================================================
nand_boot_beg
	[ {TRUE}
		bl RdNF2SDRAM
	]

	ldr	pc, =copy_proc_beg
;===========================================================
copy_proc_beg
	adr	r0, ResetEntry
	ldr	r2, BaseOfROM
	cmp	r0, r2
	ldreq	r0, TopOfROM
	beq	InitRam
	ldr r3, TopOfROM
0
	ldmia	r0!, {r4-r7}
	stmia	r2!, {r4-r7}
	cmp	r2, r3
	bcc	%B0

	sub	r2, r2, r3
	sub	r0, r0, r2				

InitRam
	ldr	r2, BaseOfBSS
	ldr	r3, BaseOfZero
0
	cmp	r2, r3
	ldrcc	r1, [r0], #4
	strcc	r1, [r2], #4
	bcc	%B0	

	mov	r0,	#0
	ldr	r3,	EndOfBSS
1
	cmp	r2,	r3
	strcc	r0, [r2], #4
	bcc	%B1

	ldr	pc, =%F2		;goto compiler address
2

;	[ CLKDIV_VAL>1 		; means Fclk:Hclk is not 1:1.
;	bl	MMU_SetAsyncBusMode
;	|
;	bl MMU_SetFastBusMode	; default value.
;	]

;===========================================================
  	; Setup IRQ handler
	ldr	r0,=HandleIRQ	;This routine is needed
	ldr	r1,=IsrIRQ	;if there is not 'subs pc,lr,#4' at 0x18, 0x1c
	str	r1,[r0]

    [ :LNOT:THUMBCODE
 		bl	Main	;Do not use main() because ......
 		b	.
    ]

    [ THUMBCODE	 ;for start-up code for Thumb mode
 		orr	lr,pc,#1
 		bx	lr
 		CODE16
 		bl	Main	;Do not use main() because ......
 		b	.
		CODE32
    ]

;function initializing stacks
InitStacks
	;Do not use DRAM,such as stmfd,ldmfd......
	;SVCstack is initialized before
	;Under toolkit ver 2.5, 'msr cpsr,r1' can be used instead of 'msr cpsr_cxsf,r1'
	mrs	r0,cpsr
	bic	r0,r0,#MODEMASK
	orr	r1,r0,#UNDEFMODE:OR:NOINT
	msr	cpsr_cxsf,r1		;UndefMode
	ldr	sp,=UndefStack		; UndefStack=0x33FF_5C00

	orr	r1,r0,#ABORTMODE:OR:NOINT
	msr	cpsr_cxsf,r1		;AbortMode
	ldr	sp,=AbortStack		; AbortStack=0x33FF_6000

	orr	r1,r0,#IRQMODE:OR:NOINT
	msr	cpsr_cxsf,r1		;IRQMode
	ldr	sp,=IRQStack		; IRQStack=0x33FF_7000

	orr	r1,r0,#FIQMODE:OR:NOINT
	msr	cpsr_cxsf,r1		;FIQMode
	ldr	sp,=FIQStack		; FIQStack=0x33FF_8000

	bic	r0,r0,#MODEMASK:OR:NOINT
	orr	r1,r0,#SVCMODE
	msr	cpsr_cxsf,r1		;SVCMode
	ldr	sp,=SVCStack		; SVCStack=0x33FF_5800

	;USER mode has not be initialized.

	mov	pc,lr
	;The LR register will not be valid if the current mode is not SVC mode.

	LTORG

SMRDATA DATA
; Memory configuration should be optimized for best performance
; The following parameter is not optimized.
; Memory access cycle parameter strategy
; 1) The memory settings is  safe parameters even at HCLK=75Mhz.
; 2) SDRAM refresh period is for HCLK<=75Mhz.

	DCD (0+(B1_BWSCON<<4)+(B2_BWSCON<<8)+(B3_BWSCON<<12)+(B4_BWSCON<<16)+(B5_BWSCON<<20)+(B6_BWSCON<<24)+(B7_BWSCON<<28))
	DCD ((B0_Tacs<<13)+(B0_Tcos<<11)+(B0_Tacc<<8)+(B0_Tcoh<<6)+(B0_Tah<<4)+(B0_Tacp<<2)+(B0_PMC))   ;GCS0
	DCD ((B1_Tacs<<13)+(B1_Tcos<<11)+(B1_Tacc<<8)+(B1_Tcoh<<6)+(B1_Tah<<4)+(B1_Tacp<<2)+(B1_PMC))   ;GCS1
	DCD ((B2_Tacs<<13)+(B2_Tcos<<11)+(B2_Tacc<<8)+(B2_Tcoh<<6)+(B2_Tah<<4)+(B2_Tacp<<2)+(B2_PMC))   ;GCS2
	DCD ((B3_Tacs<<13)+(B3_Tcos<<11)+(B3_Tacc<<8)+(B3_Tcoh<<6)+(B3_Tah<<4)+(B3_Tacp<<2)+(B3_PMC))   ;GCS3
	DCD ((B4_Tacs<<13)+(B4_Tcos<<11)+(B4_Tacc<<8)+(B4_Tcoh<<6)+(B4_Tah<<4)+(B4_Tacp<<2)+(B4_PMC))   ;GCS4
	DCD ((B5_Tacs<<13)+(B5_Tcos<<11)+(B5_Tacc<<8)+(B5_Tcoh<<6)+(B5_Tah<<4)+(B5_Tacp<<2)+(B5_PMC))   ;GCS5
	DCD ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN))    ;GCS6
	DCD ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN))    ;GCS7
	DCD ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Tsrc<<18)+(Tchr<<16)+REFCNT)

	DCD 0x32	    ;SCLK power saving mode, BANKSIZE 128M/128M

	DCD 0x30	    ;MRSR6 CL=3clk
	DCD 0x30	    ;MRSR7 CL=3clk

BaseOfROM  DCD  |Image$$ER_ROM1$$RO$$Base|
TopOfROM  DCD  |Image$$ER_ROM1$$RO$$Limit|
BaseOfBSS  DCD  |Image$$RW_RAM1$$RW$$Base|
BaseOfZero  DCD  |Image$$RW_RAM1$$ZI$$Base|
EndOfBSS  DCD  |Image$$RW_RAM1$$ZI$$Limit| 

	ALIGN

;Function for entering power down mode
; 1. SDRAM should be in self-refresh mode.
; 2. All interrupt should be maksked for SDRAM/DRAM self-refresh.
; 3. LCD controller should be disabled for SDRAM/DRAM self-refresh.
; 4. The I-cache may have to be turned on.
; 5. The location of the following code may have not to be changed.

;void EnterPWDN(int CLKCON);
EnterPWDN
	mov r2,r0		;r2=rCLKCON
	tst r0,#0x8		;SLEEP mode?
	bne ENTER_SLEEP

ENTER_STOP
	ldr r0,=REFRESH
	ldr r3,[r0]		;r3=rREFRESH
	mov r1, r3
	orr r1, r1, #BIT_SELFREFRESH
	str r1, [r0]		;Enable SDRAM self-refresh

	mov r1,#16			;wait until self-refresh is issued. may not be needed.
0	subs r1,r1,#1
	bne %B0

	ldr r0,=CLKCON		;enter STOP mode.
	str r2,[r0]

	mov r1,#32
0	subs r1,r1,#1	;1) wait until the STOP mode is in effect.
	bne %B0		;2) Or wait here until the CPU&Peripherals will be turned-off
			;   Entering SLEEP mode, only the reset by wake-up is available.

	ldr r0,=REFRESH ;exit from SDRAM self refresh mode.
	str r3,[r0]

	MOV_PC_LR

ENTER_SLEEP
	;NOTE.
	;1) rGSTATUS3 should have the return address after wake-up from SLEEP mode.

	ldr r0,=REFRESH
	ldr r1,[r0]		;r1=rREFRESH
	orr r1, r1, #BIT_SELFREFRESH
	str r1, [r0]		;Enable SDRAM self-refresh

	mov r1,#16			;Wait until self-refresh is issued,which may not be needed.
0	subs r1,r1,#1
	bne %B0

	ldr	r1,=MISCCR
	ldr	r0,[r1]
	orr	r0,r0,#(7<<17)  ;Set SCLK0=0, SCLK1=0, SCKE=0.
	str	r0,[r1]

	ldr r0,=CLKCON		; Enter sleep mode
	str r2,[r0]

	b .			;CPU will die here.

WAKEUP_SLEEP
	;Release SCLKn after wake-up from the SLEEP mode.
	ldr	r1,=MISCCR
	ldr	r0,[r1]
	bic	r0,r0,#(7<<17)  ;SCLK0:0->SCLK, SCLK1:0->SCLK, SCKE:0->=SCKE.
	str	r0,[r1]

	;Set memory control registers
 	ldr	r0,=SMRDATA
	ldr	r1,=BWSCON	;BWSCON Address
	add	r2, r0, #52	;End address of SMRDATA
0
	ldr	r3, [r0], #4
	str	r3, [r1], #4
	cmp	r2, r0
	bne	%B0

	mov r1,#256
0	subs r1,r1,#1	;1) wait until the SelfRefresh is released.
	bne %B0

	ldr r1,=GSTATUS3 	;GSTATUS3 has the start address just after SLEEP wake-up
	ldr r0,[r1]

	mov pc,r0

;=====================================================================
; Clock division test
; Assemble code, because VSYNC time is very short
;=====================================================================
	EXPORT CLKDIV124
	EXPORT CLKDIV144

CLKDIV124

	ldr     r0, = CLKDIVN
	ldr     r1, = 0x3		; 0x3 = 1:2:4
	str     r1, [r0]
;	wait until clock is stable
	nop
	nop
	nop
	nop
	nop

	ldr     r0, = REFRESH
	ldr     r1, [r0]
	bic		r1, r1, #0xff
	bic		r1, r1, #(0x7<<8)
	orr		r1, r1, #0x470	; REFCNT135
	str     r1, [r0]
	nop
	nop
	nop
	nop
	nop
	mov     pc, lr

CLKDIV144
	ldr     r0, = CLKDIVN
	ldr     r1, = 0x4		; 0x4 = 1:4:4
	str     r1, [r0]
;	wait until clock is stable
	nop
	nop
	nop
	nop
	nop

	ldr     r0, = REFRESH
	ldr     r1, [r0]
	bic		r1, r1, #0xff
	bic		r1, r1, #(0x7<<8)
	orr		r1, r1, #0x630	; REFCNT675 - 1520
	str     r1, [r0]
	nop
	nop
	nop
	nop
	nop
	mov     pc, lr

	ALIGN

	AREA RamData, DATA, READWRITE

	^   _ISR_STARTADDRESS		; _ISR_STARTADDRESS=0x33FF_FF00
HandleReset 	#   4
HandleUndef 	#   4
HandleSWI		#   4
HandlePabort    #   4
HandleDabort    #   4
HandleReserved  #   4
HandleIRQ		#   4
HandleFIQ		#   4

;Do not use the label 'IntVectorTable',
;The value of IntVectorTable is different with the address you think it may be.
;IntVectorTable
;@0x33FF_FF20
HandleEINT0		#   4
HandleEINT1		#   4
HandleEINT2		#   4
HandleEINT3		#   4
HandleEINT4_7	#   4
HandleEINT8_23	#   4
HandleCAM		#   4		; Added for 2440.
HandleBATFLT	#   4
HandleTICK		#   4
HandleWDT		#   4
HandleTIMER0 	#   4
HandleTIMER1 	#   4
HandleTIMER2 	#   4
HandleTIMER3 	#   4
HandleTIMER4 	#   4
HandleUART2  	#   4
;@0x33FF_FF60
HandleLCD 		#   4
HandleDMA0		#   4
HandleDMA1		#   4
HandleDMA2		#   4
HandleDMA3		#   4
HandleMMC		#   4
HandleSPI0		#   4
HandleUART1		#   4
HandleNFCON		#   4		; Added for 2440.
HandleUSBD		#   4
HandleUSBH		#   4
HandleIIC		#   4
HandleUART0 	#   4
HandleSPI1 		#   4
HandleRTC 		#   4
HandleADC 		#   4
;@0x33FF_FFA0
	END