VHDL之concurrent之when

WHEN (simple and selected)

　　It is one of the fundamental concurrent statements (along with operators and GENERATE).

　　It appears in two forms: WHEN / ELSE (simple WHEN) and WITH / SELECT / WHEN (selected WHEN).

　　1) WHEN / ELSE:

assignment  WHEN  condition  ELSE
assignment  WHEN  condition  ELSE
...;

　　2) WITH / SELECT / WHEN:

WITH  identifier  SELECT
assignment  WHEN  value,
assignment  WHEN  value,
...;

Example

　　

Solution 1　　

 ------- Solution 1: with WHEN/ELSE --------
 LIBRARY ieee;
 USE ieee.std_logic_1164.all;
 -------------------------------------------
 ENTITY mux IS
 PORT ( a, b, c, d: IN STD_LOGIC;
 　　　　sel: IN STD_LOGIC_VECTOR ( DOWNTO );
 　　　　y: OUT STD_LOGIC);
 END mux;
 -------------------------------------------
 ARCHITECTURE mux1 OF mux IS
 BEGIN
 　　y <=  a WHEN sel="" ELSE
 　　　　　 b WHEN sel="" ELSE
 　　　　　 c WHEN sel="" ELSE
 　　　　　 d;
 END mux1;
 -------------------------------------------

Solution 2

 --- Solution 2: with WITH/SELECT/WHEN -----
 LIBRARY ieee;
 USE ieee.std_logic_1164.all;
 -------------------------------------------
 ENTITY mux IS
 PORT ( a, b, c, d: IN STD_LOGIC;
 　　　　sel: IN STD_LOGIC_VECTOR ( DOWNTO );
 　　　　y: OUT STD_LOGIC);
 END mux;
 -------------------------------------------
 ARCHITECTURE mux2 OF mux IS
 BEGIN
 WITH sel SELECT
 　y <= a WHEN "", 　　-- notice "," instead of ";"
 　　　　b WHEN "",
 　　　　c WHEN "",
 　　　　d WHEN OTHERS;  -- cannot be "d WHEN "11" "
 END mux2;
 --------------------------------------------