VHDL硬件描述语言实现数字钟

--VHDL上机的一个作业，程序太长实验报告册上写不下了。于是就在博客上留一份吧。
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
 
ENTITY CLOCK IS
PORT(CLK1S,SET,SWC,CLK1MS,RST:IN STD_LOGIC;
    S0,S1,M0,M1,H0,H1:OUT STD_LOGIC_VECTOR( DOWNTO );
    BEEP:OUT STD_LOGIC;
    PNS,PSS,PSM,PSH:OUT STD_LOGIC
);
END CLOCK;
 
ARCHITECTURE ONE OF CLOCK IS
SIGNAL CS,CM:STD_LOGIC;--,CM
SIGNAL CLKSI,CLKMI,CLKHI:STD_LOGIC;
SIGNAL NS,SS,SM,SH:STD_LOGIC;
BEGIN
PSS<=SS;
PSM<=SM;
PSH<=SH;
PNS<=NS;
PROCESS(SWC,RST)
VARIABLE STAT:STD_LOGIC_VECTOR( DOWNTO );
BEGIN
IF(RST='')THEN
STAT:="";
NS<='';
SS<='';
SM<='';
SH<='';
ELSIF(RISING_EDGE(SWC))THEN
STAT:=STAT+;
CASE STAT IS
WHEN""=>
NS<='';
SS<='';
SM<='';
SH<='';
WHEN""=>
NS<='';
SS<='';
SM<='';
SH<='';
WHEN""=>
NS<='';
SS<='';
SM<='';
SH<='';
WHEN""=>
NS<='';
SS<='';
SM<='';
SH<='';
WHEN OTHERS=>
STAT:="";
END CASE;
END IF;
END PROCESS;
 
CLKSI<=(CLK1S AND NS) OR (SS AND SET);
CLKMI<=CS OR (SM AND SET);
CLKHI<=CM OR (SH AND SET);
 
PROCESS(CLKSI,RST,SET,NS)
VARIABLE SS0,SS1:STD_LOGIC_VECTOR( DOWNTO );
BEGIN
IF(RST='')THEN
SS0:="";
SS1:="";
CS<='';
--CM<='';
ELSIF(RISING_EDGE(CLKSI))THEN
SS0:=SS0+;
IF(SS0="")THEN
SS0:="";
SS1:=SS1+;
END IF;
IF(SS1="")THEN
SS1:="";
--SM0:=SM0+;
CS<='';
ELSE
CS<='';
END IF;
END IF;
S0<=SS0;
S1<=SS1;
END PROCESS;
 
PROCESS(RST,CLKMI,SET)
VARIABLE SM0,SM1:STD_LOGIC_VECTOR( DOWNTO );
BEGIN
IF(RST='')THEN
SM0:="";
SM1:="";
CM<='';
ELSIF(RISING_EDGE(CLKMI))THEN
SM0:=SM0+;
IF(SM0="")THEN
SM0:="";
SM1:=SM1+;
END IF;
IF(SM1="")THEN
SM1:="";
CM<='';
ELSE
CM<='';
END IF;
END IF;
M0<=SM0;
M1<=SM1;
END PROCESS;
 
PROCESS(RST,CLKHI,SET)
VARIABLE SH0,SH1:STD_LOGIC_VECTOR( DOWNTO );
BEGIN
IF(RST='')THEN
SH0:="";
SH1:="";
ELSIF(RISING_EDGE(CLKHI))THEN
SH0:=SH0+;
IF(SH0="")THEN
SH0:="";
SH1:=SH1+;
END IF;
IF(SH1="" AND SH0="")THEN
SH1:="";
SH0:="";
END IF;
END IF;
H0<=SH0;
H1<=SH1;
END PROCESS;
 
PROCESS(CM,CS)
BEGIN
IF(CM='' AND CS='')THEN
BEEP<=CLK1MS;
ELSE
BEEP<='';
END IF;
END PROCESS;
END ONE;