1  synthesis steps

1)  Search Paths    

    rc:/> set_attribute  lib_search_path path /
    rc:/> set_attribute  script_search_path  path / 
    rc:/> set_attribute  hdl_search_path  path /

2)  Target Technology Library

    rc:/> set_attribute   library  lib_name.lib 

   - Target Library: Design Compiler uses the target library to build a circuit. During mapping, Design Compiler selects functionally correct gates from the target library. It also calculates the timing of the circuit, using the vendor-supplied timing data for these gates.

3)  Loading the HDL Files

   - sequentially:   read_hdl   file1.v  read_hdl   file2.v  read_hdl   file3.v 

   - simultaneously: read_hdl  { file1.v file2.v file3.v }  

read_hdl [-v1995 | -v2001 | -sv
| -vhdl [-library library_name ]
| -netlist]
[-define macro=value ] ... file_list

4)  Performing Elaboration

    This is only required for top-level design. The elaborate command automatically elaborates the top-level design and all of its references.

5)  Applying Constraints

     - Operating conditions; clock waveforms; I/O timing

6)  Applying Optimization Constraints

7)  Performing Synthesis

    rc:\> synthesize -to_mapped

8)  Analyzing the Synthesis Results

    - generate a detailed area report, use report area

    - generate a detailed gate selection and area report, use report gates

    - generate a detailed timing report, including the worst critical path of the current design, use report timing

9)  Exporting the Design

   - gate-level netlist  rc:/> write_hdl > design.v

   - design constraints  rc:/> write_script > constraints.g 

   - constraints in SDC format rc:/> write_sdc > constraints.sdc

10)  Exiting RTL Compiler

    quit or exit

2  recommended flow

#general setup
#--------------
set_attributer lib_search_path ...
set_attribute hdl_search_path ..
#load the library
#------------------------------
set_attribute library library_name
#load and elaborate the design
#------------------------------
read_hdl design.v
elaborate
#specify timing and design constraints
#--------------------------------------
read_sdc sdc_file
# add optimization constraints
#----------------------------
.....
#synthesize the design
#---------------------
synthesize -to_mapped
#analyze design
------------------
report area
report timing
report gates
#export design
#-------------
write_hdl > dessign.vm
write_sdc > constraints.sdc
write_script > constraints.g
# export design for EDI
#-----------------------
write_design [-basename string ] [-gzip_files] [-tcf]
[-encounter] [-hierarchical] [ design ]

3  working in the top-level(root) directory

  Root is a special object that contains all other objects represented as a ‘tree’ underneath it.

  The root object is always present in RTL Compiler and is represented by a “/”, as shown in above Figure.

  Root attributes contain information about all loaded designs.

RTL Compiler之synthesis steps的更多相关文章

  1. RTL Compiler之synthesis flow

    1 generic RTL Compiler work flow 2 invoking RTL compiler RTL Compiler is invoked from the operating ...

  2. RTL Compiler之Example

    Synthesis = Translation +  Logic Optimization + Mapping Step 1 Source files 1) make directory mkdir ...

  3. RTL Compiler之Technology Library

    1 Target Library Design Compiler uses the target library to build a circuit. During mapping, Design ...

  4. 行为级和RTL级的区别(转)

    转自:http://hi.baidu.com/renmeman/item/5bd83496e3fc816bf14215db RTL级,registertransferlevel,指的是用寄存器这一级别 ...

  5. Verilog的数据流、行为、结构化与RTL级描述

    Verilog语言可以有多种方式来描述硬件,同时,使用这些描述方式,又可以在多个抽象层次上设计硬件,这是Verilog语言的重要特征. 在Verilog语言中,有以下3种最基本的描述方式: 数据流描述 ...

  6. RTL 与 technology schematic的区别,包含概念与实例

    2013-06-25 16:40:45 下面是xilinx官网上的问答贴: http://china.xilinx.com/support/answers/41500.htm#solution The ...

  7. 1.2 the structure of a compiler

    Compiler 1.2 the structure  of a compiler Compiler : analysis and synthesis syntactically  语法上的 sema ...

  8. Tcl之Read files for synthesis

    The following file is to read all design files into syntehsis tool automatically, like Cadence RTL C ...

  9. backend flow

    在PD之后,netlist中会多出很多DCAP元件(去耦电容,减少IR-Drop)或者filter cell(保证芯片均匀度要求) 还有一些antenna cell也就是一些diode用来泻流,防止天 ...

随机推荐

  1. 这段百度问答,对我相关有对啊!!!----如何获取Windows系统登陆用户名

    如何获取Windows系统登陆用户名 http://zhidao.baidu.com/link?url=Hva9PkVwYZv8KSEWftSqTWe8fqM1dhoq59BurnfADmcOvFjF ...

  2. ERROR 1045 (28000)

    mysql登陆出现这个错误时,解决方法如下: 1. 修改mysql配置文件,增加 skip-grant-tables 如我的机器是linux 所以要修改/etc/mysql/my.cnf 在mysql ...

  3. Oracle Multitenant Environment (三) Plan for a cdb

    Below tables contains contant you need to consider while planning for a CDB. Action Considerations f ...

  4. Asp.Net实现JS前台带箭头的流程图方法总结!(个人笔记,信息不全)

    Asp.Net实现JS前台带箭头的流程图方法总结!(持续更新中) 一.返回前台json格式 json5 = "[{\"Id\":2259,\"Name\&quo ...

  5. 【剑指offer】斐波那契序列与跳台阶

    转载请注明出处:http://blog.csdn.net/ns_code/article/details/25337983 剑指offer上的第9题,简单题,在九度OJ上測试通过. 主要注意下面几点: ...

  6. 在word中doc与docx的区别是什么(整理)

    在word中doc与docx的区别是什么(整理) docx 是Office2007使用的,是用新的基于XML的压缩文件格式取代了其目前专有的默认文件格式,在传统的文件名扩展名后面添加了字母x(即.do ...

  7. caffe to tensorflow alexnet model

    from kaffe.tensorflow import Network class AlexNet(Network): def setup(self): (self.feed('data') .co ...

  8. [python基础] csv.wirterow()报错UnicodeEncodeError

    python在安装时,默认的编码是ascii,当程序中出现非ascii编码时,python的处理常常会报这样的错,python没办法处理非ascii编码的,此时需要自己设置将python的默认编码,一 ...

  9. HDU4336:Card Collector

    题意 有n张卡片,每一次 有pi的概率买到第i张卡.求买到所有卡的期望购买次数. n<=20 解析 Solution 1:大力状压(就是步数除以方案数) #include<iostream ...

  10. [Swift通天遁地]七、数据与安全-(1)XML文档的创建和解析

    ★★★★★★★★★★★★★★★★★★★★★★★★★★★★★★★★★★★★★★★★➤微信公众号:山青咏芝(shanqingyongzhi)➤博客园地址:山青咏芝(https://www.cnblogs. ...