VHDL之Serial-Parallel Multiplier

1　　Serial-parallel multiplier

　　Figure 12.1 shows the RTL diagram of a serial-parallel multiplier. One of the input vectors (a) is applied serially to the circuit (one bit at a time, starting from the LSB), while the other (b) is applied in parallel (all bits simultaneously). Say that a has M bits, while b has N. Then, after all M bits of a have been presented to the system, a string of M ‘0’s must follow, in order to complete the (M þ N)-bit output product.

　　

　　This system is pipelined, and is constructed using AND gates, full-adder units, plus registers (flip-flops). Each unit of the pipeline (except the leftmost one) requires one adder and two registers, plus an AND gate to compute one of the inputs. Thus for an M x N multiplier, O(N) of such units are required.

2　　VHDL

　　1)　and_2.vhd

 library IEEE;
 use ieee.std_logic_1164.all;

 entity and_2 is
 port
 (
     a, b:    in    std_logic;
     y:        out    std_logic
 );
 end and_2;

 architecture sim of and_2 is
 begin
     y    <=    a and b;

 end sim;

　　2)　reg.vhd

 library IEEE;
 use ieee.std_logic_1164.all;

 entity reg is
 port
 (
     d, clk, rst:    in    std_logic;
     q:                out std_logic
 );
 end reg;

 architecture sim of reg is
 begin
     process(clk, rst)
     begin
         if (rst = '') then q <= '';
         elsif (clk'event and clk = '') then q <= d;
         end if;
     end process;

 end sim;

　　3)　fau.vhd

 library IEEE;
 use ieee.std_logic_1164.all;

 entity fau is
 port
 (
     a, b, cin:    in    std_logic;
     s, cout:    out    std_logic
 );
 end fau;

 architecture sim of fau is
 begin
     s <= a xor b xor cin;
     cout <= (a and b) or (a and cin) or (b and cin);

 end sim;    

　　4)　　pipe

 library IEEE;
 use ieee.std_logic_1164.all;

 library work;
 use work.my_components.all;

 entity pipe is
 port
 (
     a, b, clk, rst: in    std_logic;
     q:                out    std_logic
 );
 end pipe;

 architecture sim of pipe is
     signal s, cin, cout: std_logic;
 begin
     U1: component fau port map(a, b, cin, s, cout);
     U2: component reg port map(cout, clk, rst, cin);
     U3: component reg port map(s, clk, rst, q);
 end sim;

　　5)　my_components.vhd

 library IEEE;
 use ieee.std_logic_1164.all;

 package my_components is

 component and_2 is
 port
 (
     a, b:    in    std_logic;
     y:        out    std_logic
 );
 end component;

 component fau is
 port
 (
     a, b, cin:    in    std_logic;
     s, cout:    out std_logic
 );
 end component;

 component reg is
 port
 (
     d, clk, rst:    in    std_logic;
     q:                out    std_logic
 );
 end component;

 component pipe is
 port
 (
     a, b, clk, rst:    in    std_logic;
     q:                out std_logic
 );
 end component;

 end my_components;

　　6)　multiplier.vhd

 library IEEE;
 use ieee.std_logic_1164.all;

 library work;
 use work.my_components.all;

 entity multiplier is
 port
 (
     a, clk, rst:    in    std_logic;
     b:                in    std_logic_vector( downto );
     prod:            out std_logic
 );
 end multiplier;

 architecture sim of multiplier is
     signal and_out, reg_out: std_logic_vector( downto );
 begin
     U1: component and_2 port map(a, b(), and_out());
     U2:    component and_2 port map(a, b(), and_out());
     U3: component and_2 port map(a, b(), and_out());
     U4: component and_2 port map(a, b(), and_out());
     U5: component reg port map(and_out(), clk, rst, reg_out());
     U6: component pipe port map(and_out(), reg_out(), clk, rst, reg_out());
     U7: component pipe port map(and_out(), reg_out(), clk, rst, reg_out());
     U8: component pipe port map(and_out(), reg_out(), clk, rst, reg_out());

     prod <= reg_out();

 end sim;