Verilog MIPS32 CPU（六）-- MDU

• Verilog MIPS32 CPU（一）-- PC寄存器
• Verilog MIPS32 CPU（二）-- Regfiles
• Verilog MIPS32 CPU（三）-- ALU
• Verilog MIPS32 CPU（四）-- RAM
• Verilog MIPS32 CPU（五）-- CP0
• Verilog MIPS32 CPU（六）-- MDU
• Verilog MIPS32 CPU（七）-- DIV、DIVU
• Verilog MIPS32 CPU（八）-- 控制器

module MDU(
        input clk,rst,
        input [:] mdu,
        input [:] rdata1,rdata2,
        output [:] mul_out,
        output reg pc_ena,
        output reg [:] hi,lo);

    wire div_start,divu_start,div_busy,divu_busy,div_over,divu_over;
    wire [:] mult_out,multu_out,div_out,divu_out;

    assign    mul_out    =    mult_out;
    /*
        1    mult
        2    multu
        3    div
        4    divu
        5    mthi
        6    mtlo
    */
    //assign pc_ena=1'b1;

    always@(*)begin
        case(mdu)
            'h3:    pc_ena    =    div_over ||mdu!=3'h3;
            'h4:    pc_ena    =    divu_over||mdu!=3'h4;
            default:pc_ena    =    'b1;
        endcase
    end

    assign    div_start    =    mdu=='h3&&!div_busy;
    assign    divu_start    =    mdu=='h4&&!divu_busy;

    always@(posedge clk or posedge rst)begin
        if(rst) begin
            hi<='b0;
            lo<='b0;
        end
        else begin
            case(mdu)
                'h1:    {hi,lo}    <=    mult_out;
                'h2:    {hi,lo}    <=    multu_out;
                'h3:    {lo,hi}    <=    div_out;
                'h4:    {lo,hi}    <=    divu_out;
                'h5:    hi         <=    rdata1;
                'h6:    lo        <=    rdata1;
            endcase
        end
    end
    mult_gen_0 multiplier(
        .A(rdata1),
        .B(rdata2),
        .P(mult_out));

    mult_gen_1 multiplier_unsigned(
        .A(rdata1),
        .B(rdata2),
        .P(multu_out));

    DIV DIV(
        .dividend(rdata1),
        .divisor(rdata2),
        .clock(clk),
        .reset(mdu!='h3),
        .start(div_start),
        .q(div_out[:]),
        .r(div_out[:]),
        .over(div_over),
        .busy(div_busy));

    DIVU DIVU(
        .dividend(rdata1),
        .divisor(rdata2),
        .clock(clk),
        .reset(mdu!='h4),
        .start(divu_start),
        .q(divu_out[:]),
        .r(divu_out[:]),
        .over(divu_over),
        .busy(divu_busy));
endmodule