FPGA之CORDIC算法实现_代码实现(下）

关于FPGA之CORDIC算法的纯逻辑实现，善良的一休军“https://blog.csdn.net/qq_39210023/article/details/77456031”的博文均给出了较为详细完整的代码，整个算法的思想较为简单，就

是利用迭代流水线的思想，让角度不停逼近所求角度，一般迭代16次就已经比较接近所求角度值：

1、算法实现步骤：

1）设置迭代次数为16，则x0 = 0.607253，y0 = 0（关于初值的设定，上一篇博文有写到）并输入待计算的角度θ，θ在[-99.7°，99.7°]范围内。

2）根据三个迭代公式进行迭代，i从0至15：
xi+1 = xi – d iy i2-i
yi+1 = yi + d ix i2-i
zi+1 = zi - diθi
注：z0 = θ，di与zi同符号。

3） 经过16次迭代计算后，得到的x16 和y16分别为cosθ和sinθ。

2、代码解析：

1）16级流水线迭代实现

always  @(posedge clk or negedge rst_n)begin
    if(rst_n=='b0)begin
        x[]   <= ;
        y[]   <= ;
        z[]   <= (din<<);
    end
    else if(din_vld_ff[]) begin   //初始化设置赋值 x0==0.607253*2^16,y0=0;
        x[]   <= {'b0,COS_LM};
        y[]   <= ;
        z[]   <= {'b0,din_ff,16'b0};  //角度初始化设置
    end
end
 
always  @(posedge clk or negedge rst_n)begin
    if(rst_n=='b0)begin
        x[]   <= ;
        y[]   <= ;
        z[]   <= ;
    end
    else if(din_vld_ff[])begin
        if(z[][]==)begin
            x[] <= x[] - (y[]>>>);
            y[] <= y[] + (x[]>>>);
            z[] <= z[] - `ROT0;
        end
        else begin
            x[] <= x[] + (y[]>>>);
            y[] <= y[] - (x[]>>>);
            z[] <= z[] + `ROT0;
        end
    end
end
 
always  @(posedge clk or negedge rst_n)begin
    if(rst_n=='b0)begin
        x[]   <= ;
        y[]   <= ;
        z[]   <= ;
    end
    else if(din_vld_ff[])begin
        if(z[][]==)begin
            x[] <= x[] - (y[]>>>);
            y[] <= y[] + (x[]>>>);
            z[] <= z[] - `ROT1;
        end
        else begin
            x[] <= x[] + (y[]>>>);
            y[] <= y[] - (x[]>>>);
            z[] <= z[] + `ROT1;
        end
    end
end
 
always  @(posedge clk or negedge rst_n)begin
    if(rst_n=='b0)begin
        x[]   <= ;
        y[]   <= ;
        z[]   <= ;
    end
    else if(din_vld_ff[])begin
        if(z[][]==)begin
            x[] <= x[] - (y[]>>>);
            y[] <= y[] + (x[]>>>);
            z[] <= z[] - `ROT2;
        end
        else begin
            x[] <= x[] + (y[]>>>);
            y[] <= y[] - (x[]>>>);
            z[] <= z[] + `ROT2;
        end
    end
end
 
always  @(posedge clk or negedge rst_n)begin
    if(rst_n=='b0)begin
        x[]   <= ;
        y[]   <= ;
        z[]   <= ;
    end
    else if(din_vld_ff[])begin
        if(z[][]==)begin
            x[] <= x[] - (y[]>>>);
            y[] <= y[] + (x[]>>>);
            z[] <= z[] - `ROT3;
        end
        else begin
            x[] <= x[] + (y[]>>>);
            y[] <= y[] - (x[]>>>);
            z[] <= z[] + `ROT3;
        end
    end
end
 
always  @(posedge clk or negedge rst_n)begin
    if(rst_n=='b0)begin
        x[]   <= ;
        y[]   <= ;
        z[]   <= ;
    end
    else if(din_vld_ff[])begin
        if(z[][]==)begin
            x[] <= x[] - (y[]>>>);
            y[] <= y[] + (x[]>>>);
            z[] <= z[] - `ROT4;
        end
        else begin
            x[] <= x[] + (y[]>>>);
            y[] <= y[] - (x[]>>>);
            z[] <= z[] + `ROT4;
        end
    end
end
 
always  @(posedge clk or negedge rst_n)begin
    if(rst_n=='b0)begin
        x[]   <= ;
        y[]   <= ;
        z[]   <= ;
    end
    else if(din_vld_ff[])begin
        if(z[][]==)begin
            x[] <= x[] - (y[]>>>);
            y[] <= y[] + (x[]>>>);
            z[] <= z[] - `ROT5;
        end
        else begin
            x[] <= x[] + (y[]>>>);
            y[] <= y[] - (x[]>>>);
            z[] <= z[] + `ROT5;
        end
    end
end
 
always  @(posedge clk or negedge rst_n)begin
    if(rst_n=='b0)begin
        x[]   <= ;
        y[]   <= ;
        z[]   <= ;
    end
    else if(din_vld_ff[])begin
        if(z[][]==)begin
            x[] <= x[] - (y[]>>>);
            y[] <= y[] + (x[]>>>);
            z[] <= z[] - `ROT6;
        end
        else begin
            x[] <= x[] + (y[]>>>);
            y[] <= y[] - (x[]>>>);
            z[] <= z[] + `ROT6;
        end
    end
end
 
always  @(posedge clk or negedge rst_n)begin
    if(rst_n=='b0)begin
        x[]   <= ;
        y[]   <= ;
        z[]   <= ;
    end
    else if(din_vld_ff[])begin
        if(z[][]==)begin
            x[] <= x[] - (y[]>>>);
            y[] <= y[] + (x[]>>>);
            z[] <= z[] - `ROT7;
        end
        else begin
            x[] <= x[] + (y[]>>>);
            y[] <= y[] - (x[]>>>);
            z[] <= z[] + `ROT7;
        end
    end
end
 
always  @(posedge clk or negedge rst_n)begin
    if(rst_n=='b0)begin
        x[]   <= ;
        y[]   <= ;
        z[]   <= ;
    end
    else if(din_vld_ff[])begin
        if(z[][]==)begin
            x[] <= x[] - (y[]>>>);
            y[] <= y[] + (x[]>>>);
            z[] <= z[] - `ROT8;
        end
        else begin
            x[] <= x[] + (y[]>>>);
            y[] <= y[] - (x[]>>>);
            z[] <= z[] + `ROT8;
        end
    end
end
 
always  @(posedge clk or negedge rst_n)begin
    if(rst_n=='b0)begin
        x[]   <= ;
        y[]   <= ;
        z[]   <= ;
    end
    else if(din_vld_ff[])begin
        if(z[][]==)begin
            x[] <= x[] - (y[]>>>);
            y[] <= y[] + (x[]>>>);
            z[] <= z[] - `ROT9;
        end
        else begin
            x[] <= x[] + (y[]>>>);
            y[] <= y[] - (x[]>>>);
            z[] <= z[] + `ROT9;
        end
    end
end
 
always  @(posedge clk or negedge rst_n)begin
    if(rst_n=='b0)begin
        x[]   <= ;
        y[]   <= ;
        z[]   <= ;
    end
    else if(din_vld_ff[])begin
        if(z[][]==)begin
            x[] <= x[] - (y[]>>>);
            y[] <= y[] + (x[]>>>);
            z[] <= z[] - `ROT10;
        end
        else begin
            x[] <= x[] + (y[]>>>);
            y[] <= y[] - (x[]>>>);
            z[] <= z[] + `ROT10;
        end
    end
end
 
always  @(posedge clk or negedge rst_n)begin
    if(rst_n=='b0)begin
        x[]   <= ;
        y[]   <= ;
        z[]   <= ;
    end
    else if(din_vld_ff[])begin
        if(z[][]==)begin
            x[] <= x[] - (y[]>>>);
            y[] <= y[] + (x[]>>>);
            z[] <= z[] - `ROT11;
        end
        else begin
            x[] <= x[] + (y[]>>>);
            y[] <= y[] - (x[]>>>);
            z[] <= z[] + `ROT11;
        end
    end
end
 
always  @(posedge clk or negedge rst_n)begin
    if(rst_n=='b0)begin
        x[]   <= ;
        y[]   <= ;
        z[]   <= ;
    end
    else if(din_vld_ff[])begin
        if(z[][]==)begin
            x[] <= x[] - (y[]>>>);
            y[] <= y[] + (x[]>>>);
            z[] <= z[] - `ROT12;
        end
        else begin
            x[] <= x[] + (y[]>>>);
            y[] <= y[] - (x[]>>>);
            z[] <= z[] + `ROT12;
        end
    end
end
 
always  @(posedge clk or negedge rst_n)begin
    if(rst_n=='b0)begin
        x[]   <= ;
        y[]   <= ;
        z[]   <= ;
    end
    else if(din_vld_ff[])begin
        if(z[][]==)begin
            x[] <= x[] - (y[]>>>);
            y[] <= y[] + (x[]>>>);
            z[] <= z[] - `ROT13;
        end
        else begin
            x[] <= x[] + (y[]>>>);
            y[] <= y[] - (x[]>>>);
            z[] <= z[] + `ROT13;
        end
    end
end
 
always  @(posedge clk or negedge rst_n)begin
    if(rst_n=='b0)begin
        x[]   <= ;
        y[]   <= ;
        z[]   <= ;
    end
    else if(din_vld_ff[])begin
        if(z[][]==)begin
            x[] <= x[] - (y[]>>>);
            y[] <= y[] + (x[]>>>);
            z[] <= z[] - `ROT14;
        end
        else begin
            x[] <= x[] + (y[]>>>);
            y[] <= y[] - (x[]>>>);
            z[] <= z[] + `ROT14;
        end
    end
end
 
always  @(posedge clk or negedge rst_n)begin
    if(rst_n=='b0)begin
        x[]   <= ;
        y[]   <= ;
        z[]   <= ;
    end
    else if(din_vld_ff[])begin
        if(z[][]==)begin
            x[] <= x[] - (y[]>>>);
            y[] <= y[] + (x[]>>>);
            z[] <= z[] - `ROT15;
        end
        else begin
            x[] <= x[] + (y[]>>>);
            y[] <= y[] - (x[]>>>);
            z[] <= z[] + `ROT15;
        end
    end
end

2）打拍同步

这点是我看了博主“洋葱洋葱”的代码，发现的简洁打拍写法。

a、din_vld是单比特信号，假设信号din_vld打4拍输入，可以对比下简洁写法和传统写法的代码量：

//传统写法：将信号din_vld_ff打4拍
always  @(posedge clk or negedge rst_n)begin
    if(rst_n=='b0)begin
        din_vld_ff <=;
        din_vld_ff0 <= ;
        din_vld_ff1 <= ;
        din_vld_ff2 <= ;
    end
    else begin
        din_vld_ff0 <= din_vld_ff;
        din_vld_ff1 <= din_vld_ff0;
        din_vld_ff2 <= din_vld_ff1;
    end
end
 
//简洁写法：将信号din_vld_ff打4拍
always @(posedge clk or negedge rst_n )begin
    if(rst_n==) begin
        din_vld_ff <= ()  ;
    end
    else begin
        din_vld_ff <= ({din_vld_ff[:],din_vld})  ;  //din_vld为1bit
    end
end

以上是单比特din_vld打4拍的对比写法，假如是要打十几拍，可以明显看出简洁写法的代码量少很多，这种打拍子的写法值得推崇。

b、din_vld是多比特信号，假设din_vld同样打4拍输入，利用简洁写法可以写成：

always @(posedge clk or negedge rst_n )begin
    if(rst_n==) begin
        din_vld_ff <= ()  ;
    end
    else begin
        din_vld_ff <= ({din_vld_ff[5:],din_vld})  ;  //din_vld为2bit
    end
end

3）反正切函数，要注意由于θ在[-99.7°，99.7°]范围内，因此在角度输入时要注意换成第一、第四象限，最后结果输出时要注意还原成真实角度。

always  @(posedge clk or negedge rst_n)begin
    if(rst_n=='b0)begin
        din_ff <= ;
        flag   <= ;
    end
    else if(din_vld)begin
        if(din<)begin
            din_ff = din;
            flag   = ;
        end
        else if(din<)begin
            din_ff = din-;
            flag   = ;
        end
        else if(din<)begin
            din_ff = din-;
            flag   = ;
        end
        else begin
            din_ff = din-;
            flag   = ;
        end
    end
end

//角度还原为真实值
always @(posedge clk or negedge rst_n )begin
    if(rst_n==) begin
        dout_sin <= ()  ;
    end
    else if(flag_ff[:]==)begin       //第一象限，y(16) = sin(x)
        dout_sin <= (y[])  ;
    end
    else if(flag_ff[:]==)begin       //第二象限，Sin(X)=Sin(A+90)=CosA,Cos(X)=Cos(A+90)=-SinA
        dout_sin <= (x[])  ;
    end
    else if(flag_ff[:]==)begin       //第三象限，the Sin(X)=Sin(A+180)=-SinA,Cos(X)=Cos(A+180)=-CosA
        dout_sin <= ~(y[]) + 'b1  ;
    end
    else if(flag_ff[:]==)begin       //第四象限，the Sin(X)=Sin(A+270)=-CosA,Cos(X)=Cos(A+270)=SinA
        dout_sin <= ~(x[]) 

至此，基于FPGA的cordic算法代码实现需要注意的问题就讨论到这里。