附录：ARM 手册 词汇表

来自：《DDI0406C_C_arm_architecture_reference_manual.pdf》p2723

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能够查询到：“RAZ RAO WI 等的意思”

RAZ：Read-As-Zero 读到的总是0

RAO：Read-As-Oned读到的总是1

WI　：Writes Ignoredx 写无效

SBZP：Should-Be-Zero-or-Preserved on writes 写总是0

SBOP ： Should-Be-One-or-Preserved on writes. 写总是1

UNK：unknown 读写时返回值未知

Abort
An exception caused by an illegal memory access. Aborts can be caused by the external memory system or the MMU or MPU.

Addressing mode
Means a method for generating the memory address used by a load/store instruction.

Advanced SIMD
An extension to the ARM architecture that provides SIMD operations on a bank of extension registers. If the Floating-point extension is also implemented, the two extensions share the register bank and the Advanced SIMD operations include single-precision floating-point SIMD operations.

Aligned
A data item stored at an address that is divisible by the highest power of 2 that divides into its size in bytes. Aligned halfwords, words and doublewords therefore have addresses that are divisible by 2, 4 and 8 respectively.
An aligned access is one where the address of the access is aligned to the size of each element of the access.

Architecturally executed
An instruction is architecturally executed only if it would be executed in a simple sequential execution of the program. When such an instruction has been executed and retired is has been architecturally executed. Any instruction that, in a simple sequential execution of a program, is treated as a NOP because it fails its condition code check, is an architecturally executed instruction.

In a processor that performs speculative execution, an instruction is not  architecturally executed if the processor discards the results of a speculative execution.

ARM core registers
The ARM core registers comprise:
• thirteen general-purpose registers, R0 to R12, that software can use for processing
• SP, the stack pointer, that can also be referred to as R13
• LR, the link register, that can also be referred to as R14
• PC, the program counter, that can also be referred to as R15.

In some situations, software can use SP, LR, and PC for processing. The instruction descriptions include any constraints on the use of SP, LR, and PC.
See also High registers.

ARM instruction
A word that specifies an operation for a processor in ARM state to perform. ARM instructions must be word-aligned.

Associativity
See Cache associativity.

Atomicity
Describes either single-copy atomicity or multi-copy atomicity. Atomicity in the ARM architecture on page A3-128 defines these forms of atomicity for the ARM architecture.
See also Multi-copy atomicity, Single-copy atomicity.

Banked register
A register that has multiple instances, with the instance that is in use depending on the processor mode, security state, or other processor state.

Base register
A register specified by a load/store instruction that is used as the base value for the address calculation for the instruction. Depending on the instruction and its addressing mode, an offset can be added to or subtracted from the base register value to form the virtual address that is sent to memory.

Base register writeback
Describes writing back a modified value to the base register used in an address calculation.

Big-endian memory
Means that:
• a byte or halfword at a word-aligned address is the most significant byte or halfword in the word at that address
• a byte at a halfword-aligned address is the most significant byte in the halfword at that address.

Blocking
Describes an operation that does not permit following instructions to be executed before the operation completes.

A non-blocking operation can permit following instructions to be executed before the operation completes, and in the event of encountering an exception does not signal an exception to the processor. This enables implementations to retire following instructions while the non-blocking operation is executing, without the need to retain precise processor state.

Branch prediction
Is where a processor selects a future execution path to fetch along. For example, after a branch instruction, the processor can choose to speculatively fetch either the instruction following the branch or the instruction at the branch target.
See also Prefetching.

Breakpoint
A debug event triggered by the execution of a particular instruction, specified by one or both of the address of the instruction and the state of the processor when the instruction is executed.

Byte
An 8-bit data item.

Cache associativity
The number of locations in a cache set to which an address can be assigned. Each location is identified by its way value.

Cache hit
A memory access that can be processed at high speed because the data it addresses is already in the cache.

Cache level
The position of a cache in the cache hierarchy. In the ARM architecture, the lower numbered levels are those closest to the processor. For more information see Terms used in describing the maintenance operations on page B2-1274.

Cache line
The basic unit of storage in a cache. Its size in words is always a power of two, usually 4 or 8 words. A cache line must be aligned to a suitable memory boundary. A memory cache line is a block of memory locations with the same size and alignment as a cache line. Memory cache lines are sometimes loosely called cache lines.

Cache lockdown
Enables critical software and data to be loaded into the cache so that the cache lines containing them are not subsequently reallocated. It alleviates the delays caused by accessing a cache in a worst-case situation. This ensures that all subsequent accesses to the software and data concerned are cache hits and so complete quickly.

Cache miss
A memory access that cannot be processed at high speed because the data it addresses is not in the cache.

Cache sets
Areas of a cache, divided up to simplify and speed up the process of determining whether a cache hit occurs. The number of cache sets is always a power of two.

Cache way
A cache way consists of one cache line from each cache set. The cache ways are indexed from 0 to (Associativity-1).

Each cache line in a cache way is chosen to have the same index as the cache way. For example, cache way n consists of the cache line with index n from each cache set.

Coherence order
See Coherent.

Coherent
Data accesses from a set of observers to a byte in memory are coherent if accesses to that byte in memory by the members of that set of observers are consistent with there being a single total order of all writes to that byte in memory by all members of the set of observers. This single total order of all writes to that memory location is the coherence order for that byte in memory.

Condition code check
The process of determining whether a conditional instruction executes normally or is treated as a NOP. For an instruction that includes a condition code field, that field is compared with the condition flags to determine whether the instruction is executed normally. For a Thumb instruction in an IT block, the value of the ITSTATE register determines whether the instruction is executed normally.

See also Condition code field, Condition flags, Conditional execution.

Condition code field
A 4-bit field in an instruction that specifies the condition under which the instruction executes.

See also Condition code check.

Condition flags
The N, Z, C, and V bits of the APSR, CPSR, SPSR, or FPSCR. See the register descriptions for more information.

Conditional execution
When a conditional instruction starts executing, if the condition code check returns TRUE, the instruction executes normally. Otherwise, it is treated as a NOP.

See also Condition code check.

Context switch
The saving and restoring of computational state when switching between different threads  or processes. In this manual, the term context switch describes any situations where the context is switched by an operating system and might or might not include changes to the address space.

Context synchronization operation

One of:
• Performing an ISB operation. An ISB operation is performed when an ISB instruction is executed and does not fail its condition code check.
• Taking an exception.
• Returning from an exception.
The architecture requires a context synchronization operation to guarantee visibility of any change to a system control register.

Deprecated
Something that is present in the ARM architecture for backwards compatibility. Whenever possible software must avoid using deprecated features. Features that are deprecated but are not optional are present in current implementations of the ARM architecture, but might not be present, or might be deprecated and OPTIONAL, in future versions of the ARM architecture.

See also OPTIONAL.

Digital signal processing (DSP)
Algorithms for processing signals that have been sampled and converted to digital form. DSP algorithms often use saturated arithmetic.

Direct Memory Access (DMA)
An operation that accesses main memory directly, without the processor performing any accesses to the data concerned.

DMA
See Direct Memory Access (DMA).

DNM
See Do-Not-Modify (DNM).

Domain
In the ARM architecture, domain is used in the following contexts.

Shareability domain
    Defines a set of observers for which the shareability attributes make the data or unified  caches transparent for data accesses.
    
    Power domain
    Defines a block of logic with a single, common, power supply.

Memory regions domain
    When using the Short-descriptor translation table format, defines a collection of Sections, Large pages and Small pages of memory, that can have their access permissions switched rapidly by writing to the Domain Access Control Register (DACR). ARM deprecates any use of memory regions domains.

Do-Not-Modify (DNM)
Means the value must not be altered by software. DNM fields read as UNKNOWN values, and must only be written with the value read from the same field on the same processor.

Double-precision value
Consists of two consecutive 32-bit words that are interpreted as a basic double-precision floating-point number according to the IEEE 754 standard.

Doubleword
A 64-bit data item. Doublewords are normally at least word-aligned in ARM systems.

Doubleword-aligned
Means that the address is divisible by 8.

DSP
See Digital signal processing (DSP).

Endianness
An aspect of the system memory mapping.

See also Big-endian memory and Little-endian memory.

Exception
Handles an event. For example, an exception could handle an external interrupt or an undefined instruction.

Exception vector
A fixed address that contains the address of the first instruction of the corresponding exception handler.

Execution stream
The stream of instructions that would have been executed by sequential execution of the program.

Explicit access
A read from memory, or a write to memory, generated by a load or store instruction executed by the processor. Reads and writes generated by hardware translation table accesses are not explicit accesses.

External abort
An abort that is generated by the external memory system.

Fast Context Switch Extension (FCSE)
Modifies the behavior of an ARM memory system to enable multiple programs running on the ARM processor to use identical address ranges, while ensuring that the addresses they present to the rest of the memory system differ.
From ARMv6, ARM deprecates any use of the FCSE. The FCSE is:
• optional in an ARMv7 implementation that does not include the Multiprocessing Extensions
• obsolete from the introduction of the Multiprocessing Extensions.

FCSE

See Fast Context Switch Extension (FCSE).

Flat address mapping
Is where the physical address for every access is equal to its virtual address.

Flush-to-zero mode
A special processing mode that optimizes the performance of some floating-point algorithms by replacing the denormalized operands and intermediate results with zeros, without significantly affecting the accuracy of their final results.

General-purpose registers
An older term for the ARM core registers.

See also ARM core registers.

Halfword
A 16-bit data item. Halfwords are normally halfword-aligned in ARM systems.

Halfword-aligned
Means that the address is divisible by 2.

High registers
ARM core registers 8 to 15, that cannot be accessed by some Thumb instructions.

See also Low registers.

High vectors
An alternative location for the exception vectors. The high vector address range is near the top of the address space, rather than at the bottom.

Hit

See Cache hit.

IGNORED
Indicates that the architecture guarantees that the bit or field is not interpreted or modified by hardware.

In body text, the term IGNORED is shown in SMALL CAPITALS.

Immediate and offset fields
Are unsigned unless otherwise stated.

Immediate value
A value that is encoded directly in the instruction and used as numeric data when the instruction is executed. Many ARM and Thumb instructions can be used with an immediate argument.

IMP
An abbreviation used in diagrams to indicate that one or more bits have IMPLEMENTATION DEFINED behavior.

IMPLEMENTATION DEFINED
Means that the behavior is not architecturally defined, but must be defined and documented by individual implementations. In body text, the term IMPLEMENTATION DEFINED is shown in SMALL CAPITALS.

Index register
A register specified in some load and store instructions. The value of this register is used as an offset to be added to or subtracted from the base register value to form the virtual address that is sent to memory. Some instruction forms permit the index register value to be shifted before the addition or subtraction.

Inline literals
These are constant addresses and other data items held in the same area as the software itself. They are automatically generated by compilers, and can also appear in assembler code.

Intermediate Physical Address (IPA)
An implementation of virtualization, the address to which an Guest OS maps a VA.

See also Physical address (PA), Virtual address (VA).

Interworking
A method of working that permits branches between software using the ARM and Thumb instruction sets.

IPA
See Intermediate Physical Address (IPA).

Level
See Cache level.

Level of coherence (LoC)
The last level of cache that must be cleaned or invalidated when cleaning or invalidating to the point of coherency.

For more information see Terms used in describing the maintenance operations on page B2-1274.

See also Cache level, Point of coherency (PoC).

Level of unification, Inner Shareable (LoUIS)
The last level of cache that must be cleaned or invalidated when cleaning or invalidating to the point of unification for the Inner Shareable shareability domain. For more information see Terms used in describing the maintenance operations on page B2-1274.

See also Cache level, Point of unification (PoU).

Level of unification, uniprocessor (LoUU)
For a processor, the last level of cache that must be cleaned or invalidated when cleaning or invalidating to the point of unification for that processor. For more information see Terms used in describing the maintenance operations on page B2-1274.

See also Cache level, Point of unification (PoU).

Line
See Cache line.

Little-endian memory
Means that:
• a byte or halfword at a word-aligned address is the least significant byte or halfword  in the word at that address
• a byte at a halfword-aligned address is the least significant byte in the halfword at that address.

Load/Store architecture
An architecture where data-processing operations only operate on register contents, not  directly on memory contents.

LoC
See Level of coherence (LoC).

LoUIS
See Level of unification, Inner Shareable (LoUIS).

LoUU
See Level of unification, uniprocessor (LoUU).

Lockdown
See Cache lockdown.

Low registers
ARM core registers 0 to 7. Unlike the High registers, all Thumb instructions can access the Low registers.
See also High registers.

Memory barrier
See Memory barriers on page A3-151

Memory coherency
The problem of ensuring that when a memory location is read, either by a data read or an instruction fetch, the value actually obtained is always the value that was most recently written to the location. This can be difficult when there are multiple possible physical locations, such as main memory and at least one of a write buffer and one or more levels of cache.

Memory Management Unit (MMU)
Provides detailed control of the part of a memory system that provides a single stage of address translation. Most of the control is provided using translation tables that are held in memory, and define the attributes of different regions of the physical memory map.

Memory Protection Unit (MPU)
A hardware unit whose registers provide simple control of a limited number of protection regions in memory.

Miss
See Cache miss.

Modified Virtual Address (MVA)
The address produced by the FCSE that is sent to the rest of the memory system to be used in place of the normal virtual address. When the FCSE is absent or disabled the MVA and the Virtual Address (VA) have the same value.
From ARMv6, ARM deprecates any use of the FCSE. The FCSE is:
• optional in an ARMv7 implementation that does not include the Multiprocessing Extensions
• obsolete from the introduction of the Multiprocessing Extensions.

MMU
See Memory Management Unit (MMU).

MPU
See Memory Protection Unit (MPU).

Multi-copy atomicity
The form of atomicity described in Multi-copy atomicity on page A3-130.
See also Atomicity, Single-copy atomicity.

MVA
See Modified Virtual Address (MVA).

NaN
Special floating-point values that can be used when neither a numeric value nor an infinity is appropriate. NaNs can be quiet NaNs that propagate through most floating-point operations, or signaling NaNs that cause Invalid Operation floating-point exceptions when used. For more information, see the IEEE 754 standard.

Observer
A processor or mechanism in the system, such as a peripheral device, that can generate reads from or writes to memory.

Offset addressing
Means that the memory address is formed by adding or subtracting an offset to or from the base register value.

OPTIONAL
When applied to a feature of the architecture, OPTIONAL indicates a feature that is not required in an implementation of the ARM architecture:
• If a feature is OPTIONAL and deprecated, this indicates that the feature is being phased out of the architecture. ARM expects such a features to be included in a new implementation only if there is a known backwards-compatibility reason for the inclusion of the feature. A feature that is OPTIONAL and deprecated might not be present in future versions of the architecture.
• A feature that is OPTIONAL but not deprecated is, typically, a feature added to a version of the ARM architecture after the initial release of that version of the architecture. ARM recommends that such features are included in all new implementations of the architecture.
In body text, these meanings of the term OPTIONAL are shown in SMALL CAPITALS.

Note: Do not confuse these ARM-specific uses of OPTIONAL with other uses of optional, where it has its usual meaning. These include:
• Optional arguments in the syntax of many instructions.
• Behavior determined by an implementation choice, for example the optional byte order reversal in an ARMv7-R implementation, where the SCTLR.IE bit indicates the implemented option.

See also Deprecated.

PA
See Physical address (PA).

Physical address (PA)
Identifies a main memory location.
See also Intermediate Physical Address (IPA), Virtual address (VA).

PoC
See Point of coherency (PoC).

PoU
See Point of unification (PoU).

Point of coherency (PoC)
For a particular MVA, the point at which all agents that can access memory are guaranteed to see the same copy of a memory location. For more information see Terms used in describing the maintenance operations on page B2-1274.

Point of unification (PoU)
For a particular processor, the point by which the instruction and data caches and the translation table walks of that processor are guaranteed to see the same copy of a memory location. For more information see Terms used in describing the maintenance operations on page B2-1274.

Post-indexed addressing
Means that the memory address is the base register value, but an offset is added to or subtracted from the base register value and the result is written back to the base register.

Prefetching
Prefetching refers to speculatively fetching instructions or data from the memory system. In particular, instruction prefetching is the process of fetching instructions from memory before the instructions that precede them, in simple sequential execution of the program, have finished executing. Prefetching an instruction does not mean that the instruction has to be executed.
In this manual, references to instruction or data fetching apply also to prefetching, unless the context explicitly indicates otherwise.
Note, in particular, that the Prefetch Abort exception can be generated on any instruction fetch, and is not limited to speculative instruction fetches.
Pre-indexed addressing Means that the memory address is formed in the same way as for offset addressing, but the memory address is also written back to the base register.

Process ID
In the FCSE, this is a 7-bit number that identifies which process block the current process is loaded into.

Protection region
A memory region whose position, size, and other properties are defined by Memory Protection Unit registers.

Protection Unit
See Memory Protection Unit (MPU).

Pseudo-instruction
UAL assembler syntax that assembles to an instruction encoding that is expected to disassemble to a different assembler syntax, and is described in this manual under that other syntax. For example, MOV <Rd>, <Rm>, LSL #<n> is a pseudo-instruction that is expected to disassemble as LSL <Rd>, <Rm>, #<n>.

Quadword
A 128-bit data item. Quadwords are normally at least word-aligned in ARM systems.

Quadword-aligned
Means that the address is divisible by 16.

Quiet NaN
A NaN that propagates unchanged through most floating-point operations.

RAO
See Read-As-One (RAO)

RAZ
See Read-As-Zero (RAZ).

RAO/SBOP
Read-As-One, Should-Be-One-or-Preserved on writes.
Hardware must implement the field as Read-as-One, and must ignore writes to the field.
Software can rely on the field reading as all 1s, but must use an SBOP policy to write to the field.
This description can apply to a single bit that reads as 1, or to a field that reads as all 1s.
See also Read-As-One (RAO), Should-Be-One-or-Preserved (SBOP).

RAO/WI
Read-As-One, Writes Ignored.
Hardware must implement the field as read as Read-as-One, and must ignore writes to the field.
Software can rely on the field reading as all 1s, and on writes being ignored.
This description can apply to a single bit that reads as 1, or to a field that reads as all 1s.

See also Read-As-One (RAO).

RAZ/SBZP

Read-As-Zero, Should-Be-Zero-or-Preserved on writes.
Hardware must implement the field as Read-as-Zero, and must ignore writes to the field.
Software can rely on the field reading as all 0s, but must use an SBZP policy to write to the field.
This description can apply to a single bit that reads as 0, or to a field that reads as all 0s.
See also Read-As-Zero (RAZ), Should-Be-Zero-or-Preserved (SBZP).

RAZ/WI
Read-As-Zero, Writes Ignored.
Hardware must implement the field as Read-as-Zero, and must ignore writes to the field.
Software can rely on the field reading as all 0s, and on writes being ignored.
This description can apply to a single bit that reads as 0, or to a field that reads as all 0s.
See also Read-As-Zero (RAZ).

Read-allocate cache
A cache in which a cache miss on reading data causes a cache line to be allocated into the cache.

Read-As-One (RAO)
Hardware must implement the field as reading as all 1s.
Software can rely on the field reading as all 1s.
This description can apply to a single bit that reads as 1, or to a field that reads as all 1s.

Read-As-Zero (RAZ)
Hardware must implement the field as reading as all 0s.
Software can rely on the field reading as all 0s
This description can apply to a single bit that reads as 0, or to a field that reads as all 0s.

Read, modify, write
In a read, modify, write instruction sequence, a value is read to a general-purpose register, the relevant fields updated in that register, and the new value written back.

Reserved
Unless otherwise stated:
• instructions that are reserved or that access reserved registers have UNPREDICTABLE behavior
• bit positions described as reserved are:
— in an RW register, UNK/SBZP
— in an RO register, UNK
— in a WO register, SBZ.

RISC
Reduced Instruction Set Computer.

Rounding error
The value of the rounded result of an arithmetic operation minus the exact result of the operation.

Rounding mode
Specifies how the exact result of a floating-point operation is rounded to a value that is representable in the destination format.

Round to Nearest (RN) mode
Means that the rounded result is the nearest representable number to the unrounded result.

Round towards Plus Infinity (RP) mode
Means that the rounded result is the nearest representable number that is greater than or equal to the exact result.

Round towards Minus Infinity (RM) mode
Means that the rounded result is the nearest representable number that is less than or equal to the exact result.

Round towards Zero (RZ) mode
Means that results are rounded to the nearest representable number that is no greater in magnitude than the unrounded result.

Saturated arithmetic
Integer arithmetic in which a result that would be greater than the largest representable number is set to the largest representable number, and a result that would be less than the smallest representable number is set to the smallest representable number. Signed saturated arithmetic is often used in DSP algorithms. It contrasts with the normal signed integer arithmetic used in ARM processors, in which overflowing results wrap around from +231–1 to –231 or vice versa.

SBO
See Should-Be-One (SBO).

SBOP
See Should-Be-One-or-Preserved (SBOP).

SBZ
See Should-Be-Zero (SBZ).

SBZP
See Should-Be-Zero-or-Preserved (SBZP).

Security hole
A mechanism by which execution at the current level of privilege can achieve an outcome that cannot be achieved at the current or a lower level of privilege using instructions that are not UNPREDICTABLE. The ARM architecture forbids security holes.

Self-modifying code
Code that writes one or more instructions to memory and then executes them. When using self-modifying code you must use cache maintenance and barrier instructions to ensure synchronization. For more information see Ordering of cache and branch predictor maintenance operations on page B2-1289.

Set
See Cache sets.

Should-Be-One (SBO)
Hardware must ignore writes to the field.

Software should write the field as all 1s. If software writes a value that is not all 1s, it must expect an UNPREDICTABLE result.
This description can apply to a single bit that should be written as 1, or to a field that should be written as all 1s.

Should-Be-One-or-Preserved (SBOP)
The Large Physical Address Extension modifies the definition of SBOP for register bits that are reallocated by the extension, and as a result are SBOP in some but not all contexts. For more information see Meaning of fixed bit values in register bit assignment diagrams on page B3-1466. The generic definition of SBOP given here applies only to bits that are not affected by this modification.
Hardware must ignore writes to the field.

If software has read the field since the processor implementing the field was last reset and initialized, it should preserve the value of the field by writing the value that it previously read from the field. Otherwise, it should write the field as all 1s.
If software writes a value to the field that is not a value previously read for the field and is not all 1s, it must expect an UNPREDICTABLE result.
This description can apply to a single bit that should be written as its preserved value or as 1, or to a field that should be written as its preserved value or as all 1s.

Should-Be-Zero (SBZ)
Hardware must ignore writes to the field.

Software should write the field as all 0s. If software writes a value that is not all 0s, it must expect an UNPREDICTABLE result.
This description can apply to a single bit that should be written as 0, or to a field that should be written as all 0s.

Should-Be-Zero-or-Preserved (SBZP)
The Large Physical Address Extension modifies the definition of SBZP for register bits that are reallocated by the extension, and as a result are SBZP in some but not all contexts. For more information see Meaning of fixed bit values in register bit assignment diagrams on page B3-1466. The generic definition of SBZP given here applies only to bits that are not affected by this modification.
Hardware must ignore writes to the field.

If software has read the field since the processor implementing the field was last reset and initialized, it must preserve the value of the field by writing the value that it previously read from the field. Otherwise, it must write the field as all 0s.
If software writes a value to the field that is not a value previously read for the field and is not all 0s, it must expect an UNPREDICTABLE result.

This description can apply to a single bit that should be written as its preserved value or as 0, or to a field that should be written as its preserved value or as all 0s.

Signaling NaNs
Cause an Invalid Operation exception whenever any floating-point operation receives a signaling NaN as an operand. Signaling NaNs can be used in debugging, to track down some uses of uninitialized variables.

Signed immediate and offset fields
Are encoded in two’s complement notation unless otherwise stated.

SIMD Single-Instruction, Multiple-Data.
The SIMD instructions in the ARMv7 architecture are:
• The instructions summarized in Parallel addition and subtraction instructions on page A4-171.
• the Advanced SIMD instructions summarized in Chapter A7 Advanced SIMD and Floating-point
Instruction Encoding, when operating on vectors.

Note :
In ARMv7, some VFP instructions can operate on vectors. However, ARM deprecates those instruction uses, and strongly recommends that Advanced SIMD instructions are always used for vector operations.

Simple sequential execution
The behavior of an implementation that fetches, decodes and completely executes each instruction before proceeding to the next instruction. Such an implementation performs no speculative accesses to memory, including to instruction memory. The implementation does not pipeline any phase of execution. In practice, this is the theoretical execution model that the architecture is based on, and ARM does not expect this model to correspond to a realistic implementation of the architecture.

Single-copy atomicity
The form of atomicity described in Single-copy atomicity on page A3-128.
See also Atomicity, Multi-copy atomicity.

Single-precision value
A 32-bit word that is interpreted as a basic single-precision floating-point number according to the IEEE 754 standard.
Spatial locality The observed effect that after a program has accessed a memory location, it is likely to also access nearby memory locations in the near future. Caches with multi-word cache lines exploit this effect to improve performance.

SUBARCHITECTURE DEFINED
Means that the behavior is expected to be specified by a subarchitecture definition. This definition might be shared by multiple implementations, but it must not be relied on by architecturally-portable software.
In this manual, subarchitecture definitions are used for:
• the interface between a VFP implementation and its support code
• the interface between an implementation of the Jazelle extension and an Enabled JVM.
In body text, the term SUBARCHITECTURE DEFINED is shown in SMALL CAPITALS.

Temporal locality
The observed effect that after a program has accesses a memory location, it is likely to access the same memory location again in the near future. Caches exploit this effect to improve performance.

Thumb instruction
One or two halfwords that specify an operation for a processor in Thumb state to perform. Thumb instructions must be halfword-aligned.

TLB
See Translation Lookaside Buffer (TLB).

TLB lockdown
A way to prevent specific translation table walk results being accessed. This ensures that accesses to the associated memory areas never cause a translation table walk.

Translation Lookaside Buffer (TLB)
A memory structure containing the results of translation table walks. They help to reduce the average cost of a memory access. Usually, there is a TLB for each memory interface of the ARM implementation.

Translation table
A table held in memory that defines the properties of memory areas of various sizes from 1KB to 1MB.

Translation table walk
The process of doing a full translation table lookup. It is performed automatically by hardware.
Trap enable bits In VFPv2, VFPv3U, and VFPv4U, determine whether trapped or untrapped exception handling is selected. If trapped exception handling is selected, the way it is carried out is IMPLEMENTATION DEFINED.
Unaligned An unaligned access is an access where the address of the access is not aligned to the size of an element of the access.

Unaligned memory accesses
Are memory accesses that are not, or might not be, appropriately halfword-aligned, word-aligned, or doubleword-aligned.

Unallocated
Except where otherwise stated, an instruction encoding is unallocated if the architecture does not assign a specific function to the entire bit pattern of the instruction, but instead describes it as UNDEFINED, UNPREDICTABLE, or an unallocated hint instruction.
A bit in a register is unallocated if the architecture does not assign a function to that bit.

UNDEFINED
Indicates an instruction that generates an Undefined Instruction exception.
In body text, the term UNDEFINED is shown in SMALL CAPITALS.
See also Undefined Instruction exception on page B1-1206.

Unified cache
Is a cache used for both processing instruction fetches and processing data loads and stores.

Unindexed addressing
Means addressing in which the base register value is used directly as the virtual address to send to memory, without adding or subtracting an offset. In most types of load/store instruction, unindexed addressing is performed by using offset addressing with an immediate offset of 0. The LDC, LDC2, STC, and STC2 instructions have an explicit unindexed addressing mode that permits the offset field in the instruction to specify additional coprocessor options.
UNK An abbreviation indicating that software must treat a field as containing an UNKNOWN value.
Hardware must implement the bit as read as 0, or all 0s for a bit field. Software must not rely on the field reading as zero.
See also UNKNOWN.

UNK/SBOP
Hardware must implement the field as Read-As-One, and must ignore writes to the field.
Software must not rely on the field reading as all 1s, and except for writing back to the register it must treat the value as if it is UNKNOWN. Software must use an SBOP policy to write to the field.
This description can apply to a single bit that should be written as its preserved value or as 1, or to a field that should be written as its preserved value or as all 1s.
See also Read-As-One (RAO), Should-Be-One-or-Preserved (SBOP), UNKNOWN.

UNK/SBZP
Hardware must implement the bit as Read-As-Zero, and must ignore writes to the field.
Software must not rely on the field reading as all 0s, and except for writing back to the register must treat the value as if it is UNKNOWN. Software must use an SBZP policy to write to the field.
This description can apply to a single bit that should be written as its preserved value or as 0, or to a field that should be written as its preserved value or as all 0s.
See also Read-As-Zero (RAZ), Should-Be-Zero-or-Preserved (SBZP), UNKNOWN.

UNKNOWN
An UNKNOWN value does not contain valid data, and can vary from moment to moment, instruction to instruction, and implementation to implementation. An UNKNOWN value must not return information that cannot be accessed at the current or a lower level of privilege using instructions that are not UNPREDICTABLE and do not return UNKNOWN values.
An UNKNOWN value must not be documented or promoted as having a defined value or effect.
In body text, the term UNKNOWN is shown in SMALL CAPITALS.
See also UNK.

UNPREDICTABLE
Means the behavior cannot be relied upon. UNPREDICTABLE behavior must not perform any function that cannot be performed at the current or a lower level of privilege using instructions that are not UNPREDICTABLE.
UNPREDICTABLE behavior must not be documented or promoted as having a defined effect.
An instruction that is UNPREDICTABLE can be implemented as UNDEFINED.
In an implementation that includes the Virtualization Extensions, execution in a Non-secure PL1 or PL0 mode of an instruction that is UNPREDICTABLE can be implemented as generating a Hyp Trap exception, provided that at least one instruction that is not UNPREDICTABLE causes a Hyp Trap exception.
In body text, the term UNPREDICTABLE is shown in SMALL CAPITALS.

VA See Virtual address (VA).
VFP A coprocessor extension to the ARM architecture, that provides single-precision and double-precision floating-point arithmetic.

Virtual address (VA)
An address generated by an ARM processor. For a PMSA implementation, the virtual address is identical to the physical address.
See also Intermediate Physical Address (IPA), Physical address (PA).

Watchpoint
A debug event triggered by an access to memory, specified in terms of the address of the location in memory being accessed.

Way
See Cache way.

Word
A 32-bit data item. Words are normally word-aligned in ARM systems.

Word-aligned
Means that the address is divisible by 4.

Write-allocate cache
A cache in which a cache miss on storing data causes a cache line to be allocated into the cache.

Write-back cache
A cache in which when a cache hit occurs on a store access, the data is only written to the cache. Data in the cache can therefore be more up-to-date than data in main memory. Any such data is written back to main memory when the cache line is cleaned or reallocated. Another common term for a write-back cache is a copy-back cache.

Write-through cache
A cache in which when a cache hit occurs on a store access, the data is written both to the cache and to main memory.
This is normally done via a write buffer, to avoid slowing down the processor.
Write buffer A block of high-speed memory that optimizes stores to main memory.