基于BASYS2的VHDL程序——数字钟

在编电子表时发现FPGA求余，取模只能针对2的次方。毕竟是数字的嘛！

时钟用到了动态刷新数码管。以一个大于50Hz的速度刷新每一个数码管。

因为数码管只有四个，只写了分针和秒针。

代码如下：

 library IEEE;
 use IEEE.STD_LOGIC_1164.ALL;
 use IEEE.STD_LOGIC_ARITH.ALL;
 use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
 entity clock is
     Port ( clk : in  STD_LOGIC;
            seg : out  STD_LOGIC_VECTOR ( downto );
            an : out  STD_LOGIC_VECTOR ( downto ));
 end clock;
 
 architecture Behavioral of clock is
 signal num:STD_LOGIC_VECTOR ( downto );
 signal min_h:STD_LOGIC_VECTOR ( downto );
 signal min_l:STD_LOGIC_VECTOR ( downto );
 signal second_h:STD_LOGIC_VECTOR ( downto );
 signal second_l:STD_LOGIC_VECTOR ( downto );
 signal an_sel:STD_LOGIC_VECTOR ( downto );
 signal cnt:   INTEGER;
 signal cnt2:  INTEGER;
 signal sclk: STD_LOGIC;
 constant a:integer :=;
 begin
 process(clk)
 begin
 if(clk'event and clk='') then
     if(cnt=) then
         cnt<=;
         sclk<=not sclk;
     else
         cnt<=cnt+;
     end if;
 end if;
 end process;
 
 process(clk)
 begin
 if(clk'event and clk='') then
     if(cnt2=) then
         cnt2<=;
         if(an_sel="") then
             an_sel<="";
         else
             an_sel<=an_sel+'';
         end if;
     else
         cnt2<=cnt2+;
     end if;
 end if;
 end process;
 
 process(sclk)
 begin
 if(sclk'event and sclk='') then
     if(second_h="" and second_l="") then
         second_h<="";
         second_l<="";
         min_l<=min_l+'';
         if(min_h="" and min_l="") then
             min_h<="";
             min_l<="";
         elsif(min_l="") then
             min_h<=min_h+'';
             min_l<="";
         end if;
     elsif(second_l="") then
         second_h<=second_h+'';
         second_l<="";
     else
         second_l<=second_l+'';
     end if;
 end if;
 end process;
 
 process(an_sel,second_l,second_h,min_l,min_h)
 begin
 case an_sel is
 when ""=>an<="";num<=second_l;
 when ""=>an<="";num<=second_h;
 when ""=>an<="";num<=min_l;
 when ""=>an<="";num<=min_h;
 when others=>null;
 end case;
 
 case num  is
         when x""=>seg<=b"";
         when x""=>seg<=b"";
         when x""=>seg<=b"";
         when x""=>seg<=b"";
         when x""=>seg<=b"";
         when x""=>seg<=b"";
         when x""=>seg<=b"";
         when x""=>seg<=b"";
         when x""=>seg<=b"";
         when x""=>seg<=b"";
         when others=>null;
 end case;
 end process;
 end Behavioral;

约束文件如下：

 NET "clk" LOC = "B8";
 NET "an<0>" LOC="K14";
 NET "an<1>" LOC="M13";
 NET "an<2>" LOC="J12";
 NET "an<3>" LOC="F12";
 NET "seg<6>" LOC="L14";
 NET "seg<5>" LOC="H12";
 NET "seg<4>" LOC="N14";
 NET "seg<3>" LOC="N11";
 NET "seg<2>" LOC="P12";
 NET "seg<1>" LOC="L13";
 NET "seg<0>" LOC="M12";