mul16

设计思想：乘法运算本身就可以看做是一个移位相加的过程
               1 1 0 1 0     = 26
*              1 0 1 1 1    = 23                  
   -----------------------------       23*26 = 598
               1 1 0 1 0
            1 1 0 1 0
         1 1 0 1 0
      0 0 0 0 0
  1 1  0 1 0
----------------------------
10 0 1  0 1 0 1 1 0        = 598

核心是这个操作
                   result_reg <= {  {   ( 16 - clock_counter ){1'd0}},                         // 31 - (clock_counter+14) -1
                                             {   result_reg[clock_counter+14 : clock_counter-1]  +  a_reg   }, 
                                            {    result_reg[clock_counter-2 : 0]}
                                         };
因为clock_counter <2 的时候，拼接操作 result_reg [clock_counter-2 ： 0] 要成立
       clock_counter>16 的时候，拼接操作{   ( 16 - clock_counter ){1'd0}} 要成立，（中间的那一部分相加是17bit，第31bit不应该补零）
所以要将他们单独拿出来讨论。

就以上思想进行设计，悲剧发生了

 //date :2013/6/16
 //designer :pengxiaoen
 //function : unsigned 16 bit multiplication

 module mul16 (
               clock,reset,
                   a_in,b_in,
                   status_mul16,
                    result_mul16
                   );

 input clock,reset;
 input [:] a_in ,b_in;
 output reg status_mul16;
 output [:]result_mul16;

 reg [:] clock_counter;
 //--------------------------------------------
 always @ (posedge clock or negedge reset)
 if (!reset)
   clock_counter <= 'd0;
 else if(clock_counter == 'd17)
        clock_counter <= 'd0;
       else
         clock_counter <= clock_counter + ;

 //-----------------------------------------------
 always @ (posedge clock or negedge reset)
 if(!reset)
   status_mul16 <= 'd0;
 else if (clock_counter == 'd17)
   status_mul16 <= 'd1;
        else status_mul16 <= 'd0;  

 reg [:] result_reg;
 reg [:] a_reg,b_reg;
 //------------------------------------------------
 always @ (posedge clock or negedge reset)
 if (!reset)
    begin
         a_reg <= 'd0;
          b_reg <= 'd0;
          result_reg <= 'd0;
     end
 else if (clock_counter == 'd0)
          begin
                 a_reg <= a_in;
                  b_reg <= b_in;
           end
         else  if ((clock_counter >= 'd1) && (clock_counter <= 5'd16))
                  begin
                           if(b_reg [clock_counter -])
                                if(clock_counter == 'd1)
                                     result_reg <= result_reg + a_reg;
                                  else if ((clock_counter >= 'd2)  &  (clock_counter <= 5'd15))
                                      result_reg <= {{( - clock_counter ){'d0}},       // 31 - (clock_counter+14) -1
                                                     {result_reg[clock_counter+ : clock_counter-]  +  a_reg},
                                                           {result_reg[clock_counter- : ]}
                                                          };
                                        else if(clock_counter == 'd16)
                                                 result_reg <= {result_reg[:] + a_reg,  result_reg[:]};
                             else result_reg <= result_reg << ;
                    end  

 assign result_mul16 = result_reg;

 endmodule 

编译产生的结果是：

因为错误提示是因为这个{ } 内部只能是常数，这个是因为语法约束导致的设计失败，那么我很想知道如果我采用门级建模是不是就避开了这个语法约束而实现呢？，但是门级建模，哎，头痛并且浩大的工作量啊。现在懒，不想搞门级建模
修正中..................

 //date :2013/6/17
 //designer :pengxiaoen
 //function : unsigned 16 bit multiplication 

 module mul16 (
               clock,reset,
                   a_in,b_in,
                   data_in_en,        //1 :data input enable   0:data input unenable
                   status_mul16,  //1 :finish.   0:calculating
                   result_mul16
                   );

 input clock,reset;
 input [:] a_in ,b_in;
 output reg data_in_en;
 output reg status_mul16;
 output [:]result_mul16;

 reg [:] clock_counter;
 //--------------------------------------------
 always @ (posedge clock or negedge reset)
 if (!reset)
   clock_counter <= 'd0;
 else if(clock_counter >= 'd17)
        clock_counter <= 'd0;
       else
         clock_counter <= clock_counter + ;

 //-----------------------------------------------
 always @ (posedge clock or negedge reset)
 if(!reset)
     begin
          status_mul16 <= 'd0;
           data_in_en   <= 'd0;
      end 

 else case (clock_counter)
                  : data_in_en <= 'd1;
                    : status_mul16 <= 'd1;
             default  : begin
                            data_in_en<= 'd0;
                                 status_mul16 <= 'd0;
                        end
       endcase 

 reg [:] result_reg;
 reg [:] a_reg,b_reg;
 //------------------------------------------------
 always @ (posedge clock or negedge reset)
 if (!reset)
    begin
         a_reg <= 'd0;
          b_reg <= 'd0;
          result_reg <= 'd0;
     end
 else if (clock_counter == 'd0)
          begin
                 a_reg <= a_in;
                  b_reg <= b_in;
           end
         else  if ((clock_counter >= 'd1) && (clock_counter <= 5'd15))
                  begin
                          if(b_reg[clock_counter -])
                               result_reg <= {'b0,
                                                result_reg [:] + a_reg,
                                                     result_reg [:]
                                                     };
                           else result_reg <= result_reg >> ;
                    end
                 else if ((b_reg[])  &&  (clock_counter == 'd16))
                          result_reg [: ]  <= {result_reg [: ]  +  a_reg};

 assign result_mul16 = result_reg;

 endmodule 

计算精华部分

         else  if ((clock_counter >= 'd1) && (clock_counter <= 5'd15))
                  begin
                          if(b_reg[clock_counter -])
                               result_reg <= {'b0,
                                                result_reg [:] + a_reg,
                                                     result_reg [:]
                                                     };
                           else result_reg <= result_reg >> ;
                    end
                 else if ((b_reg[])  &&  (clock_counter == 'd16))
                          result_reg [: ]  <= {result_reg [: ]  +  a_reg};

先运算reg中的[30:15] 部分，相加运算之后右移。最后第一个bit不就右移到最后去了嘛，为什么我当时就一定要在低位相加呢，不能倒过来呢，嘿嘿。自己愚钝了。

如果b_reg的当前bit是0 只需要右移
最后一个bit不需要移动，直接加到最高的 [31 ：16 ] 就可以了。