基于BASYS2的VHDL程序——交通灯

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数电实验交通灯VHDL版，程序写的扩展性很差，待以后有时间进行优化。

程序如下：

 library IEEE;
 use IEEE.STD_LOGIC_1164.ALL;
 use IEEE.STD_LOGIC_ARITH.ALL;
 use IEEE.STD_LOGIC_UNSIGNED.ALL;
 entity main is
     Port ( clk : in  STD_LOGIC;
            rst : in  STD_LOGIC;
            led : out  STD_LOGIC_VECTOR ( downto );
            an : out  STD_LOGIC_VECTOR ( downto );
            seg : out  STD_LOGIC_VECTOR ( downto ));
 end main;
 
 architecture Behavioral of main is
 signal sclk: std_logic;
 signal cnt0:integer:=;
 signal cnt1:integer:=;
 signal cnt2:integer:=;
 signal cnt3:integer:=;
 signal disp1:integer:=;
 signal disp2:integer:=;
 signal display:integer;
 signal num1:integer;
 signal num1_l:integer;
 signal num1_h:integer;
 signal num2:integer;
 signal num2_l:integer;
 signal num2_h:integer;
 signal ledt: std_logic_vector ( downto );
 signal an_sel: integer;
 begin
 led()<=ledt();
 led()<=ledt();
 led()<=ledt();
 led()<=ledt();
 led()<=ledt();
 led()<=ledt();
 process(clk)
 begin
     if(clk'event and clk='') then
         if(cnt0=)then
             cnt0<=;
             sclk<=not sclk;
         else
             cnt0<=cnt0+;
         end if;
     end if;
 end process;
 
 process(clk)
 begin
 if(clk'event and clk='') then
     if(cnt2=) then
         cnt2<=;
           if(an_sel=)then
                 an_sel<=;
           else
                 an_sel<=an_sel+;
           end if;
     else
         cnt2<=cnt2+;
     end if;
 end if;
 end process;
 
 process(rst,sclk)
 begin
     if(rst='') then
             ledt()<='';
             ledt()<='';
             ledt()<='';
     elsif(sclk'event and sclk='') then
         cnt1<=cnt1+;
         cnt3<=cnt3+;
         if(cnt1>= and cnt1<=)then
             ledt()<='';
             ledt()<='';
             ledt()<='';
         elsif(cnt1>= and cnt1<=)then
             ledt()<='';
             ledt()<='';
             ledt()<='';
         elsif(cnt1=)then
             ledt()<='';
             ledt()<='';
             ledt()<='';
         elsif(cnt1=)then
             cnt1<=;
         end if;
         if(cnt3>= and cnt3<=)then
             ledt()<='';
             ledt()<='';
             ledt()<='';
         elsif(cnt3>= and cnt3<=)then
             ledt()<='';
             ledt()<='';
             ledt()<='';
         elsif(cnt3=)then
             ledt()<='';
             ledt()<='';
             ledt()<='';
         elsif(cnt3=)then
             cnt3<=;
         end if;
     end if;
 end process;
 
 process(sclk,ledt,rst)
 begin
 if (rst='')then
         disp1<=;
         disp2<=;
     elsif(sclk'event and sclk='') then
         if(ledt()='' or ledt()='' or ledt()='')then
             if(ledt()='' and disp1=)then
                 disp1<=;
             elsif(ledt()='' and disp1=)then
                 disp1<=;
             elsif(ledt()='' and disp1=)then
                 disp1<=;
             else
                 disp1<=disp1 + ;
             end if;
         end if;
         if(ledt()='' or ledt()='' or ledt()='')then
             if(ledt()='' and disp2=)then
                 disp2<=;
             elsif(ledt()='' and disp2=)then
                 disp2<=;
             elsif(ledt()='' and disp2=)then
                 disp2<=;
             else
                 disp2<=disp2 + ;
             end if;
         end if;
     end if;
 end process;
 
 process(an_sel)
 begin
     num1<=-disp1;
     if(num1>=)then
         num1_h<=;
         num1_l<=num1-;
     else
         num1_h<=;
         num1_l<=num1;
     end if;
         num2<=-disp2;
     if(num2>=)then
         num2_h<=;
         num2_l<=num2-;
     else
         num2_h<=;
         num2_l<=num2;
     end if;
 case an_sel is
         when =>an<="";display<=num1_l;
         when =>an<="";display<=num1_h;
         when =>an<="";display<=num2_l;
         when =>an<="";display<=num2_h;
         when others=>null;
 end case;
 case display is
           when =>seg<=b"";
           when =>seg<=b"";
           when =>seg<=b"";
           when =>seg<=b"";
           when =>seg<=b"";
           when =>seg<=b"";
           when =>seg<=b"";
           when =>seg<=b"";
           when =>seg<=b"";
           when =>seg<=b"";
           when others=>null;
 end case;
 end process;
 end Behavioral;

约束文件

NET "clk" LOC = "B8";
NET "led<0>" LOC = "M5";
NET "led<1>" LOC = "M11";
NET "led<2>" LOC = "P7";
NET "led<3>" LOC = "P6";
NET "led<4>" LOC = "N5";
NET "led<5>" LOC = "N4";
NET "an<0>" LOC="F12";
NET "an<1>" LOC="J12";
NET "an<2>" LOC="M13";
NET "an<3>" LOC="K14";
#NET "seg<7>" LOC="N13";
NET "seg<6>" LOC="L14";
NET "seg<5>" LOC="H12";
NET "seg<4>" LOC="N14";
NET "seg<3>" LOC="N11";
NET "seg<2>" LOC="P12";
NET "seg<1>" LOC="L13";
NET "seg<0>" LOC="M12";
NET "rst" LOC="P11";