I2C controller core之Bit controller(02)

4　　generate clock and control signals

 1 -- architecture
 signal iscl_oen, isda_oen   : std_logic;             -- internal I2C lines
 signal sda_chk              : std_logic;             -- check SDA status (multi-master arbitration)
 signal dscl_oen             : std_logic;             -- delayed scl_oen signals
 signal sSCL, sSDA           : std_logic;             -- synchronized SCL and SDA inputs
 signal dSCL, dSDA           : std_logic;             -- delayed versions ofsSCL and sSDA
 signal clk_en               : std_logic;             -- statemachine clock enable
 signal scl_sync, slave_wait : std_logic;             -- clock generation signals
 signal ial                  : std_logic;             -- internal arbitration lost signal
 signal cnt                  : unsigned( downto ); -- clock divider counter (synthesis)

12 -- whenever the slave is not ready it can delay the cycle by pulling SCL low
13 -- delay scl_oen
 process (clk, nRst)
 begin
     if (nRst = '') then
         dscl_oen <= '';
     elsif (clk'event and clk = '') then
         dscl_oen <= iscl_oen;
     end if;
 end process;

23 -- slave_wait is asserted when master wants to drive SCL high, but the slave pulls it low
24 -- slave_wait remains asserted until the slave releases SCL
 process (clk, nRst)
 begin
     if (nRst = '') then
         slave_wait <= '';
     elsif (clk'event and clk = '') then
         slave_wait <= (iscl_oen and not dscl_oen and not sSCL) or (slave_wait and not sSCL);
     end if;
 end process;

34 -- master drives SCL high, but another master pulls it low
35 -- master start counting down its low cycle now (clock synchronization)
 scl_sync <= dSCL and not sSCL and iscl_oen;

38 -- generate clk enable signal
 gen_clken: process(clk, nRst)
 begin
     if (nRst = '') then
         cnt    <= (others => '');
         clk_en <= '';
     elsif (clk'event and clk = '') then
            if ((rst = '') or (cnt = ) or (ena = '') or (scl_sync = '')) then
                cnt    <= clk_cnt;
                clk_en <= '';
            elsif (slave_wait = '') then
                cnt    <= cnt;
                clk_en <= '';
            else
                cnt    <= cnt -;
                clk_en <= '';
            end if;
     end if;
 end process gen_clken;