verilog FAQ(zz)

1. What is the race condition in verilog?

Ans :The situation when two expressions are allowed to execute at same instance of time without mentioning the order of execution.

2. List the levels of abstraction in verilog?

Ans : 1. Behavioral level 2. Register-Transfer level 3. Gate level 4. Switch levels

3. Which are the two types of design methodologies?

Ans : Top down and Bottom up

4. Num = 'bX; What will be the value of Num?

Ans : 8'bxxxx_xxxx

5. What are the differences between wire and register?

Ans : Wire just transfer input to output, Register stores the value as a variable until or unless another value replaces it.

6. What are the differences between logical AND and reduction AND?

Ans : Reduction and takes one operand and perform a bit by next bit operation.

7. What is the difference between swapping the contents of two registers with temp register and without temp register?

Ans : We use temp register in case of blocking statements to swap the registers contents. We wont use temp register for non blocking          statements.

8. How logical shift differs from arithmetic shift?

Ans : In logical shift the MSB will be accumulated by zero's In arithmetic shift MSB will be accumulated by sign bit.

9. What is the conditional operator and how it is used?

Ans : Operator which assigns any one variable out of two by evaluating the expression mentioned in that operator. Syntax : cond_expr?          true_expr:false_expr

10. What is the difference between “==” and “===”?

Ans : “==” it is logical equality.
“===” it is case equality.

11. What exactly expression reg[8*13:1]
string_val; signifies?

Ans : Reg can hold up to 13
characters.

12. When output port is generated by a
submodule what will be the type of output
a. register
   b.
wire

Ans : b

13. List the built in
primitives?

Ans : gates, transmission gates and
switches.

14. Name the two possible ways by which we
can instantiate the modules?

Ans : Port order connection and Port name
connection.

15. Which assignment statement we usually
use in dataflow modeling?

Ans : A continuous assignment
statement.

16. What are rise delay and turn off
delays?

Ans :The rise delay is associated with a
gate output transition to 1 from another value(0,x,z).
Turn off delay associated with a gate transition to Z from value
(0,1,x).

17. What is inter delay? explain with an
example

Ans : Delay where command waits for
particular time steps before executing that command.
ex: #10 a=b+c;

18. What is intra delay? explain with an
example

Ans : Here the evaluated expression waits
for specified time to assign value to LHS.
ex : a = #10 b+c;

19. What are the difference between inter
and intra delays?

Ans : Inter delay simply wait for
appropriate no of time steps before executing the command.
ex : #10 q = x + y;
Intra delay wait for appropriate no of time steps before assignment
of RHS to LHS.
ex : q = #10 x + y;

20. Which is the stable one in the
following
a. #10 q=x+y;
   b. q= #10
x+y;

Ans : b

21. What are the differences between
continuous and procedural assignments?

Ans : Difference between continuous and
procedural assignments.
Continuous assignments procedural assignments
1 Assigns primarily to net Assigns primarily to reg
2 Values continuously drive to out put Values will be stored into
variables
3 Occurs in assignments to wire,port and net Occurs in constructs
like always,initial,task,function.

22. What are the differences between
assignment in initial and always blocks?

Ans : Assignment in initial Assignment in
always
1. Execute from time 0 in simulation and proceed in the specified
sequence. This also begin from time 0, and repeat forever as a
function
           of
the changes on sensitivity list.
2. Execution stops when the end of the block is reached. Execution
continuously repeats according to the change in values of
sensitivity
           list.

3. Non-synthasizable Synthasizable

23. What are the differences between
blocking and non blocking statements?

Ans : Blocking Non blocking
1. The evaluation of the expression of the RHS is updated to LHS
autonomously based on delay. But here RHS will not be updated to
LHS
           immediately

2. In case of multiple blocking assignments the trailing
assignments are blocked. Multiple blocking assignments can be
scheduled to occur
           concurrently
on next evaluation cycle.
3. There is a possibility of race condition in this. Race condition
can be avoided.
4 Represented by “=” operator sign between LHS and RHS. Represented
by “< =”operator sign between LHS and
RHS.

24. What are the differences between Task
and Functions?

Ans : Task Function
1. Can contain time control statements like @(posedge). Executes in
zero simulation time.
2. Can call any number of function or tasks. Can call any number of
functions but not tasks.
3. Cannot return any value when called instead the task can have
output arguments. It can return any value when called.

25. How re-entrant task,function differs
from static task,functions ?

Ans : Re-entrant task,functions have a key
word automatic between task and name of the task which replicates
and allocates the variables. But
         it
is not possible in static.

26. How we can convert static task and
function to re-entrant task and function?

Ans : By adding key word automatic between
task and name of the task.

27. What is an effect of keyword automatic
for re-entrant task?

Ans : It replicates the variables and
allocates the variables in task.

28. What is an fork--join exactly
mean?

Ans : fork--join groups two or more
statements together in parallel, so that all statements are
evaluated concurrently.

29. Which assignment statement will be
used in Behavioral modeling?

Ans : Procedural assignment
statements.

30. Always and initial blocks are called
______ blocks.

Ans : Procedural

31. What is sensitivity list?

Ans : It is an event timing control that
controls when all statements in the procedural block will start to
be evaluated.

32. What are procedural assignment
statements?

Ans : The statements within a procedure
which executes sequentially.

33. How we can avoid race
condition?

Ans : By using non blocking
statements.

34. How we can represent a blocking and
non blocking assignments?

Ans : Blocking can be represented by
wire.
Non blocking can be represented by latch.

35. List process synchronization supported
by verilog?

Ans : event, fork and join,
disable.

36. What actually event does?

Ans : It suspends the process until
specified event to occur.

37. What wait does actually?

Ans : It suspends the process until
expression become true.

38. What forever loop does?

Ans : this loop executes continuously and
never completes until you break it intentionally.

39. When generate statements are
used?

Ans : Generate statements are used when
the same operation or module instance is repeated for multiple bits
of vector.

40. List out the different methods to
create generate statement?

Ans : Generate loop, Generate conditional,
Generate case.

41. Which are the two types of UDP's in
verilog?

Ans : 1. Combinational UDP
2. Sequential UDP

42. Why RTL synthesis is
important?

Ans : It is important to improve designers
productivity to meet today's design complexity.

43. What is the difference between always
with @ and always without @?

Ans : The only difference is always with @
can be synthesized but not other one.
The always without @ will be used only in test benches.

44. What is the difference between
$display and $monitor?

Ans : $display display its parameter
whenever that is executed. $monitor display its parameter whenever
the value of parameter changes.

45. Write a code for 2:1 Mux?

Ans : assign mux_out = (sel)? din_1 :
din_0;

46. Write a Verilog code which divides the
clock by 2?

Ans : always @ (posedge clk_in)
if (reset)
clk_out <= 1'b0;
else
clk_out <= ! clk_out ;

47. Write a code which converts 4 bit
binary to gray code?

Ans : assign out = { binary[3]),(binary[3]
^ binary[2]), (binary[2] ^
binary[1]),(binary[1] ^ binary[0])
};

48. Write a code for one hot
counter?

Ans : always @ (posedge clk)
if (reset)
out <= 8'b0000_0001 ;
else if (enable)
out <= {out[6],out[5],out[4],out[3],
out[2],out[1],out[0],out[7]};

49. Write a code for 16 bit
counter?

Ans : always @(posedge clk)
if (reset)
out <= 16'b0 ;
else if (enable)
out <= out + 1;

50. Write a code for 8 bit parity
checker?

Ans : assign parity_out = ^data_in; //
data_in is 8 bits

51. Write a code for 8 bit shift-left
register?

Ans : always @(posedge Clock)
begin
register <= register
<< 1;
register[0] <= Input;
end
assign output = register[7];

52. Write a code for 8 bit Unsigned
adder?

Ans : assign {Carry_Out,SUM} = input_A +
input_B + Carry_In;

53. Write a code for
comparator?

Ans : assign out = (in_1 >=
in_2)? 1'b1:1'b0;

54. When we use FSMs?

Ans : FSMs are widely used in applications
that require prescribed sequential activity.

55. Difference between `define and
parameter?

Ans : Define Parameter only one constant
with the same name can exist in the whole scope multiple modules
can have same parameter name cannot be
overridden can be overridden used to specify macro used to specify
constants

56. What value is inferred when multiple
procedural assignments made to the same reg variable in an always
block?

Ans : When there are multiple nonblocking
assignments made to the same reg variable in a sequential always
block, then the last assignment is picked up
for logic synthesis.

57. What are “snake” paths?

Ans : A snake path, as the name suggests
is a path that traverses through a number of hierarchies, and may
eventually return back to the same hierarchy
from which it originated.

58. What is “constant propagation”? How
can I use constant propagation to minimize area?

Ans : Constant propagation is a very
effective technique for area minimization, since it forces the
synthesis tools to optimize the logic in both forward and backward directions. Since the area
minimization is achieved using constants, this technique is called
constant propagation.

59. What happens to the bits of a reg
which are declared, but not assigned or used?

Ans : When any of the bits of a reg
declaration is unused, the logic corresponding to those bits gets
optimized

60. Why we use `ifdef and generate for in
verilog?

Ans : Both `ifdef and generate constructs
can be used for the purpose of area minimization.

61. What is the difference between using
`ifdef and generate?

Ans : `ifdef generate we can use it inside
the module as well as outside the module we can only use it inside
the module works on the boolean presence or
absence of `define of the `ifdef variable use the value of a
variable using genvar, can be used inside loops used only in
if-else and cannot perform any looping operation the genvar
variable can be used inside for loop or case
statements

62. What is “retime” logic between
registers?

Ans : Retiming is the process of
relocating registers across logic gates, without affecting the
underlying combinatorial logic structure. This process is achieved by borrowing logic from one time
frame and lending it to the other, while maintaining the design
behavior.

63. Why one-hot encoding is preferred for
FSMs?

Ans : Since there is one explicit FF per
stage of a one-hot encoded state machine, there is no need of
output state decoding. Hence, the only anticipated delay is the clock to q delay of the FF.
This makes the one-hot encoding mechanism preferable for high-speed
operation.

64. What are the main factors that affect
testability of a design?

Ans : Reset of a FF driven by the output
of another FF Presence of tri-state buses in
the design Presence of derived clocks in the design Presence of
gated clocks in the design Presence of latches in the
design

65. What are the various methods to reduce
power during RTL coding?

Ans : Reduce switching of the data input
to the Flip-Flops. Reduce the clock
switching of the Flip-Flops. Have area reduction techniques within
the chip, since the number of gates/Flip-Flops that toggle can be
reduced.

66. What is the advantage of using
hierarchical names to refer to Verilog objects?

Ans : It is easy to debug the internal
signals of a design, especially if they are not a part of the top
level pinout.

67. What are the disadvantages of using
hierarchical name to refer to Verilog objects?

Ans : During synthesis, these hierarchical
names get ungrouped or dissolved or renamed, depending upon the
synthesis strategy and switches used, and
hence, will cease to exist. In that case, special switches need to
be added to the synthesis compiler commands, in order to maintain
the hierarchical naming. If the Verilog code needs to be translated
into VHDL, the hierarchical names are not
translatable.

68. What is the effect of specifying
delays in assignment’s during synthesis?

Ans : Specifying any kind of delay before
an assignment, or within an assignment, in a blocking or
non-blocking procedural assignment is ignored by synthesis tools. If the functionality depends upon
the presence of the delay, then a mismatch in functional simulation
will be seen between the model and the synthesized netlist. Ex:
reg1 = #3 reg2; // #3 will be ignored #6 reg3 <=
reg4; // #6 will be ignored Since the above construct is
syntactically legal, the synthesis tools will issue a WARNING and
not an ERROR.

69. What is the synthesized hardware for
the verilog code below?
module generator_ex1(data, select,
out);
input [0:7] data;
input [0:2] select;
out out;
assign out = data [select];
endmodule

Ans: 8:1 Mux

70. What is the synthesized hardware for
the verilog code below?
module generate_ex2(out,in,select);
input En;
input [0:1] select;
output [0:3] out;
assign out = En? (1 << select) :
4’b0;
endmodule

Ans: 2:4 Decoder

71. How to avoid unintentional latches in
the design?

Ans : Completely specify all branches for
every case and if statement. Completely specify all outputs for
every case and if statement. Use synopsys
full-case if all desired cases have specified.

72. What is a "full" case
statement?

Ans : A "full" case statement is a case
statement in which all possible case-expression binary patterns can
be matched to a case item or to a case default. If case statement does not include a case
default and if it is possible to find a binary case expression that
does not match any of the defined case items, the case statement is
not full.

73. What is a "parallel" case
statement?

Ans : A parallel case statement is a case
statement in which it is only possible to match a case expression
to one and only one case item. If it is possible to find a case expression that would match more
than one case item, the matching case items are called
"overlapping" case items and the case statement is not
parallel.

74. Pros and cons of latch and
Flip-Flop?

Ans : Latch takes less area, consume less
power, facilitate time borrowing or cycle stealing, not friendly
with DFT tools
always @(clk) begin
IF (clk == 1’b1)
q <= d;
end
Flip-flop takes more area, consumes more power, allow synchronous
logic, friendly with DFT tools.
D-Flip-flop:
always @(posedge clk)
begin
if(reset)
q<=1'b0;
else
q <= d;
end

75. Write a verilog code for D flip flop
with Synchronous reset?

Ans : D type flip flop with synchronous
reset
reg q;
always @ (posedge clk)
if (reset)
q <= 1'b0;
else
q <= d;

76. Write a verilog code for D flip flop
with asynchronous Reset?

Ans : D type flip flop with asynchronous
reset
reg q;
always @ (posedge clk or posedge reset)
if (reset)
q <= 1'b0;
else
q <= d;

77. Write a verilog code for D flip flop
with gated clock?

Ans : D type flip flop with gated
clock
reg q;
wire gtd_clk = enable && clk;
always @ (posedge gtd_clk)
q <= d;

78. What are the guidelines for coding
priority encoders?

Ans : Non-parallel case statements infer
priority encoders. It is a poor coding practice to code priority
encoders using case statements. It is better
to code priority encoders using if-else-if statements.
Code all intentional priority encoders using if-else-if statements.
It is easier for a typical design engineer to recognize a priority
encoder when it is coded as an if-else-if statement.
Case statements can be used to create tabular coded parallel logic.
Coding with case statements is recommended when a truth-table-like
structure makes the Verilog code more concise and readable.
Examine all synthesis tool case-statement reports.
Change the case statement code, as outlined in the above coding
guidelines, whenever the synthesis tool reports that the case
statement is not parallel (whenever the synthesis tool reports "no"
for "parallel_case").

79. What are the limitations of using
tri-state logic?

Ans : The presence of internal tri-state
logic is a critical consideration for power sensitive products.
Normally a multiplexer should be used in place of tri-state logic. However, if the tri-state
logic remains in the RTL, it is not an error for compilation.
Synthesis tools sometimes warn the users. The linting tools also
detect this condition, and report this to the
user.

80. What is the effect of specifying a
function without a range?

Ans : If a range is not specified, Verilog
will assume a 1 bit return value. If a multi-bit return value was
calculated in the function, only the least
significant bit is returned.

81.How to selectively enable or disable
monitoring?

Ans : $monitor can be selectively enabled
or disabled by the $monitoron and the $monitoroff system calls,
respectively. The $monitoron and $monitoroff
system calls affect only the most recent call to
$monitor.

82. What is the main limitation of
fork-join in Verilog,

Ans : The main limitation of fork-join
construct in Verilog is that it is static, that is, the execution
of the code beyond the join is suspended until all the processes within the fork-join are
completed.

83. What are the differences and
similarities between the logical (<<,
>>) and the arithmetic
(<<<,
>>>) shift
operators?

Ans : The logical shift operators are
(<< and
>>). The logical shift operator has
been present from Verilog-1995. The arithmetic shift operators are
(<<< and
>>>), which were
introduced with Verilog-2001. Three of them, that is, logical left
shift (<<), arithmetic left shift
(<<<) and logical
shift right(>>) operators, shift the
bits left/right by the number of bit positions specified by the
right operand, and the vacated bits are filled with zeros. The
arithmetic right shift operator
(>>>) will fill the
vacated bits with 0 if the left operand is unsigned, and the most
significant bit if the left operand is signed.

84. What is the difference between the
logical (==) and the case (===) equality operators?

Ans : The “==” are synthesizable while
“===” operators are not synthesizable.

85. What is the difference between
assign-deassign and force-release?

Ans : Force - release can be applicable to
nets and variables, whereas assign - deassign is applicable only to
variables.

86. What is a critical path in a
design?

Ans : There can be more than one critical
path in a design. A critical path is the path through a circuit
that has the least slack. Need not necessarily the longest path in the
design.

87. If there are only inputs and no output
what it will be synthesized?

Ans : A module with only inputs and no
outputs will synthesize into a module with no logic, since there is
nothing to be synthesized as an output.

88. what is the difference between casex
and casez?

Ans : Casex – treats x,z both as don’t
cares.

89. Write a Verilog code for ring
counter?

Ans : module ring_counter(clk,
initial_count, count);
input clk, initial_count;
output reg [7:0] count;
always @ (posedge clk)
begin
if (initial_count)
count = 8’b00000000;
else
count = {count (6:0), count[7]};
endmodule

90. What is `timescale?

Ans : It is compiler directive which
indicates the time unit to be used for delays specified in the
testbench.

91. What are different types of Verilog
simulators?

Ans : Event-based Simulator:
Event base Simulation method sacrifices
performance for rich functionality.
Every active signal is calculated for every device it propagates
through during a clock cycle.
Full timing calculations for all devices and the full HDL
standard.
Cycle Based Simulator:
Cycle based Simulation method eliminates unnecessary calculations
to achieve huge performance gains in verifying Boolean logic.
At the end of every clock cycle results are examined.
The digital logic is the only part of the design simulated. These
simulators are mainly meant for logic verification, no timing
calculations. By limiting these calculations, cycle based
Simulators can provide huge increases in performance over
Event-based simulators.
Static Timing analysis is used to compensate for the lost timing
information coverage.

92. How we can use Verilog function to
define the width of a multi-bit port, wire, or reg type?

Ans : The width elements of ports, wire or
reg declarations require a constant in both MSB and LSB. Before
Verilog 2001, it is a syntax error to
specify a function call to evaluate the value of these widths. For
example, the following code is erroneous before Verilog 2001
version. reg [ port1(val1:vla2) : port2 (val3:val4)] reg1;
Verilog-2001 allows the use of a function call to evaluate the MSB
or LSB of a width declaration.

93. What is alias?

Ans : System Verilog has introduced a
keyword alias, which can be used only on nets to have a two-way
assignment.
module top_alias ();
wire rhs,lhs;
alias lhs=rhs;
In the above verilog code, if LHS changes it reflets to RHS and
similarly if RHS changes it reflects to LHS as
well.

94. What is the difference between: c =
con ? a : b; and if (con) c = a; else c = b;

Ans :The operator (?) gives answers even
if the condition is "x", so for example if con = 1'bx, a = 'b10,
and b = 'b11, it will give c = 'b1x. Whereas “if” treats Xs or Zs as FALSE, so it will return always
c = b.

95. What is scheduling semantics for the
simulation time in Verilog?

Ans : Verilog basically imply a four-level
deep queue for the current simulation time:
Active Events (blocking statements)
Inactive Events (#0 delays, etc)
Non-Blocking Assign Updates (non-blocking statements)
Monitor Events ($display, $monitor, etc).

96. What is PLI?

Ans : Programming Language Interface (PLI)
of Verilog HDL is a mechanism to interface Verilog programs with
programs written in C language. It also
provides mechanism to access internal databases of the simulator
from the C program.

97. List all the system tasks and their
purpose?

Ans : $display – Displays once every time
when they are executed.
$strobe – Displays the parameters at the
very end of the current simulation time rather than exactly where
it is executed.
$monitor – Displays every time when one of its parameter
changes.
$reset – Resets the simulation back to zero.
$stop – Halts the simulator and puts in the interactive mode where
user can enter commands
$finish – Exits simulator back to operating system.
$time, $stime, $realtime – Currenmt simulation time as a 64-bit
integer, 32-bit integer and real number respectively.
$scope (hierarchy_name) – sets the current scope to hierarchy scope
to hierarchy name.
$showscopes – Lists all modules,tasks & block naems
in current scope.
$fopen – Opens an ouput file and gives the open file a handle for
use by the other commands.
fclose – Closes the file and lets the other programs access
it.
$fdisply, $fwrite – Writes formated data to a file when ever they
executed. Both are same except $fdisplay inserts a new line after
every execution and $fwrite does not inserts.
$fstrobe – Writes a file when executed, but waits until all other
operations in the time step are complete before writing.
initilal
# 1 a= 1; b=0;
#fstrobe (file, a,b );
b=1;
Will writes 11 for a and b.
$fmonitor – Writes to a file when ever any argument changes
$dumpfile, $dumpvar, $dumpon, $dumpoff, $dumpall – The dump files
are capable of dumping all the variables in a simulation.
$dumpvar – dumps all the variables in the design.
$dumpvar(1,top) – Dumps all variables in the top and below but not
sub modules.
$dumpvar(2,top) – Dumps all variables in the top and one level
below.
$dumpvar(n,top) – Dumps all variables in the top and n-1 level
below.
$dumpvar(0,top) – Dumps all variables in the top and all levels
below.
$dumpon – Initiates the dump.
$dumpoff - Stops dumping.
$random – Generates radom integer every time when it is
called.

98. What is a netlist?

Ans : Gate level representation of
RTL.

99. How memory is declared in
Verilog?

Ans : Memories are declared as
two-dimensional arrays of registers.
syntax: reg [msb:lsb] identifier
[first_addr:last_addr] ;
Where msb:lsb determine the width (word size) of the memory
first_addr:last_addr determine the depth (address range) of the
memory

100.What are the guidelines for using
functions in Verilog?

Ans : A function cannot advance
simulation-time, using constructs like #, @. etc.
A function should not have nonblocking
assignments.
A function without a range defaults to a one bit reg for the return
value.
It is illegal to declare another object with the same name as the function in the scope where the function is declared