AMBA APB总线

　　前面分析了AHB总线协议。接下来分析APB总线协议。

　　（一） APB总线接口：

　　PCLK APB总线时钟。

　　PRESETn APB总线复位。低有效。

　　PADDR 地址总线。

　　PSELx 从设备选择。

　　PENABLE APB传输选通。

　　PWRITE 高为写传输，低为读。

　　PRDATA 读数据总线。

　　PWDATA 写数据总线。

　　接口信号定义如下：

 interface   apb_slv_intf #(
     parameter   AW  = ,
                 DW  =
 ) (
     input   logic       PCLK,
     input   logic       PRESETn
 );
     logic               PSEL;
     logic               PENABLE;
     logic   [AW-:]    PADDR;
     logic               PWRITE;
     logic   [DW-:]    PWDATA;
 
     logic   [DW-:]    PRDATA;
 
     modport m (
         input   PRDATA,
         output  PSEL, PENABLE, PADDR, PWRITE, PWDATA
     );
 
     modport s (
         input   PSEL, PENABLE, PADDR, PWRITE, PWDATA,
         output  PRDATA
     );
 
 endinterface: apb_slv_intf

　　（二） APB总线时序图：

写传输

读传输

　　注意在PENABLE信号有效后从设备需要给出有效数据/读取有效数据。

　　（三） AHB总线到APB总线转换桥

 module ahb2apb_bridge #(
     parameter   AHB_AW  = ,
                 AHB_DW  = ,
                 APB_AW  = ,
                 APB_DW  = ,
                 NSLV    =
 ) (
     input   logic   HCLK,
     input   logic   HRESETn,
     input   logic   PCLK,
     input   logic   PRESETn,
     ahb_slv_intf.s  ahb,
     apb_slv_intf.m  apbv[NSLV]
 );
 
     logic   ahb_work;
     logic   apb_work;
 
     genvar  i;
 
     typedef enum logic [:] {
         AHB_IDLE    = 'b00,
         AHB_WRITE   = 'b01,
         AHB_READ    = 'b10,
         AHB_WAIT    = 'b11
     } ahb_state_e;
 
     // Signal of AHB Domain
     struct {
         logic                   work;
         logic   [AHB_AW-:]    addr;
         logic   [AHB_DW-:]    data;
         logic                   write;
         ahb_state_e             cstate, nstate;
     } ahbd;
 
     typedef enum logic [:] {
         APB_IDLE    = 'b00,
         APB_WRITE   = 'b01,
         APB_READ    = 'b10
     } apb_state_e;
 
     // Signal of APB Domain
     struct {
         logic                   work;
         logic   [APB_DW-:]    data[NSLV];
         logic                   PSEL[NSLV];
         logic                   PENABLE[NSLV];
         apb_state_e             cstate, nstate;
     } apbd;
 
     // AHB Control Logic
     always_comb begin
         case (ahbd.cstate)
             AHB_IDLE: begin
                 if (ahb.HSEL && ahb.HTRANS == HTRANS_NONSEQ) begin
                     if (ahb.HWRITE)
                         ahbd.nstate = AHB_WRITE;
                     else
                         ahbd.nstate = AHB_READ;
                 end
                 else
                     ahbd.nstate = AHB_IDLE;
             end
             AHB_WRITE: begin
                 if (apbd.work)
                     ahbd.nstate = AHB_WAIT;
                 else
                     ahbd.nstate = AHB_WRITE;
             end
             AHB_READ: begin
                 if (apbd.work)
                     ahbd.nstate = AHB_WAIT;
                 else
                     ahbd.nstate = AHB_READ;
             end
             AHB_WAIT: begin
                 if (!apbd.work)
                     ahbd.nstate = AHB_IDLE;
                 else
                     ahbd.nstate = AHB_WAIT;
             end
             default: ahbd.nstate = AHB_IDLE;
         endcase
     end
 
     always_ff @(posedge HCLK or negedge HRESETn) begin
         if (!HRESETn)
             ahbd.cstate <= AHB_IDLE;
         else
             ahbd.cstate <= ahbd.nstate;
     end
 
     always_ff @(posedge HCLK or negedge HRESETn) begin
         if (!HRESETn) begin
             ahbd.work   <= 'b0;
             ahbd.addr   <= '0;
             ahbd.data   <= '0;
             ahbd.write  <= 'b0;
             ahb.HREADY  <= 'b1;
             ahb.HRDATA[APB_DW-:]  <= '0;
         end
         else begin
             case (ahbd.cstate)
                 AHB_IDLE: begin
                     if (ahb.HSEL && ahb.HTRANS == HTRANS_NONSEQ) begin
                         ahbd.addr   <= ahb.HADDR;
                         ahbd.write  <= ahb.HWRITE;
                         ahb.HREADY  <= 'b0;
                     end
                     else begin
                         ahbd.addr   <= '0;
                         ahbd.write  <= 'b0;
                         ahb.HREADY  <= 'b1;
                     end
                     ahbd.work   <= 'b0;
                     ahbd.data   <= '0;
                     ahb.HRDATA[APB_DW-:]  <= apbd.data[ahbd.addr[AHB_AW-:AHB_AW-]];
                 end
                 AHB_WRITE: begin
                     ahb.HREADY  <= 'b0;
                     ahbd.work   <= 'b1;
                     ahbd.data   <= ahb.HWDATA;
                     ahb.HRDATA[APB_DW-:]  <= '0;
                 end
                 AHB_READ: begin
                     ahbd.work   <= 'b1;
                     ahbd.data   <= '0;
                     ahb.HREADY  <= 'b0;
                     ahb.HRDATA[APB_DW-:]  <= '0;
                 end
                 AHB_WAIT: begin
                     ahbd.work   <= 'b0;
                     ahb.HREADY  <= 'b0;
                     ahb.HRDATA[APB_DW-:]  <= '0;
                 end
             endcase
         end
     end
 
     assign  ahb.HRESP = HRESP_OKAY;
     // assign  ahb.HRDATA[AHB_DW-1:APB_DW] = '0;
 
     // APB Control Logic
     always_comb begin
         case (apbd.cstate)
             APB_IDLE: begin
                 if (ahbd.work) begin
                     if (ahbd.write)
                         apbd.nstate = APB_WRITE;
                     else
                         apbd.nstate = APB_READ;
                 end
                 else
                     apbd.nstate = APB_IDLE;
             end
             APB_WRITE:  apbd.nstate = APB_IDLE;
             APB_READ:   apbd.nstate = APB_IDLE;
             default:    apbd.nstate = APB_IDLE;
         endcase
     end
 
     always_ff @(posedge PCLK or negedge PRESETn) begin
         if (!PRESETn)
             apbd.cstate <= APB_IDLE;
         else
             apbd.cstate <= apbd.nstate;
     end
 
     always_ff @(posedge PCLK or negedge PRESETn) begin
         if (!PRESETn) begin
             apbd.work   <= 'b0;
             for (int j = ; j < NSLV; j++) begin
                 apbd.PSEL[j]    <= 'b0;
                 apbd.PENABLE[j] <= 'b0;
             end
         end
         else begin
             case (apbd.cstate)
                 APB_IDLE: begin
                     if (ahbd.work) begin
                         apbd.work <= 'b1;
                         for (int j = ; j < NSLV; j++)
                             apbd.PSEL[j] <= (ahbd.addr[AHB_AW-:AHB_AW-] == j) ? 'b1 : 1'b0;
                     end
                     else begin
                         apbd.work <= 'b0;
                         for (int j = ; j < NSLV; j++)
                             apbd.PSEL[j] <= 'b0;
                     end
                     for (int j = ; j < NSLV; j++)
                         apbd.PENABLE[j] <= 'b0;
                 end
                 APB_WRITE: begin
                     apbd.work <= 'b1;
                     for (int j = ; j < NSLV; j++)
                         apbd.PENABLE[j] <= (ahbd.addr[AHB_AW-:AHB_AW-] == j) ? 'b1 : 1'b0;
                 end
                 APB_READ: begin
                     apbd.work <= 'b1;
                     for (int j = ; j < NSLV; j++)
                         apbd.PENABLE[j] <= (ahbd.addr[AHB_AW-:AHB_AW-] == j) ? 'b1 : 1'b0;
                 end
             endcase
         end
     end
 
     generate
         for (i = ; i < NSLV; i++) begin: apbv_loop
             assign apbv[i].PADDR    = {'h0, ahbd.addr[APB_AW-4-1:0]};
             assign apbv[i].PWRITE   = ahbd.write;
             assign apbv[i].PWDATA   = ahbd.data[APB_DW-:];
             assign apbd.data[i]     = apbv[i].PRDATA;
             assign apbv[i].PSEL     = apbd.PSEL[i];
             assign apbv[i].PENABLE  = apbd.PENABLE[i];
         end
     endgenerate
 
 endmodule: ahb2apb_bridge