1. #define  CLK_PWRCON_PD_WAIT_CPU_Pos   8 
  2.  
  3. #define  CLK_PWRCON_PD_WAIT_CPU_Msk   (1ul << CLK_PWRCON_PD_WAIT_CPU_Pos) 
  4.  
  5. #define  CLK_PWRCON_PWR_DOWN_EN_Pos   7 
  6.  
  7. #define  CLK_PWRCON_PWR_DOWN_EN_Msk   (1ul << CLK_PWRCON_PWR_DOWN_EN_Pos) 
  8.  
  9. #define  CLK_PWRCON_PD_WU_STS_Pos   6 
  10.  
  11. #define  CLK_PWRCON_PD_WU_STS_Msk   (1ul << CLK_PWRCON_PD_WU_STS_Pos) 
  12.  
  13. #define  CLK_PWRCON_PD_WU_INT_EN_Pos   5 
  14.  
  15. #define  CLK_PWRCON_PD_WU_INT_EN_Msk   (1ul << CLK_PWRCON_PD_WU_INT_EN_Pos) 
  16.  
  17. #define  CLK_PWRCON_PD_WU_DLY_Pos   4 
  18.  
  19. #define  CLK_PWRCON_PD_WU_DLY_Msk   (1ul << CLK_PWRCON_PD_WU_DLY_Pos) 
  20.  
  21. #define  CLK_PWRCON_OSC10K_EN_Pos   3 
  22.  
  23. #define  CLK_PWRCON_OSC10K_EN_Msk   (1ul << CLK_PWRCON_OSC10K_EN_Pos) 
  24.  
  25. #define  CLK_PWRCON_IRC10K_EN_Pos   3 
  26.  
  27. #define  CLK_PWRCON_IRC10K_EN_Msk   (1ul << CLK_PWRCON_IRC10K_EN_Pos) 
  28.  
  29. #define  CLK_PWRCON_OSC22M_EN_Pos   2 
  30.  
  31. #define  CLK_PWRCON_OSC22M_EN_Msk   (1ul << CLK_PWRCON_OSC22M_EN_Pos) 
  32.  
  33. #define  CLK_PWRCON_IRC22M_EN_Pos   2 
  34.  
  35. #define  CLK_PWRCON_IRC22M_EN_Msk   (1ul << CLK_PWRCON_IRC22M_EN_Pos) 
  36.  
  37. #define  CLK_PWRCON_XTL12M_EN_Pos   0 
  38.  
  39. #define  CLK_PWRCON_XTL12M_EN_Msk   (1ul << CLK_PWRCON_XTL12M_EN_Pos) 
  40.  
  41. #define  CLK_AHBCLK_ISP_EN_Pos   2 
  42.  
  43. #define  CLK_AHBCLK_ISP_EN_Msk   (1ul << CLK_AHBCLK_ISP_EN_Pos) 
  44.  
  45. #define  CLK_AHBCLK_PDMA_EN_Pos   1 
  46.  
  47. #define  CLK_AHBCLK_PDMA_EN_Msk   (1ul << CLK_AHBCLK_PDMA_EN_Pos) 
  48.  
  49. #define  CLK_APBCLK_PS2_EN_Pos   31 
  50.  
  51. #define  CLK_APBCLK_PS2_EN_Msk   (1ul << CLK_APBCLK_PS2_EN_Pos) 
  52.  
  53. #define  CLK_APBCLK_I2S_EN_Pos   29 
  54.  
  55. #define  CLK_APBCLK_I2S_EN_Msk   (1ul << CLK_APBCLK_I2S_EN_Pos) 
  56.  
  57. #define  CLK_APBCLK_ADC_EN_Pos   28 
  58.  
  59. #define  CLK_APBCLK_ADC_EN_Msk   (1ul << CLK_APBCLK_ADC_EN_Pos) 
  60.  
  61. #define  CLK_APBCLK_USBD_EN_Pos   27 
  62.  
  63. #define  CLK_APBCLK_USBD_EN_Msk   (1ul << CLK_APBCLK_USBD_EN_Pos) 
  64.  
  65. #define  CLK_APBCLK_PWM23_EN_Pos   21 
  66.  
  67. #define  CLK_APBCLK_PWM23_EN_Msk   (1ul << CLK_APBCLK_PWM23_EN_Pos) 
  68.  
  69. #define  CLK_APBCLK_PWM01_EN_Pos   20 
  70.  
  71. #define  CLK_APBCLK_PWM01_EN_Msk   (1ul << CLK_APBCLK_PWM01_EN_Pos) 
  72.  
  73. #define  CLK_APBCLK_UART1_EN_Pos   17 
  74.  
  75. #define  CLK_APBCLK_UART1_EN_Msk   (1ul << CLK_APBCLK_UART1_EN_Pos) 
  76.  
  77. #define  CLK_APBCLK_UART0_EN_Pos   16 
  78.  
  79. #define  CLK_APBCLK_UART0_EN_Msk   (1ul << CLK_APBCLK_UART0_EN_Pos) 
  80.  
  81. #define  CLK_APBCLK_SPI2_EN_Pos   14 
  82.  
  83. #define  CLK_APBCLK_SPI2_EN_Msk   (1ul << CLK_APBCLK_SPI2_EN_Pos) 
  84.  
  85. #define  CLK_APBCLK_SPI1_EN_Pos   13 
  86.  
  87. #define  CLK_APBCLK_SPI1_EN_Msk   (1ul << CLK_APBCLK_SPI1_EN_Pos) 
  88.  
  89. #define  CLK_APBCLK_SPI0_EN_Pos   12 
  90.  
  91. #define  CLK_APBCLK_SPI0_EN_Msk   (1ul << CLK_APBCLK_SPI0_EN_Pos) 
  92.  
  93. #define  CLK_APBCLK_I2C1_EN_Pos   9 
  94.  
  95. #define  CLK_APBCLK_I2C1_EN_Msk   (1ul << CLK_APBCLK_I2C1_EN_Pos) 
  96.  
  97. #define  CLK_APBCLK_I2C0_EN_Pos   8 
  98.  
  99. #define  CLK_APBCLK_I2C0_EN_Msk   (1ul << CLK_APBCLK_I2C0_EN_Pos) 
  100.  
  101. #define  CLK_APBCLK_FDIV_EN_Pos   6 
  102.  
  103. #define  CLK_APBCLK_FDIV_EN_Msk   (1ul << CLK_APBCLK_FDIV_EN_Pos) 
  104.  
  105. #define  CLK_APBCLK_TMR3_EN_Pos   5 
  106.  
  107. #define  CLK_APBCLK_TMR3_EN_Msk   (1ul << CLK_APBCLK_TMR3_EN_Pos) 
  108.  
  109. #define  CLK_APBCLK_TMR2_EN_Pos   4 
  110.  
  111. #define  CLK_APBCLK_TMR2_EN_Msk   (1ul << CLK_APBCLK_TMR2_EN_Pos) 
  112.  
  113. #define  CLK_APBCLK_TMR1_EN_Pos   3 
  114.  
  115. #define  CLK_APBCLK_TMR1_EN_Msk   (1ul << CLK_APBCLK_TMR1_EN_Pos) 
  116.  
  117. #define  CLK_APBCLK_TMR0_EN_Pos   2 
  118.  
  119. #define  CLK_APBCLK_TMR0_EN_Msk   (1ul << CLK_APBCLK_TMR0_EN_Pos) 
  120.  
  121. #define  CLK_APBCLK_WDT_EN_Pos   0 
  122.  
  123. #define  CLK_APBCLK_WDT_EN_Msk   (1ul << CLK_APBCLK_WDT_EN_Pos) 
  124.  
  125. #define  CLK_CLKSTATUS_CLK_SW_FAIL_Pos   7 
  126.  
  127. #define  CLK_CLKSTATUS_CLK_SW_FAIL_Msk   (1ul << CLK_CLKSTATUS_CLK_SW_FAIL_Pos) 
  128.  
  129. #define  CLK_CLKSTATUS_OSC22M_STB_Pos   4 
  130.  
  131. #define  CLK_CLKSTATUS_OSC22M_STB_Msk   (1ul << CLK_CLKSTATUS_OSC22M_STB_Pos) 
  132.  
  133. #define  CLK_CLKSTATUS_IRC22M_STB_Pos   4 
  134.  
  135. #define  CLK_CLKSTATUS_IRC22M_STB_Msk   (1ul << CLK_CLKSTATUS_IRC22M_STB_Pos) 
  136.  
  137. #define  CLK_CLKSTATUS_OSC10K_STB_Pos   3 
  138.  
  139. #define  CLK_CLKSTATUS_OSC10K_STB_Msk   (1ul << CLK_CLKSTATUS_OSC10K_STB_Pos) 
  140.  
  141. #define  CLK_CLKSTATUS_IRC10K_STB_Pos   3 
  142.  
  143. #define  CLK_CLKSTATUS_IRC10K_STB_Msk   (1ul << CLK_CLKSTATUS_IRC10K_STB_Pos) 
  144.  
  145. #define  CLK_CLKSTATUS_PLL_STB_Pos   2 
  146.  
  147. #define  CLK_CLKSTATUS_PLL_STB_Msk   (1ul << CLK_CLKSTATUS_PLL_STB_Pos) 
  148.  
  149. #define  CLK_CLKSTATUS_XTL12M_STB_Pos   0 
  150.  
  151. #define  CLK_CLKSTATUS_XTL12M_STB_Msk   (1ul << CLK_CLKSTATUS_XTL12M_STB_Pos) 
  152.  
  153. #define  CLK_CLKSEL0_STCLK_S_Pos   3 
  154.  
  155. #define  CLK_CLKSEL0_STCLK_S_Msk   (7ul << CLK_CLKSEL0_STCLK_S_Pos) 
  156.  
  157. #define  CLK_CLKSEL0_HCLK_S_Pos   0 
  158.  
  159. #define  CLK_CLKSEL0_HCLK_S_Msk   (7ul << CLK_CLKSEL0_HCLK_S_Pos) 
  160.  
  161. #define  CLK_CLKSEL1_PWM23_S_Pos   30 
  162.  
  163. #define  CLK_CLKSEL1_PWM23_S_Msk   (3ul << CLK_CLKSEL1_PWM23_S_Pos) 
  164.  
  165. #define  CLK_CLKSEL1_PWM01_S_Pos   28 
  166.  
  167. #define  CLK_CLKSEL1_PWM01_S_Msk   (3ul << CLK_CLKSEL1_PWM01_S_Pos) 
  168.  
  169. #define  CLK_CLKSEL1_UART_S_Pos   24 
  170.  
  171. #define  CLK_CLKSEL1_UART_S_Msk   (3ul << CLK_CLKSEL1_UART_S_Pos) 
  172.  
  173. #define  CLK_CLKSEL1_TMR3_S_Pos   20 
  174.  
  175. #define  CLK_CLKSEL1_TMR3_S_Msk   (7ul << CLK_CLKSEL1_TMR3_S_Pos) 
  176.  
  177. #define  CLK_CLKSEL1_TMR2_S_Pos   16 
  178.  
  179. #define  CLK_CLKSEL1_TMR2_S_Msk   (7ul << CLK_CLKSEL1_TMR2_S_Pos) 
  180.  
  181. #define  CLK_CLKSEL1_TMR1_S_Pos   12 
  182.  
  183. #define  CLK_CLKSEL1_TMR1_S_Msk   (7ul << CLK_CLKSEL1_TMR1_S_Pos) 
  184.  
  185. #define  CLK_CLKSEL1_TMR0_S_Pos   8 
  186.  
  187. #define  CLK_CLKSEL1_TMR0_S_Msk   (7ul << CLK_CLKSEL1_TMR0_S_Pos) 
  188.  
  189. #define  CLK_CLKSEL1_SPI2_S_Pos   6 
  190.  
  191. #define  CLK_CLKSEL1_SPI2_S_Msk   (1ul << CLK_CLKSEL1_SPI2_S_Pos) 
  192.  
  193. #define  CLK_CLKSEL1_SPI1_S_Pos   5 
  194.  
  195. #define  CLK_CLKSEL1_SPI1_S_Msk   (1ul << CLK_CLKSEL1_SPI1_S_Pos) 
  196.  
  197. #define  CLK_CLKSEL1_SPI0_S_Pos   4 
  198.  
  199. #define  CLK_CLKSEL1_SPI0_S_Msk   (1ul << CLK_CLKSEL1_SPI0_S_Pos) 
  200.  
  201. #define  CLK_CLKSEL1_ADC_S_Pos   2 
  202.  
  203. #define  CLK_CLKSEL1_ADC_S_Msk   (3ul << CLK_CLKSEL1_ADC_S_Pos) 
  204.  
  205. #define  CLK_CLKSEL1_WDT_S_Pos   0 
  206.  
  207. #define  CLK_CLKSEL1_WDT_S_Msk   (3ul << CLK_CLKSEL1_WDT_S_Pos) 
  208.  
  209. #define  CLK_CLKSEL2_WWDT_S_Pos   16 
  210.  
  211. #define  CLK_CLKSEL2_WWDT_S_Msk   (3ul << CLK_CLKSEL2_WWDT_S_Pos) 
  212.  
  213. #define  CLK_CLKSEL2_PWM23_S_E_Pos   9 
  214.  
  215. #define  CLK_CLKSEL2_PWM23_S_E_Msk   (1ul << CLK_CLKSEL2_PWM23_S_E_Pos) 
  216.  
  217. #define  CLK_CLKSEL2_PWM23_S_EXT_Pos   9 
  218.  
  219. #define  CLK_CLKSEL2_PWM23_S_EXT_Msk   (1ul << CLK_CLKSEL2_PWM23_S_EXT_Pos) 
  220.  
  221. #define  CLK_CLKSEL2_PWM01_S_E_Pos   8 
  222.  
  223. #define  CLK_CLKSEL2_PWM01_S_E_Msk   (1ul << CLK_CLKSEL2_PWM01_S_E_Pos) 
  224.  
  225. #define  CLK_CLKSEL2_PWM01_S_EXT_Pos   8 
  226.  
  227. #define  CLK_CLKSEL2_PWM01_S_EXT_Msk   (1ul << CLK_CLKSEL2_PWM01_S_EXT_Pos) 
  228.  
  229. #define  CLK_CLKSEL2_FRQDIV_S_Pos   2 
  230.  
  231. #define  CLK_CLKSEL2_FRQDIV_S_Msk   (3ul << CLK_CLKSEL2_FRQDIV_S_Pos) 
  232.  
  233. #define  CLK_CLKSEL2_I2S_S_Pos   0 
  234.  
  235. #define  CLK_CLKSEL2_I2S_S_Msk   (3ul << CLK_CLKSEL2_I2S_S_Pos) 
  236.  
  237. #define  CLK_CLKDIV_ADC_N_Pos   16 
  238.  
  239. #define  CLK_CLKDIV_ADC_N_Msk   (0xFFul << CLK_CLKDIV_ADC_N_Pos) 
  240.  
  241. #define  CLK_CLKDIV_UART_N_Pos   8 
  242.  
  243. #define  CLK_CLKDIV_UART_N_Msk   (0xFul << CLK_CLKDIV_UART_N_Pos) 
  244.  
  245. #define  CLK_CLKDIV_USB_N_Pos   4 
  246.  
  247. #define  CLK_CLKDIV_USB_N_Msk   (0xFul << CLK_CLKDIV_USB_N_Pos) 
  248.  
  249. #define  CLK_CLKDIV_HCLK_N_Pos   0 
  250.  
  251. #define  CLK_CLKDIV_HCLK_N_Msk   (0xFul << CLK_CLKDIV_HCLK_N_Pos) 
  252.  
  253. #define  CLK_PLLCON_PLL_SRC_Pos   19 
  254.  
  255. #define  CLK_PLLCON_PLL_SRC_Msk   (1ul << CLK_PLLCON_PLL_SRC_Pos) 
  256.  
  257. #define  CLK_PLLCON_OE_Pos   18 
  258.  
  259. #define  CLK_PLLCON_OE_Msk   (1ul << CLK_PLLCON_OE_Pos) 
  260.  
  261. #define  CLK_PLLCON_BP_Pos   17 
  262.  
  263. #define  CLK_PLLCON_BP_Msk   (1ul << CLK_PLLCON_BP_Pos) 
  264.  
  265. #define  CLK_PLLCON_PD_Pos   16 
  266.  
  267. #define  CLK_PLLCON_PD_Msk   (1ul << CLK_PLLCON_PD_Pos) 
  268.  
  269. #define  CLK_PLLCON_OUT_DV_Pos   14 
  270.  
  271. #define  CLK_PLLCON_OUT_DV_Msk   (3ul << CLK_PLLCON_OUT_DV_Pos) 
  272.  
  273. #define  CLK_PLLCON_IN_DV_Pos   9 
  274.  
  275. #define  CLK_PLLCON_IN_DV_Msk   (0x1Ful << CLK_PLLCON_IN_DV_Pos) 
  276.  
  277. #define  CLK_PLLCON_FB_DV_Pos   0 
  278.  
  279. #define  CLK_PLLCON_FB_DV_Msk   (0x1FFul << CLK_PLLCON_FB_DV_Pos) 
  280.  
  281. #define  CLK_FRQDIV_DIVIDER_EN_Pos   4 
  282.  
  283. #define  CLK_FRQDIV_DIVIDER_EN_Msk   (1ul << CLK_FRQDIV_DIVIDER_EN_Pos) 
  284.  
  285. #define  CLK_FRQDIV_FSEL_Pos   0 
  286.  
  287. #define  CLK_FRQDIV_FSEL_Msk   (0xFul << CLK_FRQDIV_FSEL_Pos) 
  288.  
  289. #define  CLK_APBDIV_APBDIV_Pos   0 
  290.  
  291. #define  CLK_APBDIV_APBDIV_Msk   (1ul << CLK_APBDIV_APBDIV_Pos) 
  292.  
  293. Detailed Description
  294.  
  295. Macro Definition Documentation
  296.  
  297. #define CLK_AHBCLK_ISP_EN_Msk   (1ul << CLK_AHBCLK_ISP_EN_Pos) 
  298.  
  299. CLK_T::AHBCLK: ISP_EN Mask 
  300.  
  301. Definition at line  of file NUC123.h.
  302.  
  303. #define CLK_AHBCLK_ISP_EN_Pos   2 
  304.  
  305. CLK_T::AHBCLK: ISP_EN Position 
  306.  
  307. Definition at line  of file NUC123.h.
  308.  
  309. #define CLK_AHBCLK_PDMA_EN_Msk   (1ul << CLK_AHBCLK_PDMA_EN_Pos) 
  310.  
  311. CLK_T::AHBCLK: PDMA_EN Mask 
  312.  
  313. Definition at line  of file NUC123.h.
  314.  
  315. #define CLK_AHBCLK_PDMA_EN_Pos   1 
  316.  
  317. CLK_T::AHBCLK: PDMA_EN Position 
  318.  
  319. Definition at line  of file NUC123.h.
  320.  
  321. #define CLK_APBCLK_ADC_EN_Msk   (1ul << CLK_APBCLK_ADC_EN_Pos) 
  322.  
  323. CLK_T::APBCLK: ADC_EN Mask 
  324.  
  325. Definition at line  of file NUC123.h.
  326.  
  327. #define CLK_APBCLK_ADC_EN_Pos   28 
  328.  
  329. CLK_T::APBCLK: ADC_EN Position 
  330.  
  331. Definition at line  of file NUC123.h.
  332.  
  333. #define CLK_APBCLK_FDIV_EN_Msk   (1ul << CLK_APBCLK_FDIV_EN_Pos) 
  334.  
  335. CLK_T::APBCLK: FDIV_EN Mask 
  336.  
  337. Definition at line  of file NUC123.h.
  338.  
  339. #define CLK_APBCLK_FDIV_EN_Pos   6 
  340.  
  341. CLK_T::APBCLK: FDIV_EN Position 
  342.  
  343. Definition at line  of file NUC123.h.
  344.  
  345. #define CLK_APBCLK_I2C0_EN_Msk   (1ul << CLK_APBCLK_I2C0_EN_Pos) 
  346.  
  347. CLK_T::APBCLK: I2C0_EN_ Mask 
  348.  
  349. Definition at line  of file NUC123.h.
  350.  
  351. #define CLK_APBCLK_I2C0_EN_Pos   8 
  352.  
  353. CLK_T::APBCLK: I2C0_EN_ Position 
  354.  
  355. Definition at line  of file NUC123.h.
  356.  
  357. #define CLK_APBCLK_I2C1_EN_Msk   (1ul << CLK_APBCLK_I2C1_EN_Pos) 
  358.  
  359. CLK_T::APBCLK: I2C1_EN Mask 
  360.  
  361. Definition at line  of file NUC123.h.
  362.  
  363. #define CLK_APBCLK_I2C1_EN_Pos   9 
  364.  
  365. CLK_T::APBCLK: I2C1_EN Position 
  366.  
  367. Definition at line  of file NUC123.h.
  368.  
  369. #define CLK_APBCLK_I2S_EN_Msk   (1ul << CLK_APBCLK_I2S_EN_Pos) 
  370.  
  371. CLK_T::APBCLK: I2S_EN Mask 
  372.  
  373. Definition at line  of file NUC123.h.
  374.  
  375. #define CLK_APBCLK_I2S_EN_Pos   29 
  376.  
  377. CLK_T::APBCLK: I2S_EN Position 
  378.  
  379. Definition at line  of file NUC123.h.
  380.  
  381. #define CLK_APBCLK_PS2_EN_Msk   (1ul << CLK_APBCLK_PS2_EN_Pos) 
  382.  
  383. CLK_T::APBCLK: PS2_EN Mask 
  384.  
  385. Definition at line  of file NUC123.h.
  386.  
  387. #define CLK_APBCLK_PS2_EN_Pos   31 
  388.  
  389. CLK_T::APBCLK: PS2_EN Position 
  390.  
  391. Definition at line  of file NUC123.h.
  392.  
  393. #define CLK_APBCLK_PWM01_EN_Msk   (1ul << CLK_APBCLK_PWM01_EN_Pos) 
  394.  
  395. CLK_T::APBCLK: PWM01_EN Mask 
  396.  
  397. Definition at line  of file NUC123.h.
  398.  
  399. #define CLK_APBCLK_PWM01_EN_Pos   20 
  400.  
  401. CLK_T::APBCLK: PWM01_EN Position 
  402.  
  403. Definition at line  of file NUC123.h.
  404.  
  405. #define CLK_APBCLK_PWM23_EN_Msk   (1ul << CLK_APBCLK_PWM23_EN_Pos) 
  406.  
  407. CLK_T::APBCLK: PWM23_EN Mask 
  408.  
  409. Definition at line  of file NUC123.h.
  410.  
  411. #define CLK_APBCLK_PWM23_EN_Pos   21 
  412.  
  413. CLK_T::APBCLK: PWM23_EN Position 
  414.  
  415. Definition at line  of file NUC123.h.
  416.  
  417. #define CLK_APBCLK_SPI0_EN_Msk   (1ul << CLK_APBCLK_SPI0_EN_Pos) 
  418.  
  419. CLK_T::APBCLK: SPI0_EN Mask 
  420.  
  421. Definition at line  of file NUC123.h.
  422.  
  423. #define CLK_APBCLK_SPI0_EN_Pos   12 
  424.  
  425. CLK_T::APBCLK: SPI0_EN Position 
  426.  
  427. Definition at line  of file NUC123.h.
  428.  
  429. #define CLK_APBCLK_SPI1_EN_Msk   (1ul << CLK_APBCLK_SPI1_EN_Pos) 
  430.  
  431. CLK_T::APBCLK: SPI1_EN Mask 
  432.  
  433. Definition at line  of file NUC123.h.
  434.  
  435. #define CLK_APBCLK_SPI1_EN_Pos   13 
  436.  
  437. CLK_T::APBCLK: SPI1_EN Position 
  438.  
  439. Definition at line  of file NUC123.h.
  440.  
  441. #define CLK_APBCLK_SPI2_EN_Msk   (1ul << CLK_APBCLK_SPI2_EN_Pos) 
  442.  
  443. CLK_T::APBCLK: SPI2_EN Mask 
  444.  
  445. Definition at line  of file NUC123.h.
  446.  
  447. #define CLK_APBCLK_SPI2_EN_Pos   14 
  448.  
  449. CLK_T::APBCLK: SPI2_EN Position 
  450.  
  451. Definition at line  of file NUC123.h.
  452.  
  453. #define CLK_APBCLK_TMR0_EN_Msk   (1ul << CLK_APBCLK_TMR0_EN_Pos) 
  454.  
  455. CLK_T::APBCLK: TMR0_EN Mask 
  456.  
  457. Definition at line  of file NUC123.h.
  458.  
  459. #define CLK_APBCLK_TMR0_EN_Pos   2 
  460.  
  461. CLK_T::APBCLK: TMR0_EN Position 
  462.  
  463. Definition at line  of file NUC123.h.
  464.  
  465. #define CLK_APBCLK_TMR1_EN_Msk   (1ul << CLK_APBCLK_TMR1_EN_Pos) 
  466.  
  467. CLK_T::APBCLK: TMR1_EN Mask 
  468.  
  469. Definition at line  of file NUC123.h.
  470.  
  471. #define CLK_APBCLK_TMR1_EN_Pos   3 
  472.  
  473. CLK_T::APBCLK: TMR1_EN Position 
  474.  
  475. Definition at line  of file NUC123.h.
  476.  
  477. #define CLK_APBCLK_TMR2_EN_Msk   (1ul << CLK_APBCLK_TMR2_EN_Pos) 
  478.  
  479. CLK_T::APBCLK: TMR2_EN Mask 
  480.  
  481. Definition at line  of file NUC123.h.
  482.  
  483. #define CLK_APBCLK_TMR2_EN_Pos   4 
  484.  
  485. CLK_T::APBCLK: TMR2_EN Position 
  486.  
  487. Definition at line  of file NUC123.h.
  488.  
  489. #define CLK_APBCLK_TMR3_EN_Msk   (1ul << CLK_APBCLK_TMR3_EN_Pos) 
  490.  
  491. CLK_T::APBCLK: TMR3_EN Mask 
  492.  
  493. Definition at line  of file NUC123.h.
  494.  
  495. #define CLK_APBCLK_TMR3_EN_Pos   5 
  496.  
  497. CLK_T::APBCLK: TMR3_EN Position 
  498.  
  499. Definition at line  of file NUC123.h.
  500.  
  501. #define CLK_APBCLK_UART0_EN_Msk   (1ul << CLK_APBCLK_UART0_EN_Pos) 
  502.  
  503. CLK_T::APBCLK: UART0_EN Mask 
  504.  
  505. Definition at line  of file NUC123.h.
  506.  
  507. #define CLK_APBCLK_UART0_EN_Pos   16 
  508.  
  509. CLK_T::APBCLK: UART0_EN Position 
  510.  
  511. Definition at line  of file NUC123.h.
  512.  
  513. #define CLK_APBCLK_UART1_EN_Msk   (1ul << CLK_APBCLK_UART1_EN_Pos) 
  514.  
  515. CLK_T::APBCLK: UART1_EN Mask 
  516.  
  517. Definition at line  of file NUC123.h.
  518.  
  519. #define CLK_APBCLK_UART1_EN_Pos   17 
  520.  
  521. CLK_T::APBCLK: UART1_EN Position 
  522.  
  523. Definition at line  of file NUC123.h.
  524.  
  525. #define CLK_APBCLK_USBD_EN_Msk   (1ul << CLK_APBCLK_USBD_EN_Pos) 
  526.  
  527. CLK_T::APBCLK: USBD_EN Mask 
  528.  
  529. Definition at line  of file NUC123.h.
  530.  
  531. #define CLK_APBCLK_USBD_EN_Pos   27 
  532.  
  533. CLK_T::APBCLK: USBD_EN Position 
  534.  
  535. Definition at line  of file NUC123.h.
  536.  
  537. #define CLK_APBCLK_WDT_EN_Msk   (1ul << CLK_APBCLK_WDT_EN_Pos) 
  538.  
  539. CLK_T::APBCLK: WDT_EN Mask 
  540.  
  541. Definition at line  of file NUC123.h.
  542.  
  543. #define CLK_APBCLK_WDT_EN_Pos   0 
  544.  
  545. CLK_T::APBCLK: WDT_EN Position 
  546.  
  547. Definition at line  of file NUC123.h.
  548.  
  549. #define CLK_APBDIV_APBDIV_Msk   (1ul << CLK_APBDIV_APBDIV_Pos) 
  550.  
  551. CLK_T::APBDIV: APBDIV Mask 
  552.  
  553. Definition at line  of file NUC123.h.
  554.  
  555. #define CLK_APBDIV_APBDIV_Pos   0 
  556.  
  557. CLK_T::APBDIV: APBDIV Position 
  558.  
  559. Definition at line  of file NUC123.h.
  560.  
  561. #define CLK_CLKDIV_ADC_N_Msk   (0xFFul << CLK_CLKDIV_ADC_N_Pos) 
  562.  
  563. CLK_T::CLKDIV: ADC_N Mask 
  564.  
  565. Definition at line  of file NUC123.h.
  566.  
  567. #define CLK_CLKDIV_ADC_N_Pos   16 
  568.  
  569. CLK_T::CLKDIV: ADC_N Position 
  570.  
  571. Definition at line  of file NUC123.h.
  572.  
  573. #define CLK_CLKDIV_HCLK_N_Msk   (0xFul << CLK_CLKDIV_HCLK_N_Pos) 
  574.  
  575. CLK_T::CLKDIV: HCLK_N Mask 
  576.  
  577. Definition at line  of file NUC123.h.
  578.  
  579. #define CLK_CLKDIV_HCLK_N_Pos   0 
  580.  
  581. CLK_T::CLKDIV: HCLK_N Position 
  582.  
  583. Definition at line  of file NUC123.h.
  584.  
  585. #define CLK_CLKDIV_UART_N_Msk   (0xFul << CLK_CLKDIV_UART_N_Pos) 
  586.  
  587. CLK_T::CLKDIV: UART_N Mask 
  588.  
  589. Definition at line  of file NUC123.h.
  590.  
  591. #define CLK_CLKDIV_UART_N_Pos   8 
  592.  
  593. CLK_T::CLKDIV: UART_N Position 
  594.  
  595. Definition at line  of file NUC123.h.
  596.  
  597. #define CLK_CLKDIV_USB_N_Msk   (0xFul << CLK_CLKDIV_USB_N_Pos) 
  598.  
  599. CLK_T::CLKDIV: USB_N Mask 
  600.  
  601. Definition at line  of file NUC123.h.
  602.  
  603. #define CLK_CLKDIV_USB_N_Pos   4 
  604.  
  605. CLK_T::CLKDIV: USB_N Position 
  606.  
  607. Definition at line  of file NUC123.h.
  608.  
  609. #define CLK_CLKSEL0_HCLK_S_Msk   (7ul << CLK_CLKSEL0_HCLK_S_Pos) 
  610.  
  611. CLK_T::CLKSEL0: HCLK_S Mask 
  612.  
  613. Definition at line  of file NUC123.h.
  614.  
  615. #define CLK_CLKSEL0_HCLK_S_Pos   0 
  616.  
  617. CLK_T::CLKSEL0: HCLK_S Position 
  618.  
  619. Definition at line  of file NUC123.h.
  620.  
  621. #define CLK_CLKSEL0_STCLK_S_Msk   (7ul << CLK_CLKSEL0_STCLK_S_Pos) 
  622.  
  623. CLK_T::CLKSEL0: STCLK_S Mask 
  624.  
  625. Definition at line  of file NUC123.h.
  626.  
  627. #define CLK_CLKSEL0_STCLK_S_Pos   3 
  628.  
  629. CLK_T::CLKSEL0: STCLK_S Position 
  630.  
  631. Definition at line  of file NUC123.h.
  632.  
  633. #define CLK_CLKSEL1_ADC_S_Msk   (3ul << CLK_CLKSEL1_ADC_S_Pos) 
  634.  
  635. CLK_T::CLKSEL1: ADC_S Mask 
  636.  
  637. Definition at line  of file NUC123.h.
  638.  
  639. #define CLK_CLKSEL1_ADC_S_Pos   2 
  640.  
  641. CLK_T::CLKSEL1: ADC_S Position 
  642.  
  643. Definition at line  of file NUC123.h.
  644.  
  645. #define CLK_CLKSEL1_PWM01_S_Msk   (3ul << CLK_CLKSEL1_PWM01_S_Pos) 
  646.  
  647. CLK_T::CLKSEL1: PWM01_S Mask 
  648.  
  649. Definition at line  of file NUC123.h.
  650.  
  651. #define CLK_CLKSEL1_PWM01_S_Pos   28 
  652.  
  653. CLK_T::CLKSEL1: PWM01_S Position 
  654.  
  655. Definition at line  of file NUC123.h.
  656.  
  657. #define CLK_CLKSEL1_PWM23_S_Msk   (3ul << CLK_CLKSEL1_PWM23_S_Pos) 
  658.  
  659. CLK_T::CLKSEL1: PWM23_S Mask 
  660.  
  661. Definition at line  of file NUC123.h.
  662.  
  663. #define CLK_CLKSEL1_PWM23_S_Pos   30 
  664.  
  665. CLK_T::CLKSEL1: PWM23_S Position 
  666.  
  667. Definition at line  of file NUC123.h.
  668.  
  669. #define CLK_CLKSEL1_SPI0_S_Msk   (1ul << CLK_CLKSEL1_SPI0_S_Pos) 
  670.  
  671. CLK_T::CLKSEL1: SPI0_S Mask 
  672.  
  673. Definition at line  of file NUC123.h.
  674.  
  675. #define CLK_CLKSEL1_SPI0_S_Pos   4 
  676.  
  677. CLK_T::CLKSEL1: SPI0_S Position 
  678.  
  679. Definition at line  of file NUC123.h.
  680.  
  681. #define CLK_CLKSEL1_SPI1_S_Msk   (1ul << CLK_CLKSEL1_SPI1_S_Pos) 
  682.  
  683. CLK_T::CLKSEL1: SPI1_S Mask 
  684.  
  685. Definition at line  of file NUC123.h.
  686.  
  687. #define CLK_CLKSEL1_SPI1_S_Pos   5 
  688.  
  689. CLK_T::CLKSEL1: SPI1_S Position 
  690.  
  691. Definition at line  of file NUC123.h.
  692.  
  693. #define CLK_CLKSEL1_SPI2_S_Msk   (1ul << CLK_CLKSEL1_SPI2_S_Pos) 
  694.  
  695. CLK_T::CLKSEL1: SPI2_S Mask 
  696.  
  697. Definition at line  of file NUC123.h.
  698.  
  699. #define CLK_CLKSEL1_SPI2_S_Pos   6 
  700.  
  701. CLK_T::CLKSEL1: SPI2_S Position 
  702.  
  703. Definition at line  of file NUC123.h.
  704.  
  705. #define CLK_CLKSEL1_TMR0_S_Msk   (7ul << CLK_CLKSEL1_TMR0_S_Pos) 
  706.  
  707. CLK_T::CLKSEL1: TMR0_S Mask 
  708.  
  709. Definition at line  of file NUC123.h.
  710.  
  711. #define CLK_CLKSEL1_TMR0_S_Pos   8 
  712.  
  713. CLK_T::CLKSEL1: TMR0_S Position 
  714.  
  715. Definition at line  of file NUC123.h.
  716.  
  717. #define CLK_CLKSEL1_TMR1_S_Msk   (7ul << CLK_CLKSEL1_TMR1_S_Pos) 
  718.  
  719. CLK_T::CLKSEL1: TMR1_S Mask 
  720.  
  721. Definition at line  of file NUC123.h.
  722.  
  723. #define CLK_CLKSEL1_TMR1_S_Pos   12 
  724.  
  725. CLK_T::CLKSEL1: TMR1_S Position 
  726.  
  727. Definition at line  of file NUC123.h.
  728.  
  729. #define CLK_CLKSEL1_TMR2_S_Msk   (7ul << CLK_CLKSEL1_TMR2_S_Pos) 
  730.  
  731. CLK_T::CLKSEL1: TMR2_S Mask 
  732.  
  733. Definition at line  of file NUC123.h.
  734.  
  735. #define CLK_CLKSEL1_TMR2_S_Pos   16 
  736.  
  737. CLK_T::CLKSEL1: TMR2_S Position 
  738.  
  739. Definition at line  of file NUC123.h.
  740.  
  741. #define CLK_CLKSEL1_TMR3_S_Msk   (7ul << CLK_CLKSEL1_TMR3_S_Pos) 
  742.  
  743. CLK_T::CLKSEL1: TMR3_S Mask 
  744.  
  745. Definition at line  of file NUC123.h.
  746.  
  747. #define CLK_CLKSEL1_TMR3_S_Pos   20 
  748.  
  749. CLK_T::CLKSEL1: TMR3_S Position 
  750.  
  751. Definition at line  of file NUC123.h.
  752.  
  753. #define CLK_CLKSEL1_UART_S_Msk   (3ul << CLK_CLKSEL1_UART_S_Pos) 
  754.  
  755. CLK_T::CLKSEL1: UART_S Mask 
  756.  
  757. Definition at line  of file NUC123.h.
  758.  
  759. #define CLK_CLKSEL1_UART_S_Pos   24 
  760.  
  761. CLK_T::CLKSEL1: UART_S Position 
  762.  
  763. Definition at line  of file NUC123.h.
  764.  
  765. #define CLK_CLKSEL1_WDT_S_Msk   (3ul << CLK_CLKSEL1_WDT_S_Pos) 
  766.  
  767. CLK_T::CLKSEL1: WDT_S Mask 
  768.  
  769. Definition at line  of file NUC123.h.
  770.  
  771. #define CLK_CLKSEL1_WDT_S_Pos   0 
  772.  
  773. CLK_T::CLKSEL1: WDT_S Position 
  774.  
  775. Definition at line  of file NUC123.h.
  776.  
  777. #define CLK_CLKSEL2_FRQDIV_S_Msk   (3ul << CLK_CLKSEL2_FRQDIV_S_Pos) 
  778.  
  779. CLK_T::CLKSEL2: FRQDIV_S Mask 
  780.  
  781. Definition at line  of file NUC123.h.
  782.  
  783. #define CLK_CLKSEL2_FRQDIV_S_Pos   2 
  784.  
  785. CLK_T::CLKSEL2: FRQDIV_S Position 
  786.  
  787. Definition at line  of file NUC123.h.
  788.  
  789. #define CLK_CLKSEL2_I2S_S_Msk   (3ul << CLK_CLKSEL2_I2S_S_Pos) 
  790.  
  791. CLK_T::CLKSEL2: I2S_S Mask 
  792.  
  793. Definition at line  of file NUC123.h.
  794.  
  795. #define CLK_CLKSEL2_I2S_S_Pos   0 
  796.  
  797. CLK_T::CLKSEL2: I2S_S Position 
  798.  
  799. Definition at line  of file NUC123.h.
  800.  
  801. #define CLK_CLKSEL2_PWM01_S_E_Msk   (1ul << CLK_CLKSEL2_PWM01_S_E_Pos) 
  802.  
  803. CLK_T::CLKSEL2: PWM01_S_E Mask 
  804.  
  805. Definition at line  of file NUC123.h.
  806.  
  807. #define CLK_CLKSEL2_PWM01_S_E_Pos   8 
  808.  
  809. CLK_T::CLKSEL2: PWM01_S_E Position 
  810.  
  811. Definition at line  of file NUC123.h.
  812.  
  813. #define CLK_CLKSEL2_PWM01_S_EXT_Msk   (1ul << CLK_CLKSEL2_PWM01_S_EXT_Pos) 
  814.  
  815. CLK_T::CLKSEL2: PWM01_S_EXT Mask 
  816.  
  817. Definition at line  of file NUC123.h.
  818.  
  819. #define CLK_CLKSEL2_PWM01_S_EXT_Pos   8 
  820.  
  821. CLK_T::CLKSEL2: PWM01_S_EXT Position 
  822.  
  823. Definition at line  of file NUC123.h.
  824.  
  825. #define CLK_CLKSEL2_PWM23_S_E_Msk   (1ul << CLK_CLKSEL2_PWM23_S_E_Pos) 
  826.  
  827. CLK_T::CLKSEL2: PWM23_S_E Mask 
  828.  
  829. Definition at line  of file NUC123.h.
  830.  
  831. #define CLK_CLKSEL2_PWM23_S_E_Pos   9 
  832.  
  833. CLK_T::CLKSEL2: PWM23_S_E Position 
  834.  
  835. Definition at line  of file NUC123.h.
  836.  
  837. #define CLK_CLKSEL2_PWM23_S_EXT_Msk   (1ul << CLK_CLKSEL2_PWM23_S_EXT_Pos) 
  838.  
  839. CLK_T::CLKSEL2: PWM23_S_EXT Mask 
  840.  
  841. Definition at line  of file NUC123.h.
  842.  
  843. #define CLK_CLKSEL2_PWM23_S_EXT_Pos   9 
  844.  
  845. CLK_T::CLKSEL2: PWM23_S_EXT Position 
  846.  
  847. Definition at line  of file NUC123.h.
  848.  
  849. #define CLK_CLKSEL2_WWDT_S_Msk   (3ul << CLK_CLKSEL2_WWDT_S_Pos) 
  850.  
  851. CLK_T::CLKSEL2: WWDT_S Mask 
  852.  
  853. Definition at line  of file NUC123.h.
  854.  
  855. #define CLK_CLKSEL2_WWDT_S_Pos   16 
  856.  
  857. CLK_T::CLKSEL2: WWDT_S Position 
  858.  
  859. Definition at line  of file NUC123.h.
  860.  
  861. #define CLK_CLKSTATUS_CLK_SW_FAIL_Msk   (1ul << CLK_CLKSTATUS_CLK_SW_FAIL_Pos) 
  862.  
  863. CLK_T::CLKSTATUS: CLK_SW_FAIL Mask 
  864.  
  865. Definition at line  of file NUC123.h.
  866.  
  867. #define CLK_CLKSTATUS_CLK_SW_FAIL_Pos   7 
  868.  
  869. CLK_T::CLKSTATUS: CLK_SW_FAIL Position 
  870.  
  871. Definition at line  of file NUC123.h.
  872.  
  873. #define CLK_CLKSTATUS_IRC10K_STB_Msk   (1ul << CLK_CLKSTATUS_IRC10K_STB_Pos) 
  874.  
  875. CLK_T::CLKSTATUS: IRC10K_STB Mask 
  876.  
  877. Definition at line  of file NUC123.h.
  878.  
  879. #define CLK_CLKSTATUS_IRC10K_STB_Pos   3 
  880.  
  881. CLK_T::CLKSTATUS: IRC10K_STB Position 
  882.  
  883. Definition at line  of file NUC123.h.
  884.  
  885. #define CLK_CLKSTATUS_IRC22M_STB_Msk   (1ul << CLK_CLKSTATUS_IRC22M_STB_Pos) 
  886.  
  887. CLK_T::CLKSTATUS: IRC22M_STB Mask 
  888.  
  889. Definition at line  of file NUC123.h.
  890.  
  891. #define CLK_CLKSTATUS_IRC22M_STB_Pos   4 
  892.  
  893. CLK_T::CLKSTATUS: IRC22M_STB Position 
  894.  
  895. Definition at line  of file NUC123.h.
  896.  
  897. #define CLK_CLKSTATUS_OSC10K_STB_Msk   (1ul << CLK_CLKSTATUS_OSC10K_STB_Pos) 
  898.  
  899. CLK_T::CLKSTATUS: OSC10K_STB Mask 
  900.  
  901. Definition at line  of file NUC123.h.
  902.  
  903. #define CLK_CLKSTATUS_OSC10K_STB_Pos   3 
  904.  
  905. CLK_T::CLKSTATUS: OSC10K_STB Position 
  906.  
  907. Definition at line  of file NUC123.h.
  908.  
  909. #define CLK_CLKSTATUS_OSC22M_STB_Msk   (1ul << CLK_CLKSTATUS_OSC22M_STB_Pos) 
  910.  
  911. CLK_T::CLKSTATUS: OSC22M_STB Mask 
  912.  
  913. Definition at line  of file NUC123.h.
  914.  
  915. #define CLK_CLKSTATUS_OSC22M_STB_Pos   4 
  916.  
  917. CLK_T::CLKSTATUS: OSC22M_STB Position 
  918.  
  919. Definition at line  of file NUC123.h.
  920.  
  921. #define CLK_CLKSTATUS_PLL_STB_Msk   (1ul << CLK_CLKSTATUS_PLL_STB_Pos) 
  922.  
  923. CLK_T::CLKSTATUS: PLL_STB Mask 
  924.  
  925. Definition at line  of file NUC123.h.
  926.  
  927. #define CLK_CLKSTATUS_PLL_STB_Pos   2 
  928.  
  929. CLK_T::CLKSTATUS: PLL_STB Position 
  930.  
  931. Definition at line  of file NUC123.h.
  932.  
  933. #define CLK_CLKSTATUS_XTL12M_STB_Msk   (1ul << CLK_CLKSTATUS_XTL12M_STB_Pos) 
  934.  
  935. CLK_T::CLKSTATUS: XTL12M_STB Mask 
  936.  
  937. Definition at line  of file NUC123.h.
  938.  
  939. #define CLK_CLKSTATUS_XTL12M_STB_Pos   0 
  940.  
  941. CLK_T::CLKSTATUS: XTL12M_STB Position 
  942.  
  943. Definition at line  of file NUC123.h.
  944.  
  945. #define CLK_FRQDIV_DIVIDER_EN_Msk   (1ul << CLK_FRQDIV_DIVIDER_EN_Pos) 
  946.  
  947. CLK_T::FRQDIV: DIVIDER_EN Mask 
  948.  
  949. Definition at line  of file NUC123.h.
  950.  
  951. #define CLK_FRQDIV_DIVIDER_EN_Pos   4 
  952.  
  953. CLK_T::FRQDIV: DIVIDER_EN Position 
  954.  
  955. Definition at line  of file NUC123.h.
  956.  
  957. #define CLK_FRQDIV_FSEL_Msk   (0xFul << CLK_FRQDIV_FSEL_Pos) 
  958.  
  959. CLK_T::FRQDIV: FRQDIV_FSEL Mask 
  960.  
  961. Definition at line  of file NUC123.h.
  962.  
  963. #define CLK_FRQDIV_FSEL_Pos   0 
  964.  
  965. CLK_T::FRQDIV: FRQDIV_FSEL Position 
  966.  
  967. Definition at line  of file NUC123.h.
  968.  
  969. #define CLK_PLLCON_BP_Msk   (1ul << CLK_PLLCON_BP_Pos) 
  970.  
  971. CLK_T::PLLCON: OE Mask 
  972.  
  973. Definition at line  of file NUC123.h.
  974.  
  975. #define CLK_PLLCON_BP_Pos   17 
  976.  
  977. CLK_T::PLLCON: OE Position 
  978.  
  979. Definition at line  of file NUC123.h.
  980.  
  981. #define CLK_PLLCON_FB_DV_Msk   (0x1FFul << CLK_PLLCON_FB_DV_Pos) 
  982.  
  983. CLK_T::PLLCON: FB_DV Mask 
  984.  
  985. Definition at line  of file NUC123.h.
  986.  
  987. #define CLK_PLLCON_FB_DV_Pos   0 
  988.  
  989. CLK_T::PLLCON: FB_DV Position 
  990.  
  991. Definition at line  of file NUC123.h.
  992.  
  993. #define CLK_PLLCON_IN_DV_Msk   (0x1Ful << CLK_PLLCON_IN_DV_Pos) 
  994.  
  995. CLK_T::PLLCON: IN_DV Mask 
  996.  
  997. Definition at line  of file NUC123.h.
  998.  
  999. #define CLK_PLLCON_IN_DV_Pos   9 
  1000.  
  1001. CLK_T::PLLCON: IN_DV Position 
  1002.  
  1003. Definition at line  of file NUC123.h.
  1004.  
  1005. #define CLK_PLLCON_OE_Msk   (1ul << CLK_PLLCON_OE_Pos) 
  1006.  
  1007. CLK_T::PLLCON: PLL_SRC Mask 
  1008.  
  1009. Definition at line  of file NUC123.h.
  1010.  
  1011. #define CLK_PLLCON_OE_Pos   18 
  1012.  
  1013. CLK_T::PLLCON: PLL_SRC Position 
  1014.  
  1015. Definition at line  of file NUC123.h.
  1016.  
  1017. #define CLK_PLLCON_OUT_DV_Msk   (3ul << CLK_PLLCON_OUT_DV_Pos) 
  1018.  
  1019. CLK_T::PLLCON: OUT_DV Mask 
  1020.  
  1021. Definition at line  of file NUC123.h.
  1022.  
  1023. #define CLK_PLLCON_OUT_DV_Pos   14 
  1024.  
  1025. CLK_T::PLLCON: OUT_DV Position 
  1026.  
  1027. Definition at line  of file NUC123.h.
  1028.  
  1029. #define CLK_PLLCON_PD_Msk   (1ul << CLK_PLLCON_PD_Pos) 
  1030.  
  1031. CLK_T::PLLCON: PD Mask 
  1032.  
  1033. Definition at line  of file NUC123.h.
  1034.  
  1035. #define CLK_PLLCON_PD_Pos   16 
  1036.  
  1037. CLK_T::PLLCON: PD Position 
  1038.  
  1039. Definition at line  of file NUC123.h.
  1040.  
  1041. #define CLK_PLLCON_PLL_SRC_Msk   (1ul << CLK_PLLCON_PLL_SRC_Pos) 
  1042.  
  1043. CLK_T::PLLCON: PLL_SRC Mask 
  1044.  
  1045. Definition at line  of file NUC123.h.
  1046.  
  1047. #define CLK_PLLCON_PLL_SRC_Pos   19 
  1048.  
  1049. CLK_T::PLLCON: PLL_SRC Position 
  1050.  
  1051. Definition at line  of file NUC123.h.
  1052.  
  1053. #define CLK_PWRCON_IRC10K_EN_Msk   (1ul << CLK_PWRCON_IRC10K_EN_Pos) 
  1054.  
  1055. CLK_T::PWRCON: IRC10K_EN Mask 
  1056.  
  1057. Definition at line  of file NUC123.h.
  1058.  
  1059. #define CLK_PWRCON_IRC10K_EN_Pos   3 
  1060.  
  1061. CLK_T::PWRCON: IRC10K_EN Position 
  1062.  
  1063. Definition at line  of file NUC123.h.
  1064.  
  1065. #define CLK_PWRCON_IRC22M_EN_Msk   (1ul << CLK_PWRCON_IRC22M_EN_Pos) 
  1066.  
  1067. CLK_T::PWRCON: IRC22M_EN Mask 
  1068.  
  1069. Definition at line  of file NUC123.h.
  1070.  
  1071. #define CLK_PWRCON_IRC22M_EN_Pos   2 
  1072.  
  1073. CLK_T::PWRCON: IRC22M_EN Position 
  1074.  
  1075. Definition at line  of file NUC123.h.
  1076.  
  1077. #define CLK_PWRCON_OSC10K_EN_Msk   (1ul << CLK_PWRCON_OSC10K_EN_Pos) 
  1078.  
  1079. CLK_T::PWRCON: OSC10K_EN Mask 
  1080.  
  1081. Definition at line  of file NUC123.h.
  1082.  
  1083. #define CLK_PWRCON_OSC10K_EN_Pos   3 
  1084.  
  1085. CLK_T::PWRCON: OSC10K_EN Position 
  1086.  
  1087. Definition at line  of file NUC123.h.
  1088.  
  1089. #define CLK_PWRCON_OSC22M_EN_Msk   (1ul << CLK_PWRCON_OSC22M_EN_Pos) 
  1090.  
  1091. CLK_T::PWRCON: OSC22M_EN Mask 
  1092.  
  1093. Definition at line  of file NUC123.h.
  1094.  
  1095. #define CLK_PWRCON_OSC22M_EN_Pos   2 
  1096.  
  1097. CLK_T::PWRCON: OSC22M_EN Position 
  1098.  
  1099. Definition at line  of file NUC123.h.
  1100.  
  1101. #define CLK_PWRCON_PD_WAIT_CPU_Msk   (1ul << CLK_PWRCON_PD_WAIT_CPU_Pos) 
  1102.  
  1103. CLK_T::PWRCON: PD_WAIT_CPU Mask 
  1104.  
  1105. Definition at line  of file NUC123.h.
  1106.  
  1107. #define CLK_PWRCON_PD_WAIT_CPU_Pos   8 
  1108.  
  1109. CLK_T::PWRCON: PD_WAIT_CPU Position 
  1110.  
  1111. Definition at line  of file NUC123.h.
  1112.  
  1113. #define CLK_PWRCON_PD_WU_DLY_Msk   (1ul << CLK_PWRCON_PD_WU_DLY_Pos) 
  1114.  
  1115. CLK_T::PWRCON: PD_WU_DLY Mask 
  1116.  
  1117. Definition at line  of file NUC123.h.
  1118.  
  1119. #define CLK_PWRCON_PD_WU_DLY_Pos   4 
  1120.  
  1121. CLK_T::PWRCON: PD_WU_DLY Position 
  1122.  
  1123. Definition at line  of file NUC123.h.
  1124.  
  1125. #define CLK_PWRCON_PD_WU_INT_EN_Msk   (1ul << CLK_PWRCON_PD_WU_INT_EN_Pos) 
  1126.  
  1127. CLK_T::PWRCON: PD_WU_INT_EN Mask 
  1128.  
  1129. Definition at line  of file NUC123.h.
  1130.  
  1131. #define CLK_PWRCON_PD_WU_INT_EN_Pos   5 
  1132.  
  1133. CLK_T::PWRCON: PD_WU_INT_EN Position 
  1134.  
  1135. Definition at line  of file NUC123.h.
  1136.  
  1137. #define CLK_PWRCON_PD_WU_STS_Msk   (1ul << CLK_PWRCON_PD_WU_STS_Pos) 
  1138.  
  1139. CLK_T::PWRCON: PD_WU_STS Mask 
  1140.  
  1141. Definition at line  of file NUC123.h.
  1142.  
  1143. #define CLK_PWRCON_PD_WU_STS_Pos   6 
  1144.  
  1145. CLK_T::PWRCON: PD_WU_STS Position 
  1146.  
  1147. Definition at line  of file NUC123.h.
  1148.  
  1149. #define CLK_PWRCON_PWR_DOWN_EN_Msk   (1ul << CLK_PWRCON_PWR_DOWN_EN_Pos) 
  1150.  
  1151. CLK_T::PWRCON: PWR_DOWN_EN Mask 
  1152.  
  1153. Definition at line  of file NUC123.h.
  1154.  
  1155. #define CLK_PWRCON_PWR_DOWN_EN_Pos   7 
  1156.  
  1157. CLK_T::PWRCON: PWR_DOWN_EN Position 
  1158.  
  1159. Definition at line  of file NUC123.h.
  1160.  
  1161. #define CLK_PWRCON_XTL12M_EN_Msk   (1ul << CLK_PWRCON_XTL12M_EN_Pos) 
  1162.  
  1163. CLK_T::PWRCON: XTL12M_EN Mask 
  1164.  
  1165. Definition at line  of file NUC123.h.
  1166.  
  1167. #define CLK_PWRCON_XTL12M_EN_Pos   0 
  1168.  
  1169. CLK_T::PWRCON: XTL12M_EN Position 
  1170.  
  1171. Definition at line  of file NUC123.h.

#include <NUC123.h>

Data Fields
__IO uint32_t  PWRCON
 
__IO uint32_t  AHBCLK
 
__IO uint32_t  APBCLK
 
__IO uint32_t  CLKSTATUS
 
__IO uint32_t  CLKSEL0
 
__IO uint32_t  CLKSEL1
 
__IO uint32_t  CLKDIV
 
__IO uint32_t  CLKSEL2
 
__IO uint32_t  PLLCON
 
__IO uint32_t  FRQDIV
 
__I uint32_t  RESERVE0
 
__IO uint32_t  APBDIV
 

Detailed Description

Definition at line 401 of file NUC123.h.

Field Documentation

CLK_T::AHBCLK

Offset: 0x04 AHB Devices Clock Enable Control Register

Bits Field Descriptions
[1] PDMA_EN PDMA Controller Clock Enable Control
0 = PDMA peripheral clock Disabled.
1 = PDMA peripheral clock Enabled.
[2] ISP_EN Flash ISP Controller Clock Enable Control
0 = Flash ISP peripheral clock Disabled.
1 = Flash ISP peripheral clock Enabled.

Definition at line 762 of file NUC123.h.

CLK_T::APBCLK

Offset: 0x08 APB Devices Clock Enable Control Register

Bits Field Descriptions
[0] WDT_EN Watchdog Timer Clock Enable Control (Write Protect)
0 = Watchdog Timer clock Disabled.
1 = Watchdog Timer clock Enabled.
Note: This bit is write protected bit. Refer to the REGWRPROT register.
[2] TMR0_EN Timer0 Clock Enable Control
0 = Timer0 clock Disabled.
1 = Timer0 clock Enabled.
[3] TMR1_EN Timer1 Clock Enable Control
0 = Timer1 clock Disabled.
1 = Timer1 clock Enabled.
[4] TMR2_EN Timer2 Clock Enable Control
0 = Timer2 clock Disabled.
1 = Timer2 clock Enabled.
[5] TMR3_EN Timer3 Clock Enable Control
0 = Timer3 clock Disabled.
1 = Timer3 clock Enabled.
[6] FDIV_EN Frequency Divider Output Clock Enable Control
0 = FDIV clock Disabled.
1 = FDIV clock Enabled.
[8] I2C0_EN I2C0 Clock Enable Control
0 = I2C0 clock Disabled.
1 = I2C0 clock Enabled.
[9] I2C1_EN I2C1 Clock Enable Control
0 = I2C1 clock Disabled.
1 = I2C1 clock Enabled.
[12] SPI0_EN SPI0 Clock Enable Control
0 = SPI0 clock Disabled.
1 = SPI0 clock Enabled.
[13] SPI1_EN SPI1 Clock Enable Control
0 = SPI1 clock Disabled.
1 = SPI1 clock Enabled.
[14] SPI2_EN SPI2 Clock Enable Control
0 = SPI2 clock Disabled.
1 = SPI2 clock Enabled.
[16] UART0_EN UART0 Clock Enable Control
0 = UART0 clock Disabled.
1 = UART0 clock Enabled.
[17] UART1_EN UART1 Clock Enable Control
0 = UART1 clock Disabled.
1 = UART1 clock Enabled.
[20] PWM01_EN PWM_01 Clock Enable Control
0 = PWM01 clock Disabled.
1 = PWM01 clock Enabled.
[21] PWM23_EN PWM_23 Clock Enable Control
0 = PWM23 clock Disabled.
1 = PWM23 clock Enabled.
[27] USBD_EN USB 2.0 FS Device Controller Clock Enable Control
0 = USB clock Disabled.
1 = USB clock Enabled.
[28] ADC_EN Analog-Digital-Converter (ADC) Clock Enable Control
0 = ADC clock Disabled.
1 = ADC clock Enabled.
[29] I2S_EN I2S Clock Enable Control
0 = I2S clock Disabled.
1 = I2S clock Enabled.
[31] PS2_EN PS/2 Clock Enable Control
0 = PS/2 clock Disabled.
1 = PS/2 clock Enabled.

Definition at line 763 of file NUC123.h.

CLK_T::APBDIV

Offset: 0x2C APB Divider Control Register

Bits Field Descriptions
[0] APBDIV APB Divider Enable Bit
0 = PCLK is HCLK.
1 = PCLK is HCLK/2.

Definition at line 772 of file NUC123.h.

CLK_T::CLKDIV

Offset: 0x18 Clock Divider Number Register

Bits Field Descriptions
[3:0] HCLK_N HCLK Clock Divide Number From HCLK Clock Source
HCLK clock frequency = (HCLK clock source frequency) / (HCLK_N + 1).
[7:4] USB_N USB Clock Divide Number From PLL Clock
USB clock frequency = (PLL frequency) / (USB_N + 1).
[11:8] UART_N UART Clock Divide Number From UART Clock Source
UART clock frequency = (UART clock source frequency) / (UART_N + 1).
[23:16] ADC_N ADC Clock Divide Number From ADC Clock Source
ADC clock frequency = (ADC clock source frequency) / (ADC_N + 1).

Definition at line 767 of file NUC123.h.

CLK_T::CLKSEL0

Offset: 0x10 Clock Source Select Control Register 0

Bits Field Descriptions
[2:0] HCLK_S HCLK Clock Source Select (Write Protect)
The 3-bit default value is reloaded from the value of CFOSC (CONFIG0[26:24]) in user configuration register of Flash controller by any reset.
Therefore the default value is either 000b or 111b.
000 = Clock source from external 4~24 MHz high speed crystal oscillator clock.
001 = Clock source from PLL/2 clock.
010 = Clock source from PLL clock.
011 = Clock source from internal 10 kHz low speed oscillator clock.
111 = Clock source from internal 22.1184 MHz high speed oscillator clock.
Note1: Before clock switching, the related clock sources (both pre-select and new-select) must be turn on.
Note2: These bits are write protected bit. Refer to the REGWRPROT register.
[5:3] STCLK_S Cortex-M0 SysTick Clock Source Select (Write Protect)
If SYST_CSR[2] = 1, SysTick clock source is from HCLK.
If SYST_CSR[2] = 0, SysTick clock source is defined by STCLK_S(CLKSEL0[5:3]).
000 = Clock source from external 4~24 MHz high speed crystal clock.
010 = Clock source from external 4~24 MHz high speed crystal clock/2.
011 = Clock source from HCLK/2.
111 = Clock source from internal 22.1184 MHz high speed oscillator clock/2.
Note1: If SysTick clock source is not from HCLK (i.e. SYST_CSR[2] = 0), SysTick clock source must less than or equal to HCLK/2.
Note2: These bits are write protected bit. Refer to the REGWRPROT register.

Definition at line 765 of file NUC123.h.

CLK_T::CLKSEL1

Offset: 0x14 Clock Source Select Control Register 1

Bits Field Descriptions
[1:0] WDT_S Watchdog Timer Clock Source Select (Write Protect)
10 = Clock source from HCLK/2048 clock.
11 = Clock source from internal 10 kHz low speed oscillator clock.
Note: These bits are write protected bit. Refer to the REGWRPROT register.
[3:2] ADC_S ADC Clock Source Select
00 = Clock source from external 4~24 MHz high speed crystal oscillator clock.
01 = Clock source from PLL clock.
10 = Clock source from HCLK.
11 = Clock source from internal 22.1184 MHz high speed oscillator clock.
[4] SPI0_S SPI0 Clock Source Selection
0 = Clock source from PLL clock.
1 = Clock source from HCLK.
[5] SPI1_S SPI1 Clock Source Selection
0 = Clock source from PLL clock.
1 = Clock source from HCLK.
[6] SPI2_S SPI2 Clock Source Selection
0 = Clock source from PLL clock.
1 = Clock source from HCLK.
[10:8] TMR0_S TIMER0 Clock Source Selection
000 = Clock source from external 4~24 MHz high speed crystal clock.
010 = Clock source from HCLK.
011 = Clock source from external trigger.
101 = Clock source from internal 10 kHz low speed oscillator clock.
111 = Clock source from internal 22.1184 MHz high speed oscillator clock.
Others = Reserved.
[14:12] TMR1_S TIMER1 Clock Source Selection
000 = Clock source from external 4~24 MHz high speed crystal clock.
010 = Clock source from HCLK.
011 = Clock source from external trigger.
101 = Clock source from internal 10 kHz low speed oscillator clock.
111 = Clock source from internal 22.1184 MHz high speed oscillator clock.
Others = Reserved.
[18:16] TMR2_S TIMER2 Clock Source Selection
000 = Clock source from external 4~24 MHz high speed crystal clock.
010 = Clock source from HCLK.
011 = Clock source from external trigger.
101 = Clock source from internal 10 kHz low speed oscillator clock.
111 = Clock source from internal 22.1184 MHz high speed oscillator clock.
Others = Reserved.
[22:20] TMR3_S TIMER3 Clock Source Selection
000 = Clock source from external 4~24 MHz high speed crystal clock.
010 = Clock source from HCLK.
011 = Reserved.
101 = Clock source from internal 10 kHz low speed oscillator clock.
111 = Clock source from internal 22.1184 MHz high speed oscillator clock.
Others = Reserved.
[25:24] UART_S UART Clock Source Selection
00 = Clock source from external 4~24 MHz high speed crystal oscillator clock.
01 = Clock source from PLL clock.
11 = Clock source from internal 22.1184 MHz high speed oscillator clock.
[29:28] PWM01_S PWM0 and PWM1 Clock Source Selection
PWM0 and PWM1 used the same clock source; both of them used the same prescaler.
The clock source of PWM0 and PWM1 is defined by PWM01_S (CLKSEL1[29:28]) and PWM01_S_E (CLKSEL2[8]).
If PWM01_S_E = 0, the clock source of PWM0 and PWM1 defined by PWM01_S list below:
00 = Clock source from external 4~24 MHz high speed crystal oscillator clock.
10 = Clock source from HCLK.
11 = Clock source from internal 22.1184 MHz high speed oscillator clock.
If PWM01_S_E = 1, the clock source of PWM0 and PWM1 defined by PWM01_S list below:
00 = Reserved.
01 = Reserved.
10 = Reserved.
11 = Clock source from internal 10 kHz low speed oscillator clock.
[31:30] PWM23_S PWM2 and PWM3 Clock Source Selection
PWM2 and PWM3 used the same clock source; both of them used the same prescaler.
The clock source of PWM2 and PWM3 is defined by PWM23_S (CLKSEL1[31:30]) and PWM23_S_E (CLKSEL2[9]).
If PWM23_S_E = 0, theclock source of PWM2 and PWM3 defined by PWM23_S list below:
00 = Clock source from external 4~24 MHz high speed crystal oscillator clock.
10 = Clock source from HCLK.
11 = Clock source from internal 22.1184 MHz high speed oscillator clock.
If PWM23_S_E = 1, the clock source of PWM2 and PWM3 defined by PWM23_S list below:
00 = Reserved.
01 = Reserved.
10 = Reserved.
11 = Clock source from internal 10 kHz low speed oscillator clock.

Definition at line 766 of file NUC123.h.

CLK_T::CLKSEL2

Offset: 0x1C Clock Source Select Control Register 2

Bits Field Descriptions
[1:0] I2S_S I2S Clock Source Selection
00 = Clock source from external 4~24 MHz high speed crystal oscillator clock.
01 = Clock source from PLL clock.
10 = Clock source from HCLK.
11 = Clock source from internal 22.1184 MHz high speed oscillator clock.
[3:2] FRQDIV_S Clock Divider Clock Source Selection
00 = Clock source from external 4~24 MHz high speed crystal oscillator clock.
10 = Clock source from HCLK.
11 = Clock source from internal 22.1184 MHz high speed oscillator clock.
[8] PWM01_S_E PWM0 and PWM1 Clock Source Selection Extend
PWM0 and PWM1 used the same clock source; both of them used the same prescaler.
The clock source of PWM0 and PWM1 is defined by PWM01_S (CLKSEL1[29:28]) and PWM01_S_E (CLKSEL2[8]).
If PWM01_S_E = 0, the clock source of PWM0 and PWM1 defined by PWM01_S list below:
00 = Clock source from external 4~24 MHz high speed crystal oscillator clock.
10 = Clock source from HCLK.
11 = Clock source from internal 22.1184 MHz high speed oscillator clock.
If PWM01_S_E = 1, the clock source of PWM0 and PWM1 defined by PWM01_S list below:
00 = Reserved.
01 = Reserved.
10 = Reserved.
11 = Clock source from internal 10 kHz low speed oscillator clock.
[9] PWM23_S_E PWM2 and PWM3 Clock Source Selection Extend
PWM2 and PWM3 used the same clock source; both of them used the same prescaler.
The clock source of PWM2 and PWM3 is defined by PWM23_S (CLKSEL1[31:30]) and PWM23_S_E (CLKSEL2[9]).
If PWM23_S_E = 0, the clock source of PWM2 and PWM3 defined by PWM23_S list below:
00 = Clock source from external 4~24 MHz high speed crystal oscillator clock.
10 = Clock source from HCLK.
11 = Clock source from internal 22.1184 MHz high speed oscillator clock.
If PWM23_S_E = 1, the clock source of PWM2 and PWM3 defined by PWM23_S list below:
00 = Reserved.
01 = Reserved.
10 = Reserved.
11 = Clock source from internal 10 kHz low speed oscillator clock.
[17:16] WWDT_S Window Watchdog Timer Clock Source Selection
10 = Clock source from HCLK/2048 clock.
11 = Clock source from internal 10 kHz low speed oscillator clock.

Definition at line 768 of file NUC123.h.

CLK_T::CLKSTATUS

Offset: 0x0C Clock status monitor Register

Bits Field Descriptions
[0] XTL12M_STB External 4~24 MHz High Speed Crystal (HXT) Clock Source Stable Flag (Read Only)
0 = External 4~24 MHz high speed crystal clock (HXT) is not stable or disabled.
1 = External 4~24 MHz high speed crystal clock (HXT) is stable and enabled.
[2] PLL_STB Internal PLL Clock Source Stable Flag (Read Only)
0 = Internal PLL clock is not stable or disabled.
1 = Internal PLL clock is stable in normal mode.
[3] OSC10K_STB Internal 10 KHz Low Speed Oscillator (LIRC) Clock Source Stable Flag (Read Only)
0 = Internal 10 kHz low speed oscillator clock (LIRC) is not stable or disabled.
1 = Internal 10 kHz low speed oscillator clock (LIRC) is stable and enabled.
[4] OSC22M_STB Internal 22.1184 MHz High Speed Oscillator (HIRC) Clock Source Stable Flag (Read Only)
0 = Internal 22.1184 MHz high speed oscillator (HIRC) clock is not stable or disabled.
1 = Internal 22.1184 MHz high speed oscillator (HIRC) clock is stable and enabled.
[7] CLK_SW_FAIL Clock Switching Fail Flag
This bit is updated when software switches system clock source.
If switch target clock is stable, this bit will be set to 0.
If switch target clock is not stable, this bit will be set to 1.
0 = Clock switching success.
1 = Clock switching failure.
Note1: On NUC123xxxANx, this bit can be cleared to 0 by software writing "1".
Note2: On NUC123xxxAEx, this bit is read only. After selected clock source is stable, hardware will switch system clock to selected clock automatically, and CLK_SW_FAIL will be cleared automatically by hardware.

Definition at line 764 of file NUC123.h.

CLK_T::FRQDIV

Offset: 0x24 Frequency Divider Control Register

Bits Field Descriptions
[3:0] FSEL Divider Output Frequency Selection Bits
The formula of output frequency is Fout = Fin/2(N+1).
Fin is the input clock frequency.
Fout is the frequency of divider output clock.
N is the 4-bit value of FSEL[3:0].
[4] DIVIDER_EN Frequency Divider Enable Bit
0 = Frequency Divider function Disabled.
1 = Frequency Divider function Enabled.

Definition at line 770 of file NUC123.h.

CLK_T::PLLCON

Offset: 0x20 PLL Control Register

Bits Field Descriptions
[8:0] FB_DV PLL Feedback Divider Control Bits
Refer to the PLL formulas.
[13:9] IN_DV PLL Input Divider Control Bits
Refer to the PLL formulas.
[15:14] OUT_DV PLL Output Divider Control Bits
Refer to the PLL formulas.
[16] PD Power-down Mode
If the PWR_DOWN_EN bit is set to 1 in PWRCON register, the PLL will enter Power-down mode too.
0 = PLL is in Normal mode.
1 = PLL is in Power-down mode (default).
[17] BP PLL Bypass Control
0 = PLL is in Normal mode (default).
1 = PLL clock output is same as PLL source clock input.
[18] OE PLL OE (FOUT Enable) Control
0 = PLL FOUT Enabled.
1 = PLL FOUT is fixed low.
[19] PLL_SRC PLL Source Clock Selection
0 = PLL source clock from external 4~24 MHz high speed crystal.
1 = PLL source clock from internal 22.1184 MHz high speed oscillator.

Definition at line 769 of file NUC123.h.

CLK_T::PWRCON

Offset: 0x00 System Power-down Control Register

Bits Field Descriptions
[0] XTL12M_EN External 4~24 MHz High Speed Crystal Enable (HXT) Control (Write Protect)
The bit default value is set by flash controller user configuration register CFOSC (Config0[26:24]).
When the default clock source is from external 4~24 MHz high speed crystal, this bit is set to 1 automatically.
0 = External 4~24 MHz high speed crystal oscillator (HXT) Disabled.
1 = External 4~24 MHz high speed crystal oscillator (HXT) Enabled.
Note: This bit is write protected bit. Refer to the REGWRPROT register.
[2] OSC22M_EN Internal 22.1184 MHz High Speed Oscillator (HIRC) Enable Control (Write Protect)
0 = Internal 22.1184 MHz high speed oscillator (HIRC) Disabled.
1 = Internal 22.1184 MHz high speed oscillator (HIRC) Enabled.
Note: This bit is write protected bit. Refer to the REGWRPROT register.
[3] OSC10K_EN Internal 10 KHz Low Speed Oscillator (LIRC) Enable Control (Write Protect)
0 = Internal 10 kHz low speed oscillator (LIRC) Disabled.
1 = Internal 10 kHz low speed oscillator (LIRC) Enabled.
Note: This bit is write protected bit. Refer to the REGWRPROT register.
[4] PD_WU_DLY Wake-up Delay Counter Enable Control (Write Protect)
When the chip wakes up from Power-down mode, the clock control will delay certain clock cycles to wait system clock stable.
The delayed clock cycle is 4096 clock cycles when chip work at external 4~24 MHz high speed crystal, and 256 clock cycles when chip work at internal 22.1184 MHz high speed oscillator.
0 = Clock cycles delay Disabled.
1 = Clock cycles delay Enabled.
Note: This bit is write protected bit. Refer to the REGWRPROT register.
[5] PD_WU_INT_EN Power-Down Mode Wake-Up Interrupt Enable Control (Write Protect)
0 = Power-down mode wake-up interrupt Disabled.
1 = Power-down mode wake-up interrupt Enabled.
Note1: The interrupt will occur when both PD_WU_STS and PD_WU_INT_EN are high.
Note2: This bit is write protected bit. Refer to the REGWRPROT register.
[6] PD_WU_STS Power-down Mode Wake-Up Interrupt Status
Set by "Power-down wake-up event", it indicates that resume from Power-down mode.
The flag is set if the GPIO, USB, UART, WDT, TIMER, I2C or BOD wake-up occurred.
This bit can be cleared to 0 by software writing "1".
Note: This bit is working only if PD_WU_INT_EN (PWRCON[5]) set to 1.
[7] PWR_DOWN_EN System Power-down Enable Bit (Write Protect)
When this bit is set to 1, Power-down mode is enabled and chip Power-down behavior will depends on the PD_WAIT_CPU bit
(a) If the PD_WAIT_CPU is 0, then the chip enters Power-down mode immediately after the PWR_DOWN_EN bit set.
(b) if the PD_WAIT_CPU is 1, then the chip keeps active till the CPU sleep mode is also active and then the chip enters Power-down mode (recommend)
When chip wakes up from Power-down mode, this bit is cleared by hardware.
User needs to set this bit again for next Power-down.
In Power-down mode, 4~24 MHz external high speed crystal oscillator (HXT) and the 22.1184 MHz internal high speed RC oscillator (HIRC) will be disabled in this mode, but the 10 kHz internal low speed RC oscillator (LIRC) is not controlled by Power-down mode.
In Power- down mode, the PLL and system clock are disabled, and ignored the clock source selection. The clocks of peripheral are not controlled by Power-down mode, if the peripheral clock source is from the 10 kHz internal low speed RC oscillator (LIRC).
The clocks of peripheral are not controlled by Power-down mode, if the peripheral clock source is from the internal 10 kHz low speed oscillator.
0 = Chip operating normally or chip in Idle mode because of WFI command.
1 = Chip enters Power-down mode instantly or waits CPU sleep command WFI.
Note: This bit is write protected bit. Refer to the REGWRPROT register.
[8] PD_WAIT_CPU This Bit Control The Power-Down Entry Condition (Write Protect)
0 = Chip enters Power-down mode when the PWR_DOWN_EN bit is set to 1.
1 = Chip enters Power-down mode when the both PD_WAIT_CPU and PWR_DOWN_EN bits are set to 1 and CPU run WFI instruction.
Note: This bit is write protected bit. Refer to the REGWRPROT register.

Definition at line 761 of file NUC123.h.

__I uint32_t CLK_T::RESERVE0

Definition at line 771 of file NUC123.h.

The documentation for this struct was generated from the following file:
D:/MCU/FA8248/NUC123BSPv3/Library/Device/Nuvoton/NUC123/Include/NUC123.h
 
  1. /**************************************************************************//**
  2.  * @file     mainS.c
  3.  * @version  V2.00
  4.  * $Revision: 4 $
  5.  * $Date: 14/01/28 11:44a $
  6.  * @brief    NUC029 Series Global Control and Clock Control Driver Sample Code
  7.  *
  8.  * @note
  9.  * Copyright (C) 2011 Nuvoton Technology Corp. All rights reserved.
  10.  *
  11.  ******************************************************************************/
  12. #include <stdio.h>
  13. #include "NUC029xAN.h"
  14.  
  15. #define PLLCON_SETTING  CLK_PLLCON_50MHz_HXT
  16. #define PLL_CLOCK       50000000
  17.  
  18. #define SIGNATURE       0x125ab234
  19. #define FLAG_ADDR       0x20000FFC
  20.  
  21. /*---------------------------------------------------------------------------------------------------------*/
  22. /*  Brown Out Detector IRQ Handler                                                                         */
  23. /*---------------------------------------------------------------------------------------------------------*/
  24. void BOD_IRQHandler(void)
  25. {
  26.     /* Clear BOD Interrupt Flag */
  27.     SYS_CLEAR_BOD_INT_FLAG();
  28.  
  29.     printf("Brown Out is Detected\n");
  30. }
  31.  
  32. /*---------------------------------------------------------------------------------------------------------*/
  33. /*  Simple calculation test function                                                                       */
  34. /*---------------------------------------------------------------------------------------------------------*/
  35. #define PI_NUM  256
  36. int32_t f[PI_NUM + ];
  37. uint32_t piTbl[] =
  38. {
  39.     ,
  40.     ,
  41.     ,
  42.     ,
  43.     ,
  44.     ,
  45.     ,
  46.     ,
  47.     ,
  48.     ,
  49.     ,
  50.     ,
  51.     ,
  52.     ,
  53.     ,
  54.     ,
  55.     ,
  56.     ,
  57.  
  58. };
  59.  
  60. int32_t piResult[];
  61.  
  62. int32_t pi(void)
  63. {
  64.     int32_t i, i32Err;
  65.     int32_t a = , b = , c = PI_NUM, d = , e = , g = ;
  66.  
  67.     for(; b - c;)
  68.         f[b++] = a / ;
  69.  
  70.     i = ;
  71.     for(; d = , g = c * ; c -= ,/*printf("%.4d\n",e+d/a),*/ piResult[i++] = e + d / a, e = d % a)
  72.     {
  73.         if(i == )
  74.             break;
  75.  
  76.         for(b = c; d += f[b] * a, f[b] = d % --g, d /= g--, --b; d *= b);
  77.     }
  78.     i32Err = ;
  79.     for(i = ; i < ; i++)
  80.     {
  81.         if(piTbl[i] != piResult[i])
  82.             i32Err = -;
  83.     }
  84.  
  85.     return i32Err;
  86. }
  87.  
  88. void Delay(uint32_t x)
  89. {
  90.     int32_t i;
  91.  
  92.     for(i = ; i < x; i++)
  93.     {
  94.         __NOP();
  95.         __NOP();
  96.     }
  97. }
  98.  
  99. uint32_t g_au32PllSetting[] =
  100. {
  101.     CLK_PLLCON_PLL_SRC_HXT | CLK_PLLCON_NR() | CLK_PLLCON_NF() | CLK_PLLCON_NO_4,  /* PLL = 25MHz */
  102.     CLK_PLLCON_PLL_SRC_HXT | CLK_PLLCON_NR() | CLK_PLLCON_NF() | CLK_PLLCON_NO_4,  /* PLL = 29MHz */
  103.     CLK_PLLCON_PLL_SRC_HXT | CLK_PLLCON_NR() | CLK_PLLCON_NF() | CLK_PLLCON_NO_4,  /* PLL = 33MHz */
  104.     CLK_PLLCON_PLL_SRC_HXT | CLK_PLLCON_NR() | CLK_PLLCON_NF() | CLK_PLLCON_NO_4,  /* PLL = 37MHz */
  105.     CLK_PLLCON_PLL_SRC_HXT | CLK_PLLCON_NR() | CLK_PLLCON_NF() | CLK_PLLCON_NO_4,  /* PLL = 41MHz */
  106.     CLK_PLLCON_PLL_SRC_HXT | CLK_PLLCON_NR() | CLK_PLLCON_NF() | CLK_PLLCON_NO_4,  /* PLL = 45MHz */
  107.     CLK_PLLCON_PLL_SRC_HXT | CLK_PLLCON_NR() | CLK_PLLCON_NF() | CLK_PLLCON_NO_4   /* PLL = 49MHz */
  108. };
  109.  
  110. void SYS_PLL_Test(void)
  111. {
  112.     int32_t  i;
  113.  
  114.     /*---------------------------------------------------------------------------------------------------------*/
  115.     /* PLL clock configuration test                                                                             */
  116.     /*---------------------------------------------------------------------------------------------------------*/
  117.  
  118.     printf("\n-------------------------[ Test PLL ]-----------------------------\n");
  119.  
  120.     for(i = ; i < sizeof(g_au32PllSetting) / sizeof(g_au32PllSetting[]) ; i++)
  121.     {
  122.         /* Switch HCLK clock source to HXT and HCLK source divide 1 */
  123.         CLK->CLKSEL0 &= ~CLK_CLKSEL0_HCLK_S_Msk;
  124.         CLK->CLKSEL0 |= CLK_CLKSEL0_HCLK_S_HXT;
  125.         CLK->CLKDIV &= ~CLK_CLKDIV_HCLK_N_Msk;
  126.         CLK->CLKDIV |= (CLK_CLKDIV_HCLK() << CLK_CLKDIV_HCLK_N_Msk);
  127.  
  128.         /* Set PLL to power down mode and PLL_STB bit in CLKSTATUS register will be cleared by hardware. */
  129.         CLK->PLLCON &= ~CLK_PLLCON_PD_Msk;
  130.  
  131.         /* Set PLL frequency */
  132.         CLK->PLLCON = g_au32PllSetting[i];
  133.  
  134.         /* Waiting for PLL clock ready */
  135.         while(!(CLK->CLKSTATUS & CLK_CLKSTATUS_PLL_STB_Msk));
  136.  
  137.         /* Switch HCLK clock source to PLL */
  138.         CLK->CLKSEL0 &= (~CLK_CLKSEL0_HCLK_S_Msk);
  139.         CLK->CLKSEL0 |= CLK_CLKSEL0_HCLK_S_PLL;
  140.  
  141.         /* Update System Core Clock */
  142.         SystemCoreClockUpdate();
  143.  
  144.         printf("  Change system clock to %d Hz ...................... ", SystemCoreClock);
  145.  
  146.         /* Enable CKO clock source */
  147.         CLK->APBCLK |= CLK_APBCLK_FDIV_EN_Msk;
  148.  
  149.         /* CKO = clock source / 2^(1 + 1) */
  150.         CLK->FRQDIV = CLK_FRQDIV_DIVIDER_EN_Msk | ();
  151.  
  152.         /* Select CKO clock source as HCLK */
  153.         CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_FRQDIV_S_Msk)) | CLK_CLKSEL2_FRQDIV_S_HCLK;
  154.  
  155.         /* The delay loop is used to check if the CPU speed is increasing */
  156.         Delay(0x400000);
  157.  
  158.         if(pi())
  159.         {
  160.             printf("[FAIL]\n");
  161.         }
  162.         else
  163.         {
  164.             printf("[OK]\n");
  165.         }
  166.  
  167.         /* Disable CKO clock */
  168.         CLK->APBCLK &= (~CLK_APBCLK_FDIV_EN_Msk);
  169.     }
  170. }
  171.  
  172. void SYS_Init(void)
  173. {
  174.  
  175.     /*---------------------------------------------------------------------------------------------------------*/
  176.     /* Init System Clock                                                                                       */
  177.     /*---------------------------------------------------------------------------------------------------------*/
  178.  
  179.     /* Enable Internal RC 22.1184MHz clock */
  180.     CLK->PWRCON |= CLK_PWRCON_OSC22M_EN_Msk;
  181.  
  182.     /* Waiting for Internal RC clock ready */
  183.     while(!(CLK->CLKSTATUS & CLK_CLKSTATUS_OSC22M_STB_Msk));
  184.  
  185.     /* Switch HCLK clock source to Internal RC and and HCLK source divide 1 */
  186.     CLK->CLKSEL0 &= ~CLK_CLKSEL0_HCLK_S_Msk;
  187.     CLK->CLKSEL0 |= CLK_CLKSEL0_HCLK_S_HIRC;
  188.     CLK->CLKDIV &= ~CLK_CLKDIV_HCLK_N_Msk;
  189.     CLK->CLKDIV |= (CLK_CLKDIV_HCLK() << CLK_CLKDIV_HCLK_N_Msk);
  190.  
  191.     /* Enable external XTAL 12MHz clock */
  192.     CLK->PWRCON |= CLK_PWRCON_XTL12M_EN_Msk;
  193.  
  194.     /* Waiting for external XTAL clock ready */
  195.     while(!(CLK->CLKSTATUS & CLK_CLKSTATUS_XTL12M_STB_Msk));
  196.  
  197.     /* Set core clock as PLL_CLOCK from PLL */
  198.     CLK->PLLCON = PLLCON_SETTING;
  199.     while(!(CLK->CLKSTATUS & CLK_CLKSTATUS_PLL_STB_Msk));
  200.     CLK->CLKSEL0 &= (~CLK_CLKSEL0_HCLK_S_Msk);
  201.     CLK->CLKSEL0 |= CLK_CLKSEL0_HCLK_S_PLL;
  202.  
  203.     /* Update System Core Clock */
  204.     /* User can use SystemCoreClockUpdate() to calculate PllClock, SystemCoreClock and CycylesPerUs automatically. */
  205.     //SystemCoreClockUpdate();
  206.     PllClock        = PLL_CLOCK;            // PLL
  207.     SystemCoreClock = PLL_CLOCK / ;        // HCLK
  208.     CyclesPerUs     = PLL_CLOCK / ;  // For SYS_SysTickDelay()
  209.  
  210.     /* Enable UART module clock */
  211.     CLK->APBCLK |= CLK_APBCLK_UART0_EN_Msk;
  212.  
  213.     /* Select UART module clock source */
  214.     CLK->CLKSEL1 &= ~CLK_CLKSEL1_UART_S_Msk;
  215.     CLK->CLKSEL1 |= CLK_CLKSEL1_UART_S_HXT;
  216.  
  217.     /*---------------------------------------------------------------------------------------------------------*/
  218.     /* Init I/O Multi-function                                                                                 */
  219.     /*---------------------------------------------------------------------------------------------------------*/
  220.  
  221.     /* Set P3 multi-function pins for UART0 RXD , TXD and CKO */
  222.     SYS->P3_MFP &= ~(SYS_MFP_P30_Msk | SYS_MFP_P31_Msk  | SYS_MFP_P36_Msk);
  223.     SYS->P3_MFP |= (SYS_MFP_P30_RXD0 | SYS_MFP_P31_TXD0 | SYS_MFP_P36_CKO);
  224.  
  225. }
  226.  
  227. void UART0_Init()
  228. {
  229.     /*---------------------------------------------------------------------------------------------------------*/
  230.     /* Init UART                                                                                               */
  231.     /*---------------------------------------------------------------------------------------------------------*/
  232.     /* Reset UART IP */
  233.     SYS->IPRSTC2 |=  SYS_IPRSTC2_UART0_RST_Msk;
  234.     SYS->IPRSTC2 &= ~SYS_IPRSTC2_UART0_RST_Msk;
  235.  
  236.     /* Configure UART0 and set UART0 Baudrate */
  237.     UART0->BAUD = UART_BAUD_MODE2 | UART_BAUD_MODE2_DIVIDER(__HXT, );
  238.     UART0->LCR = UART_WORD_LEN_8 | UART_PARITY_NONE | UART_STOP_BIT_1;
  239. }
  240.  
  241. /*---------------------------------------------------------------------------------------------------------*/
  242. /*  Main Function                                                                                          */
  243. /*---------------------------------------------------------------------------------------------------------*/
  244. int32_t main(void)
  245. {
  246.     uint32_t u32data;
  247.  
  248.     /* If define INIT_SYSCLK_AT_BOOTING in system_NUC029xAN.h, HCLK will be set to 50MHz in SystemInit(void). */
  249.     /* In end of main function, program issued CPU reset and write-protection will be disabled. */
  250.     if(SYS->REGWRPROT == )
  251.         SYS->REGWRPROT = 0x0;
  252.  
  253.     /* Unlock protected registers */
  254.     SYS->REGWRPROT = 0x59;
  255.     SYS->REGWRPROT = 0x16;
  256.     SYS->REGWRPROT = 0x88;
  257.  
  258.     /* Init System, IP clock and multi-function I/O */
  259.     SYS_Init();
  260.  
  261.     /* Lock protected registers */
  262.     SYS->REGWRPROT = 0x0;
  263.  
  264.     /* Init UART0 for printf */
  265.     UART0_Init();
  266.  
  267.     printf("\n\nCPU @ %dHz\n", SystemCoreClock);
  268.  
  269.     /*
  270.         This sample code will show some function about system manager controller and clock controller:
  271.         1. Read PDID
  272.         2. Get and clear reset source
  273.         3. Setting about BOD
  274.         4. Change system clock depended on different PLL settings
  275.         5. Output system clock from CKO pin, and the output frequency = system clock / 4
  276.     */
  277.  
  278.     printf("+---------------------------------------+\n");
  279.     printf("|        System Driver Sample Code      |\n");
  280.     printf("+---------------------------------------+\n");
  281.  
  282.     if(M32(FLAG_ADDR) == SIGNATURE)
  283.     {
  284.         printf("  CPU Reset success!\n");
  285.         M32(FLAG_ADDR) = ;
  286.         printf("  Press any key to continue ...\n");
  287.         getchar();
  288.     }
  289.  
  290.     /*---------------------------------------------------------------------------------------------------------*/
  291.     /* Misc system function test                                                                               */
  292.     /*---------------------------------------------------------------------------------------------------------*/
  293.  
  294.     /* Read Part Device ID */
  295.     printf("Product ID 0x%x\n", SYS->PDID);
  296.  
  297.     /* Get reset source from last operation */
  298.     u32data = SYS->RSTSRC;
  299.     printf("Reset Source 0x%x\n", u32data);
  300.  
  301.     /* Clear reset source */
  302.     SYS->RSTSRC = u32data;
  303.  
  304.     /* Unlock protected registers for Brown-Out Detector settings */
  305.     SYS->REGWRPROT = 0x59;
  306.     SYS->REGWRPROT = 0x16;
  307.     SYS->REGWRPROT = 0x88;
  308.  
  309.     /* Check if the write-protected registers are unlocked before BOD setting and CPU Reset */
  310.     if(SYS->REGWRPROT != )
  311.     {
  312.         printf("Protected Address is Unlocked\n");
  313.     }
  314.  
  315.     /* Enable Brown-Out Detector and Low Voltage Reset function, and set Brown-Out Detector voltage 2.7V */
  316.     SYS->BODCR = SYS_BODCR_BOD_EN_Msk | SYS_BODCR_BOD_VL_2_7V | SYS_BODCR_LVR_EN_Msk;
  317.  
  318.     /* Enable BOD IRQ */
  319.     NVIC_EnableIRQ(BOD_IRQn);
  320.  
  321.     /* Run PLL Test */
  322.     SYS_PLL_Test();
  323.  
  324.     /* Write a signature work to SRAM to check if it is reset by software */
  325.     M32(FLAG_ADDR) = SIGNATURE;
  326.     printf("\n\n  >>> Reset CPU <<<\n");
  327.  
  328.     /* Waiting for message send out */
  329.     while(!(UART0->FSR & UART_FSR_TE_FLAG_Msk));
  330.  
  331.     /* Switch HCLK clock source to Internal RC and and HCLK source divide 1 */
  332.     CLK->CLKSEL0 &= ~CLK_CLKSEL0_HCLK_S_Msk;
  333.     CLK->CLKSEL0 |= CLK_CLKSEL0_HCLK_S_HIRC;
  334.     CLK->CLKDIV &= ~CLK_CLKDIV_HCLK_N_Msk;
  335.     CLK->CLKDIV |= (CLK_CLKDIV_HCLK() << CLK_CLKDIV_HCLK_N_Msk);
  336.  
  337.     /* Set PLL to Power down mode and HW will also clear PLL_STB bit in CLKSTATUS register */
  338.     CLK->PLLCON &= ~CLK_PLLCON_PD_Msk;
  339.  
  340.     /* Reset CPU */
  341.     SYS->IPRSTC1 |= SYS_IPRSTC1_CPU_RST_Msk;
  342. }
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 

M0 M4关于库函数的讲解（以时钟为例）的更多相关文章

  1. M0 M4之UART初始化

    新唐的M0/M4 UART都有16级或者64级FIFO,用来缓存UART数据的收/发.例如:如果RX FIFO中断触发级别设为14,UART接收14个字节才会发生RDA(接收数据可得)中断.这样可以降 ...

  2. 新唐M0 M4系统初始化

    系统初始化包含了时钟(clock)初始化和多功能引脚(Multi Function Pin 简称MFP寄存器)配置.void SYS_Init(void) { /* 解锁保护寄存器 */ SYS_Un ...

  3. M0 M4之GPIO初始化

    新唐所有的M0/M4芯片基本上所有的IO都可以发生中断,为了符合大家的习惯还是有所谓的外部中断EINT0和EINT1.有2跟GPIO脚可以配置为EINT0功能和EINT1功能,分别将发生EINT0中断 ...

  4. M0 M4时钟控制（一）

    时钟控制器为整个芯片提供时钟源,包括系统时钟和所有外围设备时钟.该控制器还通过单独时钟的开或关,时钟源选择和分频器来进行功耗控制.在CPU使能低功耗PDEN(CLK_PWRCTL[7]) 位和Cort ...

  5. M0 M4之Timer初始化

    新唐的定时器一般有很多功能:普通的定时功能,事件计数功能,捕获功能,超时触发ADC等等.大家如果感兴趣可以读一下<NANOB Timer功能介绍以及在弱灌注中的应用.pdf>,虽然各个系列 ...

  6. 关于新塘 M0 M4添加库文件的说明

  7. STM32入门系列-STM32时钟系统，自定义系统时钟

    在时钟树的讲解中我们知道,通过修改PLLMUL中的倍系数值(2-16)可以改变系统的时钟频率.在库函数中也有对时钟倍频因子配置的函数,如下: void RCC_PLLConfig(uint32_t R ...

  8. 如何快速上手使用STM32库函数

    一.背景 如前文所述,利用标准库函数的好处在于,可以快速开发,不用去对着数据手册,小心翼翼的一位一位的配置那些繁复的寄存器,因为这些工作意法半导体已经找了一些顶级的工程师帮你做了,杰作既是其库函数.当 ...

  9. 32位汇编第二讲,编写窗口程序,加载资源,响应消息,以及调用C库函数

    32位汇编第二讲,编写窗口程序,加载资源,响应消息,以及调用C库函数 (如果想看所有代码,请下载课堂资料,里面有所有代码,这里会讲解怎么生成一个窗口程序) 一丶32位汇编编写Windows窗口程序 首 ...

随机推荐

  1. selenium之关于 chromedriver的安装和使用

    转自:https://blog.csdn.net/d77808675/article/details/79016271 最近在学习爬虫,用到了selenium 环境:Windows,python3 但 ...

  2. Zookeeper单机伪集群

    Zookeeper单机伪集群 1.配置 zookeeper下载地址:http://apache.mirrors.lucidnetworks.net/zookeeper/ 可以选择需要的版本,我下载的是 ...

  3. Nginx代理proxy pass配置去除前缀

    使用Nginx做代理的时候,可以简单的直接把请求原封不动的转发给下一个服务. 比如,访问abc.com/appv2/a/b.html, 要求转发到localhost:8088/appv2/a/b.ht ...

  4. receiving error: 'Error: SSL Error: SELF_SIGNED_CERT_IN_CHAIN' while using npm

    From:https://stackoverflow.com/questions/9626990/receiving-error-error-ssl-error-self-signed-cert-in ...

  5. VMware DHCP Service服务无法启动问题的解决

    我的电脑出现VMware DHCP Service和VMware NAT Service两个服务无法启动的问题: 打开VMware主界面,菜单->编辑->虚拟网络编辑器: 勾选上“将主机虚 ...

  6. 疯狂Java学习笔记（75）-----------NIO.2第一篇

    Java 7引入了NIO.2.NIO.2是继承自NIO框架,并添加了新的功能(比如:处理软链接和硬链接的功能).这篇帖子包含三个部分,我将使用NIO.2的一些演示样例.由此向大家演示NIO.2的基本用 ...

  7. 利用fstream进行文件拷贝测试

    今天翻到一个早期写测试代码的目录,找到几个以前的测试代码,于是拿出来贴到博客中.(只是简单的测试,并不严谨.注意这里windows和linux的硬件环境不一样) 这一个是使用fstream进行文件拷贝 ...

  8. ASP.NET MVC 一款可预览、裁剪头像上传组件

    今天介绍一款Web上常用的头像上传组件,常用于头像上传时对用户上传的图片进行裁剪并实时预览,最终效果如下: 源代码结构: Github地址: https://github.com/FrankFan/A ...

  9. synchronized和lock比较

    一.synchronized的实现方案 1.synchronized能够把任何一个非null对象当成锁,实现由两种方式: a.当synchronized作用于非静态方法时,锁住的是当前对象的事例,当s ...

  10. JS 动态生成JSON对象

    JS 动态生成JSON对象,一般用到JSON传递参数的时候,会用到. function onGeneratedRow(columnsResult) { var jsonData = {}; colum ...