ADC及DA的头文件复析
/************************************************************
* ADC12，，，，这么多的定义，搞得我都昏死啦，抽出来可能好几一些。。
************************************************************/
#define __MSP430_HAS_ADC12__ /* Definition to show that Module is available */
#define ADC12CTL0_ (0x01A0u) /* ADC12 Control 0 */
DEFW( ADC12CTL0 , ADC12CTL0_)
#define ADC12CTL1_ (0x01A2u) /* ADC12 Control 1 */
DEFW( ADC12CTL1 , ADC12CTL1_)
#define ADC12IFG_ (0x01A4u) /* ADC12 Interrupt Flag */
DEFW( ADC12IFG , ADC12IFG_)
#define ADC12IE_ (0x01A6u) /* ADC12 Interrupt Enable */
DEFW( ADC12IE , ADC12IE_)
#define ADC12IV_ (0x01A8u) /* ADC12 Interrupt Vector Word */
DEFW( ADC12IV , ADC12IV_)
#define ADC12MEM_ (0x0140u) /* ADC12 Conversion Memory */
#ifndef __IAR_SYSTEMS_ICC__
#define ADC12MEM (ADC12MEM_) /* ADC12 Conversion Memory (for assembler) */
#else
#define ADC12MEM ((int*) ADC12MEM_) /* ADC12 Conversion Memory (for C) */
#endif
#define ADC12MEM0_ (0x0140u) /* ADC12 Conversion Memory 0 */
DEFW( ADC12MEM0 , ADC12MEM0_)
#define ADC12MEM1_ (0x0142u) /* ADC12 Conversion Memory 1 */
DEFW( ADC12MEM1 , ADC12MEM1_)
#define ADC12MEM2_ (0x0144u) /* ADC12 Conversion Memory 2 */
DEFW( ADC12MEM2 , ADC12MEM2_)
#define ADC12MEM3_ (0x0146u) /* ADC12 Conversion Memory 3 */
DEFW( ADC12MEM3 , ADC12MEM3_)
#define ADC12MEM4_ (0x0148u) /* ADC12 Conversion Memory 4 */
DEFW( ADC12MEM4 , ADC12MEM4_)
#define ADC12MEM5_ (0x014Au) /* ADC12 Conversion Memory 5 */
DEFW( ADC12MEM5 , ADC12MEM5_)
#define ADC12MEM6_ (0x014Cu) /* ADC12 Conversion Memory 6 */
DEFW( ADC12MEM6 , ADC12MEM6_)
#define ADC12MEM7_ (0x014Eu) /* ADC12 Conversion Memory 7 */
DEFW( ADC12MEM7 , ADC12MEM7_)
#define ADC12MEM8_ (0x0150u) /* ADC12 Conversion Memory 8 */
DEFW( ADC12MEM8 , ADC12MEM8_)
#define ADC12MEM9_ (0x0152u) /* ADC12 Conversion Memory 9 */
DEFW( ADC12MEM9 , ADC12MEM9_)
#define ADC12MEM10_ (0x0154u) /* ADC12 Conversion Memory 10 */
DEFW( ADC12MEM10 , ADC12MEM10_)
#define ADC12MEM11_ (0x0156u) /* ADC12 Conversion Memory 11 */
DEFW( ADC12MEM11 , ADC12MEM11_)
#define ADC12MEM12_ (0x0158u) /* ADC12 Conversion Memory 12 */
DEFW( ADC12MEM12 , ADC12MEM12_)
#define ADC12MEM13_ (0x015Au) /* ADC12 Conversion Memory 13 */
DEFW( ADC12MEM13 , ADC12MEM13_)
#define ADC12MEM14_ (0x015Cu) /* ADC12 Conversion Memory 14 */
DEFW( ADC12MEM14 , ADC12MEM14_)
#define ADC12MEM15_ (0x015Eu) /* ADC12 Conversion Memory 15 */
DEFW( ADC12MEM15 , ADC12MEM15_)
#define ADC12MCTL_ (0x0080u) /* ADC12 Memory Control */
#ifndef __IAR_SYSTEMS_ICC__
#define ADC12MCTL (ADC12MCTL_) /* ADC12 Memory Control (for assembler) */
#else
#define ADC12MCTL ((char*) ADC12MCTL_) /* ADC12 Memory Control (for C) */
#endif
#define ADC12MCTL0_ (0x0080u) /* ADC12 Memory Control 0 */
DEFC( ADC12MCTL0 , ADC12MCTL0_)
#define ADC12MCTL1_ (0x0081u) /* ADC12 Memory Control 1 */
DEFC( ADC12MCTL1 , ADC12MCTL1_)
#define ADC12MCTL2_ (0x0082u) /* ADC12 Memory Control 2 */
DEFC( ADC12MCTL2 , ADC12MCTL2_)
#define ADC12MCTL3_ (0x0083u) /* ADC12 Memory Control 3 */
DEFC( ADC12MCTL3 , ADC12MCTL3_)
#define ADC12MCTL4_ (0x0084u) /* ADC12 Memory Control 4 */
DEFC( ADC12MCTL4 , ADC12MCTL4_)
#define ADC12MCTL5_ (0x0085u) /* ADC12 Memory Control 5 */
DEFC( ADC12MCTL5 , ADC12MCTL5_)
#define ADC12MCTL6_ (0x0086u) /* ADC12 Memory Control 6 */
DEFC( ADC12MCTL6 , ADC12MCTL6_)
#define ADC12MCTL7_ (0x0087u) /* ADC12 Memory Control 7 */
DEFC( ADC12MCTL7 , ADC12MCTL7_)
#define ADC12MCTL8_ (0x0088u) /* ADC12 Memory Control 8 */
DEFC( ADC12MCTL8 , ADC12MCTL8_)
#define ADC12MCTL9_ (0x0089u) /* ADC12 Memory Control 9 */
DEFC( ADC12MCTL9 , ADC12MCTL9_)
#define ADC12MCTL10_ (0x008Au) /* ADC12 Memory Control 10 */
DEFC( ADC12MCTL10 , ADC12MCTL10_)
#define ADC12MCTL11_ (0x008Bu) /* ADC12 Memory Control 11 */
DEFC( ADC12MCTL11 , ADC12MCTL11_)
#define ADC12MCTL12_ (0x008Cu) /* ADC12 Memory Control 12 */
DEFC( ADC12MCTL12 , ADC12MCTL12_)
#define ADC12MCTL13_ (0x008Du) /* ADC12 Memory Control 13 */
DEFC( ADC12MCTL13 , ADC12MCTL13_)
#define ADC12MCTL14_ (0x008Eu) /* ADC12 Memory Control 14 */
DEFC( ADC12MCTL14 , ADC12MCTL14_)
#define ADC12MCTL15_ (0x008Fu) /* ADC12 Memory Control 15 */
DEFC( ADC12MCTL15 , ADC12MCTL15_)
/* ADC12CTL0 */
#define ADC12SC (0x001) /* ADC12 Start Conversion */
#define ENC (0x002) /* ADC12 Enable Conversion */
#define ADC12TOVIE (0x004) /* ADC12 Timer Overflow interrupt enable */
#define ADC12OVIE (0x008) /* ADC12 Overflow interrupt enable */
#define ADC12ON (0x010) /* ADC12 On/enable */
#define REFON (0x020) /* ADC12 Reference on */
#define REF2_5V (0x040) /* ADC12 Ref 0:1.5V / 1:2.5V */
#define MSC (0x080) /* ADC12 Multiple SampleConversion */
#define SHT00 (0x0100u) /* ADC12 Sample Hold 0 Select 0 */
#define SHT01 (0x0200u) /* ADC12 Sample Hold 0 Select 1 */
#define SHT02 (0x0400u) /* ADC12 Sample Hold 0 Select 2 */
#define SHT03 (0x0800u) /* ADC12 Sample Hold 0 Select 3 */
#define SHT10 (0x1000u) /* ADC12 Sample Hold 0 Select 0 */
#define SHT11 (0x2000u) /* ADC12 Sample Hold 1 Select 1 */
#define SHT12 (0x4000u) /* ADC12 Sample Hold 2 Select 2 */
#define SHT13 (0x8000u) /* ADC12 Sample Hold 3 Select 3 */
#define MSH (0x080)
#define SHT0_0 (0*0x100u) /* ADC12 Sample Hold 0 Select Bit: 0 */
#define SHT0_1 (1*0x100u) /* ADC12 Sample Hold 0 Select Bit: 1 */
#define SHT0_2 (2*0x100u) /* ADC12 Sample Hold 0 Select Bit: 2 */
#define SHT0_3 (3*0x100u) /* ADC12 Sample Hold 0 Select Bit: 3 */
#define SHT0_4 (4*0x100u) /* ADC12 Sample Hold 0 Select Bit: 4 */
#define SHT0_5 (5*0x100u) /* ADC12 Sample Hold 0 Select Bit: 5 */
#define SHT0_6 (6*0x100u) /* ADC12 Sample Hold 0 Select Bit: 6 */
#define SHT0_7 (7*0x100u) /* ADC12 Sample Hold 0 Select Bit: 7 */
#define SHT0_8 (8*0x100u) /* ADC12 Sample Hold 0 Select Bit: 8 */
#define SHT0_9 (9*0x100u) /* ADC12 Sample Hold 0 Select Bit: 9 */
#define SHT0_10 (10*0x100u) /* ADC12 Sample Hold 0 Select Bit: 10 */
#define SHT0_11 (11*0x100u) /* ADC12 Sample Hold 0 Select Bit: 11 */
#define SHT0_12 (12*0x100u) /* ADC12 Sample Hold 0 Select Bit: 12 */
#define SHT0_13 (13*0x100u) /* ADC12 Sample Hold 0 Select Bit: 13 */
#define SHT0_14 (14*0x100u) /* ADC12 Sample Hold 0 Select Bit: 14 */
#define SHT0_15 (15*0x100u) /* ADC12 Sample Hold 0 Select Bit: 15 */
#define SHT1_0 (0*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 0 */
#define SHT1_1 (1*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 1 */
#define SHT1_2 (2*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 2 */
#define SHT1_3 (3*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 3 */
#define SHT1_4 (4*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 4 */
#define SHT1_5 (5*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 5 */
#define SHT1_6 (6*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 6 */
#define SHT1_7 (7*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 7 */
#define SHT1_8 (8*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 8 */
#define SHT1_9 (9*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 9 */
#define SHT1_10 (10*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 10 */
#define SHT1_11 (11*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 11 */
#define SHT1_12 (12*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 12 */
#define SHT1_13 (13*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 13 */
#define SHT1_14 (14*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 14 */
#define SHT1_15 (15*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 15 */
/* ADC12CTL1 */
#define ADC12BUSY (0x0001u) /* ADC12 Busy */
#define CONSEQ0 (0x0002u) /* ADC12 Conversion Sequence Select 0 */
#define CONSEQ1 (0x0004u) /* ADC12 Conversion Sequence Select 1 */
#define ADC12SSEL0 (0x0008u) /* ADC12 Clock Source Select 0 */
#define ADC12SSEL1 (0x0010u) /* ADC12 Clock Source Select 1 */
#define ADC12DIV0 (0x0020u) /* ADC12 Clock Divider Select 0 */
#define ADC12DIV1 (0x0040u) /* ADC12 Clock Divider Select 1 */
#define ADC12DIV2 (0x0080u) /* ADC12 Clock Divider Select 2 */
#define ISSH (0x0100u) /* ADC12 Invert Sample Hold Signal */
#define SHP (0x0200u) /* ADC12 Sample/Hold Pulse Mode */
#define SHS0 (0x0400u) /* ADC12 Sample/Hold Source 0 */
#define SHS1 (0x0800u) /* ADC12 Sample/Hold Source 1 */
#define CSTARTADD0 (0x1000u) /* ADC12 Conversion Start Address 0 */
#define CSTARTADD1 (0x2000u) /* ADC12 Conversion Start Address 1 */
#define CSTARTADD2 (0x4000u) /* ADC12 Conversion Start Address 2 */
#define CSTARTADD3 (0x8000u) /* ADC12 Conversion Start Address 3 */
#define CONSEQ_0 (0*2u) /* ADC12 Conversion Sequence Select: 0 */
#define CONSEQ_1 (1*2u) /* ADC12 Conversion Sequence Select: 1 */
#define CONSEQ_2 (2*2u) /* ADC12 Conversion Sequence Select: 2 */
#define CONSEQ_3 (3*2u) /* ADC12 Conversion Sequence Select: 3 */
#define ADC12SSEL_0 (0*8u) /* ADC12 Clock Source Select: 0 */
#define ADC12SSEL_1 (1*8u) /* ADC12 Clock Source Select: 1 */
#define ADC12SSEL_2 (2*8u) /* ADC12 Clock Source Select: 2 */
#define ADC12SSEL_3 (3*8u) /* ADC12 Clock Source Select: 3 */
#define ADC12DIV_0 (0*0x20u) /* ADC12 Clock Divider Select: 0 */
#define ADC12DIV_1 (1*0x20u) /* ADC12 Clock Divider Select: 1 */
#define ADC12DIV_2 (2*0x20u) /* ADC12 Clock Divider Select: 2 */
#define ADC12DIV_3 (3*0x20u) /* ADC12 Clock Divider Select: 3 */
#define ADC12DIV_4 (4*0x20u) /* ADC12 Clock Divider Select: 4 */
#define ADC12DIV_5 (5*0x20u) /* ADC12 Clock Divider Select: 5 */
#define ADC12DIV_6 (6*0x20u) /* ADC12 Clock Divider Select: 6 */
#define ADC12DIV_7 (7*0x20u) /* ADC12 Clock Divider Select: 7 */
#define SHS_0 (0*0x400u) /* ADC12 Sample/Hold Source: 0 */
#define SHS_1 (1*0x400u) /* ADC12 Sample/Hold Source: 1 */
#define SHS_2 (2*0x400u) /* ADC12 Sample/Hold Source: 2 */
#define SHS_3 (3*0x400u) /* ADC12 Sample/Hold Source: 3 */
#define CSTARTADD_0 (0*0x1000u) /* ADC12 Conversion Start Address: 0 */
#define CSTARTADD_1 (1*0x1000u) /* ADC12 Conversion Start Address: 1 */
#define CSTARTADD_2 (2*0x1000u) /* ADC12 Conversion Start Address: 2 */
#define CSTARTADD_3 (3*0x1000u) /* ADC12 Conversion Start Address: 3 */
#define CSTARTADD_4 (4*0x1000u) /* ADC12 Conversion Start Address: 4 */
#define CSTARTADD_5 (5*0x1000u) /* ADC12 Conversion Start Address: 5 */
#define CSTARTADD_6 (6*0x1000u) /* ADC12 Conversion Start Address: 6 */
#define CSTARTADD_7 (7*0x1000u) /* ADC12 Conversion Start Address: 7 */
#define CSTARTADD_8 (8*0x1000u) /* ADC12 Conversion Start Address: 8 */
#define CSTARTADD_9 (9*0x1000u) /* ADC12 Conversion Start Address: 9 */
#define CSTARTADD_10 (10*0x1000u) /* ADC12 Conversion Start Address: 10 */
#define CSTARTADD_11 (11*0x1000u) /* ADC12 Conversion Start Address: 11 */
#define CSTARTADD_12 (12*0x1000u) /* ADC12 Conversion Start Address: 12 */
#define CSTARTADD_13 (13*0x1000u) /* ADC12 Conversion Start Address: 13 */
#define CSTARTADD_14 (14*0x1000u) /* ADC12 Conversion Start Address: 14 */
#define CSTARTADD_15 (15*0x1000u) /* ADC12 Conversion Start Address: 15 */
/* ADC12MCTLx */
#define INCH0 (0x0001u) /* ADC12 Input Channel Select Bit 0 */
#define INCH1 (0x0002u) /* ADC12 Input Channel Select Bit 1 */
#define INCH2 (0x0004u) /* ADC12 Input Channel Select Bit 2 */
#define INCH3 (0x0008u) /* ADC12 Input Channel Select Bit 3 */
#define SREF0 (0x0010u) /* ADC12 Select Reference Bit 0 */
#define SREF1 (0x0020u) /* ADC12 Select Reference Bit 1 */
#define SREF2 (0x0040u) /* ADC12 Select Reference Bit 2 */
#define EOS (0x0080u) /* ADC12 End of Sequence */
#define INCH_0 (0) /* ADC12 Input Channel 0 */
#define INCH_1 (1) /* ADC12 Input Channel 1 */
#define INCH_2 (2) /* ADC12 Input Channel 2 */
#define INCH_3 (3) /* ADC12 Input Channel 3 */
#define INCH_4 (4) /* ADC12 Input Channel 4 */
#define INCH_5 (5) /* ADC12 Input Channel 5 */
#define INCH_6 (6) /* ADC12 Input Channel 6 */
#define INCH_7 (7) /* ADC12 Input Channel 7 */
#define INCH_8 (8) /* ADC12 Input Channel 8 */
#define INCH_9 (9) /* ADC12 Input Channel 9 */
#define INCH_10 (10) /* ADC12 Input Channel 10 */
#define INCH_11 (11) /* ADC12 Input Channel 11 */
#define INCH_12 (12) /* ADC12 Input Channel 12 */
#define INCH_13 (13) /* ADC12 Input Channel 13 */
#define INCH_14 (14) /* ADC12 Input Channel 14 */
#define INCH_15 (15) /* ADC12 Input Channel 15 */
#define SREF_0 (0*0x10u) /* ADC12 Select Reference 0 */
#define SREF_1 (1*0x10u) /* ADC12 Select Reference 1 */
#define SREF_2 (2*0x10u) /* ADC12 Select Reference 2 */
#define SREF_3 (3*0x10u) /* ADC12 Select Reference 3 */
#define SREF_4 (4*0x10u) /* ADC12 Select Reference 4 */
#define SREF_5 (5*0x10u) /* ADC12 Select Reference 5 */
#define SREF_6 (6*0x10u) /* ADC12 Select Reference 6 */
#define SREF_7 (7*0x10u) /* ADC12 Select Reference 7 */
/* ADC12IV Definitions */
#define ADC12IV_NONE (0x0000u) /* No Interrupt pending */
#define ADC12IV_ADC12OVIFG (0x0002u) /* ADC12OVIFG */
#define ADC12IV_ADC12TOVIFG (0x0004u) /* ADC12TOVIFG */
#define ADC12IV_ADC12IFG0 (0x0006u) /* ADC12IFG0 */
#define ADC12IV_ADC12IFG1 (0x0008u) /* ADC12IFG1 */
#define ADC12IV_ADC12IFG2 (0x000Au) /* ADC12IFG2 */
#define ADC12IV_ADC12IFG3 (0x000Cu) /* ADC12IFG3 */
#define ADC12IV_ADC12IFG4 (0x000Eu) /* ADC12IFG4 */
#define ADC12IV_ADC12IFG5 (0x0010u) /* ADC12IFG5 */
#define ADC12IV_ADC12IFG6 (0x0012u) /* ADC12IFG6 */
#define ADC12IV_ADC12IFG7 (0x0014u) /* ADC12IFG7 */
#define ADC12IV_ADC12IFG8 (0x0016u) /* ADC12IFG8 */
#define ADC12IV_ADC12IFG9 (0x0018u) /* ADC12IFG9 */
#define ADC12IV_ADC12IFG10 (0x001Au) /* ADC12IFG10 */
#define ADC12IV_ADC12IFG11 (0x001Cu) /* ADC12IFG11 */
#define ADC12IV_ADC12IFG12 (0x001Eu) /* ADC12IFG12 */
#define ADC12IV_ADC12IFG13 (0x0020u) /* ADC12IFG13 */
#define ADC12IV_ADC12IFG14 (0x0022u) /* ADC12IFG14 */
#define ADC12IV_ADC12IFG15 (0x0024u) /* ADC12IFG15 */
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