【高速接口-RapidIO】5、Xilinx RapidIO核例子工程源码分析
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一、软件平台与硬件平台
软件平台：
操作系统：Windows 8.1 64-bit
开发套件：Vivado2015.4.2
硬件平台：
评估板：ZYNQ-7 ZC706 Evaluation Board
二、打开例子工程
1、新建工程，并在IP Catalog中找到Serial RapidIO Gen2
2、双击Serial RapidIO Gen2进入核的配置界面，所用参数全部保持默认，然后直接点击OK
3、在弹出的的对话框中直接点击Generate
4、在弹出的对话框中点击OK
5、等待srio_gen2_0核综合完毕，可能会花几分钟的时间
6、IP核综合完毕以后，单击srio_gen2_0，并点击鼠标右键，在弹出的菜单栏中单击Open IP Example Design…
7、在弹出的的对话框中选择例子工程的存放目录（这个目录可任意选择），然后单击OK
8、等一段时间以后例子工程就会自动打开
三、例子工程详解
3.1 工程概述
RapidIO核的例子工程的仿真顶层代码里面例化了两个实体，一个叫做srio_example_top_primary，另外一个叫做srio_example_top_mirror，如下图所示
其中每个例化实体都能被配置为发送支持的包类型，检测接收包失配以及上报链路的仿真细节。下表列出了例子工程中各个主要模块的功能简介
|
文件名 |
功能 |
|
srio_example_top.v |
例子工程的顶层模块 |
|
srio_request_gen.v |
生成请求事务的模块 |
|
instruction_list.vh |
这是一个Verilog头文件，里面定义了120个事务，它被包含在srio_request_gen.v模块中，srio_request_gen.v模块会把里面的所有事务依次发出去 |
|
srio_response_gen.v |
这个模块用来产生有响应事务的响应包 |
|
srio_condensed_gen.v |
当IP核的端口配置为Condensed I/O模式时，这个文件才会出现在例子工程中。它用来产生Condensed I/O模式的请求事务。 |
|
srio_quick_start.v |
这个模块与IP核的维护端口相连，用来发起维护事务。 |
|
maintenance_list.vh |
这是一个Verilog头文件，里面定义了一些维护事务，它被包含在srio_quick_start.v模块中，srio_quick_start.v模块会把里面的所有维护事务依次发出去用来配置相关寄存器 |
|
srio_report.v |
在仿真时，这个模块用来产生包接收和发送的时间戳，在硬件上运行的时候这个模块可以删除 |
|
srio_statistics.v |
这个模块用来收集核的统计信息并通过寄存器接口提交一些信息，提交的信息可以通过Vivado的调试特征以及用户设计来访问 |
|
srio_sim.v |
srio_sim.v是仿真顶层文件，它例化了两个核，分别是primary和mirror，并把它们连接到一起用于仿真。它也包含了上报测试是否成功的机制与超时（timeout）功能。 |
3.2 工程结构
例子工程的顶层模块例化了所有核的所有组件和在硬件上执行所需要的例子代码，整个工程的结构如下图所示。
整个结构包括时钟模块，复位模块，配置结构以及产生RapidIO事务的激励模块。
srio_quick_start模块在顶层srio_example_top.v中例化，它与IP核的维护端口相连用来产成维护事务，维护事务在maintenance_list.vh中进行定义，用户可以根据需要编辑maintenance_list.vh文件来添加，修改和移除维护事务。
srio_request_gen.v模块也在顶层srio_example_top.v中例化，它用来产生I/O事务与消息事务。这个模块也存储了期望的响应并把接收的响应与期望值进行比较。
srio_response_gen.v模块也在顶层srio_example_top.v中例化，它用来为接收到的请求事务生成对应的响应事务。
通过上图可以看出，产生I/O事务一共有两种方式：第一种是通过例子工程中自带的srio_request_gen.v产生I/O事务；第二种是通过顶层模块中Initiator和Target的resquest/response接口自己编写代码产生I/O事务。同理，产生维护事务也有两种方式：第一种是通过例子工程中自带的srio_quick_start.v模块产生维护事务；第二种是通过顶层模块中的维护接口自己编写代码产生维护事务。I/O事务的端口类型是AXI4-Stream类型，维护事务的端口类型是AXI4-Lite类型。
默认情况下，由于例子工程的顶层srio_example_top.v模块中，VALIDATION_FEATURES与QUICK_STARTUP两个参数均被设置为1，如下图所示
所以，例子工程是采用自带的srio_request_gen.v和srio_quick_start.v分别产生I/O事务与维护事务，另外，推荐注释掉外部接口以节省管脚和改善时序。
如果要使用外部接口产生I/O事务，那么需要设置参数VALIDATION_FEATURES=0，并且取消顶层模块srio_example_top.v中外部接口（axis_ireq_*,axis_tresp_*, axis_iresp_*, axis_treq_*, axis_iotx_*, axis_iorx_*）的注释。如果要使用外部接口产生维护事务，那些需要设置参数QUICK_STARTUP=0，并且取消顶层模块srio_example_top.v中外部接口（axis_maintr_*）的注释。使用外部接口的工程结构如下图所示
3.3 工程分析
I/O事务与维护事务
默认情况下，例子工程会使用srio_request_gen.v模块和srio_quick_start.v模块来产生I/O事务与维护事务。其中instruction_list.vh头文件定义了待发送的I/O事务，maintenance_list.vh头文件定义了待发送的维护事务。
当核被复位以后，maintenance_list.vh中的维护事务可以对核进行配置，维护事务可以在maintenance_list.vh进行添加、修改或移除。当没有处理器时，srio_quick_start.v模块可以用来管理公共的维护事务。当核复位以后，这是一种比较好的配置核的方法。
srio_request_gen.v模块和srio_response_gen.v模块可以用来产生I/O事务，srio_request_gen.v模块可以用来产生定义在instruction_list.vh中的I/O请求事务。instruction_list.vh中的I/O事务可以被添加、修改或移除，I/O事务的顺序是随机的，但是每次重新仿真时都是按照相同的顺序产生的。而且，只有IP核端口支持的事务才能被产生。srio_request_gen.v模块还可以追踪期望的响应并且比较接收的响应与期望值，这在仿真的时候可以很方便的确定事务的收发情况。
srio_response_gen.v模块用来产生接收到的请求所对应的目标响应I/O事务。如果写事务目标地址的第23位到16位为8’h12（address[23:16]=8’h12），那么数据负载会被存储在本地存储器。不需要响应的写事务会被丢弃，并且srio_response_gen.v模块不会响应SWRITE事务。如果读事务目标地址的第23位到16位为8’h12（address[23:16]=8’h12），那么数据将会从实际地址读出。对于那些地址不满足第23位到16位为8’h12（address[23:16]=8’h12）的事务，srio_response_gen.v模块将以地址递增的方式写入I/O事务携带的数据。响应会根据接收到的请求的顺序依次产生，所以不会有无序的事务产生。在所有的情况中，响应事务的优先级等于请求事务的优先级加1。
注意：每个srio_request_gen.v模块会消耗一个块RAM（Block RAM），每个srio_response_gen.v模块会消耗两个块RAM（Block RAM）。
配置结构
配置空间分布在RapidIO核的所有块中，配置结构的参考设计在例子设计的cfg_fabric模块中，用来管理每个块配置空间的访问情况。块（Block）的配置模块在配置总线（AXI4-Lite）上是作为从机存在的，cfg_fabric模块是作为主机存在的。维护事务的读写操作是从本地或者远程被发起，它是通过逻辑层的配置主端口接入配置模块，配置模块会把读写事务送入对应的块中，但如果地址不在各自配置寄存器的有效范围内，配置模块不会移交任何读写事务。往非法的空间写事务会被丢弃，读非法的空间将返回0。
时钟模块
例子设计的时钟模块与IP核的时钟模块是相同的。srio_clk模块有1个MMCM_ADV，1个IBUFDS和3个或4个BUFGs组成，在2x或4x模式，其中一个BUFGs将被转化为BUFGMUX。srio_clk模块会根据配置的不同产生合适的参考频率与用户时钟。
复位模块
srio_rst模块会把每个时钟域里面的异步复位信号转化为一个脉冲扩展的同步复位信号。当被用户设计调用的时候，srio_rst模块会用一个状态机强制对核重新初始化。
四、工程源码分析
3.1 顶层模块srio_example_top.v源码分析
顶层模块srio_example_top.v源码的端口定义如下
顶层模块包含5个参数：SIM_VERBOSE，VALIDATION_FEATURES，QUICK_STARTUP，STATISTICS_GATHERING和C_LINK_WIDTH。
SIM_VERBOSE设为1时，可以利用srio_report.v模块生成不可综合的报告。为0时，此功能被屏蔽。
VALIDATION_FEATURES设为1时，选择例子工程中的srio_request_gen.v和srio_response_gen.v产生相应的请求事务与响应事务对IP核的功能进行测试。为0时，选择外部的用户接口由用户自己编写请求事务与响应事务的代码对IP进行测试。
QUICK_STARTUP设为1时，选择例子工程中的srio_quick_start.v产生相应的维护事务对IP核的配置空间进行访问。为0时，选择外部的维护接口由用户自己编写维护事务的代码对IP核的配置空间进行访问。
STATISTICS_GATHERING设为1时，可以利用srio_statistics.v模块搜集IP的性能细节，这个模块是可综合的，可以通过Chipscope或ILA进行访问。为0时，此功能被屏蔽。
顶层模块的差分时钟sys_clkp和sys_clkn就是IP核配置界面第一页的参考时钟，由于例子工程中采用的全部是默认参数，所以这里这个时钟为125MHz，这个时钟可以由FPGA外部的有源晶振或锁相环芯片输出。
sys_rst为IP核的复位信号，高电平有效。
差分信号srio_rxn0和srio_rxp0为串行接收数据信号，srio_txn0和srio_txp0为串行发送数据信号。
sim_train_en信号是一个用来减少仿真时间的控制信号，仿真时把这个信号置1可以加快仿真速度，但是代码在硬件上运行时这个信号必须赋值为0。
led0是led指示信号，可以把port_initialized和link_initialized两个信号接到led0中，这样在硬件上执行时可以方便观察链路状态。
顶层模块srio_example_top.v中的第466行到第590行例化了RapidIO核，部分源码如下图所示
第612行到631行是例化了srio_report.v模块用来收集ireq接口的统计信息。除此以外，还例化了3个srio_report.v模块用来收集iresp，treq，tresp接口的统计信息。下图是收集ireq统计信息的源代码。源码如下图所示
第637行到684行srio_request_gen.v模块用来生成请求事务。这个模块有7个参数，分别为SEND_SWRITE，SEND_NWRITER，SEND_NWRITE，SEND_NREAD，SEND_FTYPE9，SEND_DB和SEND_MSG。当他们设置为1时，srio_request_gen.v模块将会把instruction_list.vh模块中对应的事务发送给SRIO IP核。部分源码如下图所示
第779行到804行例化了srio_response_gen.v模块，这个模块用来产生响应事务。部分源码如下图所示
第890行到937行例化了srio_quick_start.v模块，这个模块产生维护事务来访问配置空间。部分源码如下图所示
第944行到988行例化了srio_statistics.v模块，这个模块用来收集统计信息，它是一个可综合的模块。部分源码如下图所示
3.2 模块srio_request_gen.v源码分析
模块srio_request_gen.v的作用是产生RapidIO请求事务，上篇文章《Xilinx RapidIO核详解》（链接：https://www.cnblogs.com/liujinggang/p/10072115.html）已经提到过，RapidIO核为了简化包的构建过程，设计了一种精简的包格式——HELLO格式来完成包的构建，然后按照HELLO格式的时序把数据发送给RapidIO核，RapidIO核会把HELLO格式的包转化为标准的RapidIO串行物理层的包。这样，用户在设计请求事务的Verilog代码时只需要对HELLO格式的包与时序有所了解，而不需要过多的关注RapidIO的协议与RapidIO包格式。这里重新复习一下HELLO格式的包结构与HELLO格式的时序。
HELLO格式的包结构如下图所示：
HELLO格式的时序图如下图所示：
事实上，整个srio_request_gen.v源代码的核心就是先构建HELLO格式的包，然后把包头（Header）和数据按照HELLO格式的时序传给RapidIO核就可以了。下面详细分析一下。
分析instruction_list.vh头文件
在分析srio_request_gen.v源代码之前先来分析一下instruction_list.vh头文件。因为srio_request_gen.v文件中包含了instruction_list.vh头文件，instruction_list.vh头文件中定义了srio_request_gen.v将要发送的所有事务。
instruction_list.vh头文件的第1行到第9行定义了事务的个数以及所有事务的总个数，每种事务的个数由一个控制变量进行选择，源码如下：
第11行到50行是37个SWRITE事务（流写事务），其中第1列的12位数据是由8-bit的保留位（SWRITE事务没有srcTID字段），1-bit的保留位，2-bit的prio和1-bit的CRF组成，第2列是FTYPE字段，第3列是保留字段（SWRITE事务没有TTYPE字段），第4列的36-bit数据是由最高2-bit的保留位和34-bit的address字段组成，第5列是8-bit保留字段（SWRITE事务没有size字段），不管这个字段的值为多少，目标设备都会把这个值当做0来处理。源代码如下图所示
第52行到72行是19个NWRITE_R事务（带响应的写事务），其中第1列的12位数据是由8-bit的srcTID，1-bit的保留位，2-bit的prio和1-bit的CRF组成，第2列是FTYPE字段，第3列是TTYPE字段，第4列的36-bit数据是由最高2-bit的保留位和34-bit的address字段组成，第5列是size字段，这个字段的值为实际的数据量减1。比如size=0，表示实际传输的数据量为1。源代码如下图所示
第74行到94行是19个NWRITE事务（写事务），其中第1列的12位数据是由8-bit的srcTID，1-bit的保留位，2-bit的prio和1-bit的CRF组成，第2列是FTYPE字段，第3列是TTYPE字段，第4列的36-bit数据是由最高2-bit的保留位和34-bit的address字段组成，第5列是size字段，这个字段的值为实际的数据量减1。比如size=0，表示实际传输的数据量为1。源代码如下图所示
第96行到123行是26个NREAD事务（读事务），其中第1列的12位数据是由8-bit的srcTID，1-bit的保留位，2-bit的prio和1-bit的CRF组成，第2列是FTYPE字段，第3列是TTYPE字段，第4列的36-bit数据是由最高2-bit的保留位和34-bit的address字段组成，第5列是size字段，这个字段的值为实际的数据量减1。比如size=0，表示实际传输的数据量为1。源代码如下图所示
第125行到128行是两个DOORBELL事务（门铃事务），其中第1列的12位数据是由8-bit的srcTID，1-bit的保留位，2-bit的prio和1-bit的CRF组成，第2列是FTYPE字段，第3列是保留字段（DOORBELL事务没有TTYPE字段），第4列的36-bit数据是由最高4-bit的保留位，8-bit的信息高8位，8-bit的信息低8位以及最后的16-bit保留位组成。第5列是8-bit保留字段（DOORBELL事务没有size字段）。源代码如下图所示
第130行到148行是17个MESSAGE事务（消息事务），其中第1列的12位数据是由4-bit的msglen，4-bit的msgseg，1-bit的保留位，2-bit的prio和1-bit的CRF组成，第2列是FTYPE字段，第3列是保留字段（MESSAGE事务没有TTYPE字段），第4列的36-bit数据是由最高26-bit的保留位，6-bit的mailbox字段，2-bit的保留位以及2-bit的ltr组成。第5列是8-bit的size字段。源代码如下图所示
第150行到152行是1个Data Streaming事务，这是Xilinx定义的第9类事务，由于这种事务用的不多，我自己也不太了解，所以这里就不进行分析了。源代码如下图所示
分析srio_request_gen.v源码
在分析完毕instruction_list.vh头文件以后接下来开始着手分析srio_request_gen.v源码。分析过程中始终要记住的一点是：srio_request_gen.v的核心功能就是组装HELLO包头并把包头和数据按照HELLO格式的时序发送出去。
srio_request_gen.v源码的第50行到92行是参数与接口的定义。它包含7个参数，分别为SEND_SWRITE、SEND_NWRITER、SEND_NWRITE、SEND_NREAD、SEND_DB、SEND_FTYPE9和SEND_MSG，它们的默认值被设置为0，但是在顶层模块中例化的时候，它们的值分别被设置为1、1、1、1、0、1、1。如下图所示
根据上面分析instruction_list.vh头文件可知，如果上面的7个参数为1的话，各个事务的个数应该由instruction_list.vh头文件中NUM_SWRITES、NUM_NWRITERS、NUM_NWRITES、NUM_NREADS、NUM_DBS、NUM_MSGS和NUM_FTYPE9决定。
接下来就是端口的定义，其中log_clk与log_rst均由IP输出，log_clk的频率与链路线速率和链路宽度有关，具体的对应关系在上篇文章中能找到。接下来就是设备ID，目的ID以及源ID的定义。然后定义了ireq与iresp，它们都采用了AXI4-Stream协议。link_initialized信号由IP核输出，当它为高时表明链路成功初始化。以user_*开头的几个变量可以方便用户自定义HELLO格式包头中的各个字段。
第96到110行定义了HELLO格式包头中的FTYPE字段与TTYPE字段的值，这两个字段的值与事务的类型有关，源码如下图所示
第120行定义了一个memory类型变量，综合的时候ram的类型为分布式ram，121行导入了instruction_list.vh头文件，126行定义的变量可以看做AXI4-Stream总线上数据有效的标志位，当这个信号为高时，AXI4-Stream总线上tdata上的数据为有效数据。源代码如下图所示
第178行到205行用来初始化事务列表，instruction[ii]存放的是instruction_list.vh头文件中定义的各个事务的相关字段值，源代码如下图所示
第208到第219行是一些简单的赋值操作。其中第208行的val_ireq_tkeep和val_ireq_tuser是根据HELLO格式的时序要求赋值的，HELLO格式的时序要求tkeep为8’hFF，tuser在第一个有效的时钟（log_clk）周期内由src_id与dest_id拼接而成。第213行和第217行的go变量用来选择HELLO格式包头各个字段由用户定义还是由instruction_list.vh定义。第219行的header_beat变量就是HELLO格式的包头，在第一个有效时钟（log_clk）周期，tdata上的数据必须为header_beat。源代码如下图所示
第266行到288行主要用来产生有效时钟计数器current_beat_cnt与有效时钟计数总数number_of_data_beats。当AXI4_Stream总线的tvalid和tready信号同时为高时，时钟为有效时钟，current_beat_cnt加1，当检测到tlast信号为高时表明最后一个数据已发送完毕，所以把current_beat_cnt清0。由于tdata的宽度为64-bit，也就是8个字节，所以有效时钟计数总数number_of_data_beats为current_size右移3位。源代码如下图所示
第294行到306行用来产生AXI4_Stream总线中tlast信号，tlast为高时表明发送的是最后一个数据，所以tlast信号相当于一帧数据的边界。
第307行到328行用来产生AXI4_Stream总线中的tdata信号，当有效时钟计数器current_beat_cnt为0时，tdata为包头header_beat，包头header_beat后面是待发送的数据data_beat，例子工程为了简单起见，发送的数据是累加数，每个累加数为8-bit，然后把每个累加数拼接8次作为待发送的数据，也就是说，待发送的数据为64’h0000000000000000，64’h0101010101010101，64’h0202020202020202，……..，后面以此类推。
第330行到345行主要用来产生AXI4_Stream总线中的tvalid信号，同时也产生了一些其他的标志信号。至此，整个AXI4_Stream总线中的所有信号的逻辑都编写完毕，并且整个逻辑都是完全符合HELLO格式的时序。代码的核心部分全部分析完毕。
第351行到第371行与数据的存储相关。每当current_beat_cnt的值为0时，request_address变量加1， request_address也被赋给了tid，也就是说request_address也是事务ID值，同时request_address也是instruction的索引值。源代码如下图所示
第382行到第406行例化了一个RAMB36SDP原语，RAMB36SDP是一个大小为36Kb的简单双口Block RAM（SDP=Simple Dual Port）。它的作用是把请求事务的tid，current_ftype和current_size写入RAM中存起来，对于有响应的事务，RapidIO会收到一个响应事务，收到响应事务事务以后可以把存放在RAMB36SDP中的数据读出来与响应事务中对应的字段进行对比从而对整个事务的交互过程的正确性进行一个初步判断。关于RAMB36SDP原语的详细解释请阅读下一小节。源代码如下图所示
第458行到482行就是把存储在RAM中请求事务的tid，current_ftype和current_size与响应事务对应的字段进行对比，在仿真时给出对应的提示信息。
至此，整个产生请求事务的代码全部分析完毕，其他未分析到的代码大家自己尝试分析。
3.3 RAMB36SDP原语分析
RAMB36SDP是一个大小为36Kb的简单双口Block RAM（SDP=Simple Dual-Port），它其实是Virtex-5系列FPGA的一个原语，Vivado里面并没有RAMB36SDP的语法模板，ISE中才有它的语法模板，如下图所示
RAMB36SDP原语的完整代码如下所示
// RAMB36SDP : In order to incorporate this function into the design,
// Verilog : the forllowing instance declaration needs to be placed
// instance : in the body of the design code. The instance name
// declaration : (RAMB36SDP_inst) and/or the port declarations within the
// code : parenthesis may be changed to properly reference and
// : connect this function to the design. All inputs
// : and outputs must be connected. // <-----Cut code below this line----> // RAMB36SDP: 72x512 Simple Dual-Port BlockRAM w/ ECC
// Virtex-5
// Xilinx HDL Language Template, version 14.7 RAMB36SDP #(
.SIM_MODE("SAFE"), // Simulation: "SAFE" vs. "FAST", see "Synthesis and Simulation Design Guide" for details
.DO_REG(), // Optional output register (0 or 1)
.EN_ECC_READ("FALSE"), // Enable ECC decoder, "TRUE" or "FALSE"
.EN_ECC_WRITE("FALSE"), // Enable ECC encoder, "TRUE" or "FALSE"
.INIT('h000000000000000000), // Initial values on output port
.SIM_COLLISION_CHECK("ALL"), // Collision check enable "ALL", "WARNING_ONLY",
// "GENERATE_X_ONLY" or "NONE"
.SRVAL('h000000000000000000), // Set/Reset value for port output // The forllowing INIT_xx declarations specify the initial contents of the RAM
.INIT_00('h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
.INIT_01('h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
.INIT_02('h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
.INIT_03('h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
.INIT_04('h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
.INIT_05('h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
.INIT_06('h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
.INIT_07('h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
.INIT_08('h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
.INIT_09('h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
.INIT_0A('h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
.INIT_0B('h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
.INIT_0C('h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
.INIT_0D('h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
.INIT_0E('h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
.INIT_0F('h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
.INIT_10('h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
.INIT_11('h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
.INIT_12('h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
.INIT_13('h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
.INIT_14('h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
.INIT_15('h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
.INIT_16('h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
.INIT_17('h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
.INIT_18('h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
.INIT_19('h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
.INIT_1A('h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
.INIT_1B('h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
.INIT_1C('h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
.INIT_1D('h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
.INIT_1E('h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
.INIT_1F('h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
.INIT_20('h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
.INIT_21('h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
.INIT_22('h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
.INIT_23('h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
.INIT_24('h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
.INIT_25('h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
.INIT_26('h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
.INIT_27('h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
.INIT_28('h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
.INIT_29('h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
.INIT_2A('h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
.INIT_2B('h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
.INIT_2C('h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
.INIT_2D('h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
.INIT_2E('h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
.INIT_2F('h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
.INIT_30('h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
.INIT_31('h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
.INIT_32('h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
.INIT_33('h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
.INIT_34('h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
.INIT_35('h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
.INIT_36('h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
.INIT_37('h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
.INIT_38('h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
.INIT_39('h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
.INIT_3A('h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
.INIT_3B('h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
.INIT_3C('h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
.INIT_3D('h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
.INIT_3E('h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
.INIT_3F('h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
.INIT_40('h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
.INIT_41('h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
.INIT_42('h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
.INIT_43('h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
.INIT_44('h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
.INIT_45('h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
.INIT_46('h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
.INIT_47('h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
.INIT_48('h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
.INIT_49('h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
.INIT_4A('h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
.INIT_4B('h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
.INIT_4C('h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
.INIT_4D('h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
.INIT_4E('h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
.INIT_4F('h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
.INIT_50('h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
.INIT_51('h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
.INIT_52('h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
.INIT_53('h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
.INIT_54('h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
.INIT_55('h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
.INIT_56('h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
.INIT_57('h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
.INIT_58('h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
.INIT_59('h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
.INIT_5A('h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
.INIT_5B('h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
.INIT_5C('h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
.INIT_5D('h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
.INIT_5E('h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
.INIT_5F('h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
.INIT_60('h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
.INIT_61('h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
.INIT_62('h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
.INIT_63('h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
.INIT_64('h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
.INIT_65('h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
.INIT_66('h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
.INIT_67('h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
.INIT_68('h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
.INIT_69('h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
.INIT_6A('h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
.INIT_6B('h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
.INIT_6C('h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
.INIT_6D('h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
.INIT_6E('h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
.INIT_6F('h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
.INIT_70('h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
.INIT_71('h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
.INIT_72('h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
.INIT_73('h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
.INIT_74('h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
.INIT_75('h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
.INIT_76('h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
.INIT_77('h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
.INIT_78('h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
.INIT_79('h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
.INIT_7A('h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
.INIT_7B('h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
.INIT_7C('h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
.INIT_7D('h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
.INIT_7E('h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
.INIT_7F('h0000000000000000_0000000000000000_0000000000000000_0000000000000000), // The next set of INITP_xx are for the parity bits
.INITP_00('h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
.INITP_01('h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
.INITP_02('h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
.INITP_03('h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
.INITP_04('h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
.INITP_05('h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
.INITP_06('h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
.INITP_07('h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
.INITP_08('h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
.INITP_09('h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
.INITP_0A('h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
.INITP_0B('h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
.INITP_0C('h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
.INITP_0D('h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
.INITP_0E('h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
.INITP_0F('h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00)
) RAMB36SDP_inst (
.DBITERR(DBITERR), // 1-bit double bit error status output
.SBITERR(SBITERR), // 1-bit single bit error status output
.DO(DO), // 64-bit data output
.DOP(DOP), // 8-bit parity data output
.ECCPARITY(ECCPARITY), // 8-bit generated error correction parity
.RDCLK(RDCLK), // 1-bit read port clock
.RDEN(RDEN), // 1-bit read port enable
.REGCE(REGCE), // 1-bit register enable input
.SSR(SSR), // 1-bit synchronous output set/reset input
.WRCLK(WRCLK), // 1-bit write port clock
.WREN(WREN), // 1-bit write port enable
.WRADDR(WRADDR), // 9-bit write port address input
.RDADDR(RDADDR), // 9-bit read port address input
.DI(DI), // 64-bit data input
.DIP(DIP), // 8-bit parity data input
.WE(WE) // 8-bit write enable input
); // End of RAMB36SDP_inst instantiation
每个36Kb简单双口块RAM（Simple dual-port block RAM）都能被配置为512x64（32Kb）大小的RAM和一个内置的汉明纠错编码（Hamming Error Correction）块，由于要用到汉明纠错编码，所以数据位宽需要多用到8-bit，这样数据位宽就被扩展到72-bit，当数据位宽为72-bit，深度为512时，RAM的大小刚好为36Kb（512 * 72 / 1024 = 36）,其中汉明纠错编码操作对用户是不可见的。每次写操作都会产生8-bit的保护位（原语中的ECCPARITY信号），这个8-bit的保护位在每次读操作的过程中可以用来纠正任何单比特的错误，或者检测（但不能纠正）任何双比特的错误。ECCPARITY输出信号没有可选的输出寄存器。原语中两个状态输出信号（SBITERR和DBITERR）的组合指示了三种可能的读操作结果：无错误（No Error），纠正了单比特错误（Signal Error Corrected）和检测到了双比特错误（Double Error Detected）。在读写操作的ECC（Error Correcting Code）模式均开启时（EN_ECC_READ = TRUE 并且 EN_ECC_WRITE = TRUE，EN_ECC_READ和EN_ECC_WRITE为原语的两个参数），读操作不能再存储器阵列中直接纠正错误，而只能把已经纠正完毕的数据输出给原语中的DO信号。ECC配置选项只有RAMB36SDP原语或FIFO36原语才支持。（此部分内容参考ug190的107页到155页）
Block RAM的ECC（Error Correcting Code）结构如下图所示
RAMB36SDP各个端口的定义如下表所示
|
端口名 |
方向 |
信号描述 |
|
DI[63:0] |
Input |
数据输入总线 |
|
DIP[7:0] |
Input |
数据输入奇偶校验总线 |
|
WRADDR[8:0] |
Input |
写地址总线 |
|
RDADDR[8:0] |
Input |
读地址总线 |
|
WREN |
Input |
写使能。当WREN=1时，数据将被写入存储器，当WREN=0，写操作不使能。 |
|
RDEN |
Input |
读使能。当RDEN=1时，数据将被从存储器读出，当RDEN=0，读操作不使能。 |
|
SSR |
Input |
同步设置/复位（Synchronous Set/Reset），这个信号用来复位输出寄存器的值为SRVAL，SRVAL是RAMB36SDP原语的一个参数。这个信号不会影响存储器存储单元的内容。 |
|
REGCE |
Input |
寄存器使能（Register Enable），端口输出寄存器使能信号。 |
|
WE[7:0] |
Input |
8位的字节写使能输入，由于输出数据总线为64-bit，一共为8个字节，所以字节写使能输入为8位，详细解释见表后的内容。 |
|
WRCLK |
Input |
写操作的时钟 |
|
RDCLK |
Input |
读操作的时钟 |
|
DO[63:0] |
Output |
数据输出总线 |
|
DOP[7:0] |
Output |
数据输出奇偶校验总线 |
|
SBITERR |
Output |
单比特错误（Signal Bit Error）状态 |
|
DBITERR |
Output |
双比特错误（Double Bit Error）状态 |
|
ECCPARITY |
Output |
ECC编码器输出数据总线 |
字节写使能（Byte-Writes）：（此部分内容参考pg058的第50页到51页）
当字节写使能功能打开时，WE总线的宽度为输入数据总线DI中包含的字节个数。例如，输入数据总线DI为64位，包含8个字节，所以WE总线的宽度为8。其中WE总线的最高位对于输入数据总线DI的最高位的字节，WE总线的最低位对于输入数据总线DI的最低位的字节，在写操作过程中，只有WE总线中为1的位对应的字节才能被写入存储器中，为0的位保持原来的值不变。
假设输入数据总线的宽度为24位，它包含3个字节，所以WE的宽度为3，下图是一个字节写使能开启时往RAM的0地址写入数据的时序图（假设RAM的初始值全部为0）
由上图可知，当WEA（也就是上文的WE）为3’b011时，DINA数据24’hFF EE DD的后两个字节会写入存储器的0地址，而存储器0地址的最高字节保持00不变，所以第一次写操作完毕以后存储器0地址的数据为24’h00 EE DD；当WEA（也就是上文的WE）为3’b010时，DINA数据24’hCC BB AA的中间那个字节BB会写入存储器的0地址，而存储器0地址的最高字节和最低字节则保持前一次的00和DD值不变，所以第二次写操作完毕以后存储器0地址的数据为24’h00 BB DD。后面几次操作依次类推即可。
3.4 模块srio_response_gen.v源码分析
模块srio_response_gen.v的作用是产生RapidIO响应事务。RapidIO协议中只有NREAD、DOORBELL、MESSAGE以及NWRITE_R这几种事务有响应事务。
srio_response_gen.v源码的第51行到72行定义了模块的端口。log_clk和log_rst分别为逻辑层时钟与复位，tresp和treq为两个AXI4-Stream通道，tresp是响应事务传输通道，treq是请求事务传输通道。源码如下图所示
第77行到90行定义了HELLO格式包头中的FTYPE字段与TTYPE字段的值，这两个字段的值与事务的类型有关，源码如下图所示
第99行到100行定义了AXI4-Stream总线上有效数据的标志，当tvalid和tready同时为高时，tdata上的数据为有效数据。源代码如下图所示
第161行到163行按照HELLO格式的时序要求，把tkeep信号赋值为8’hFF，把tuser信号由src_id和dest_id拼接而成，并在第一个有效时钟发出去。源代码如下图所示
第193行到203行用来产生HELLO时序中的tready。源代码如下图所示
第205行到220行用来产生treq通道第一拍的标志信号，并把tdata中的数据按照HELLO格式的定义把对应的关键字段剥离出来，值得注意的是第218行优先级字段prio为tdata重对应的字段加1，原因是响应事务的优先级为请求事务的优先级加1，上篇博客也提到过这一点。这部分源代码如下图所示
第224行到第235行用来生成有响应事务的标志，其中RapidiO协议中只有NREAD、DOORBELL、MESSAGE和NWRITE_R这几种事务有对应的响应事务。这部分源代码如下图所示
第240行到274行与本地数据的存储有关。其中第240行到250行的逻辑用来产生数据存取使能位data_store_wen，本文第3.3节提到过，只有地址字段的第23位到第16位为8’h12时，写事务的数据才能被存放到本地存储器，原因就是第243行的判断语句加上了这个判断。第252行到260行的逻辑用来产生数据存储的写地址信号data_store_waddr。第262行到274行的逻辑用来产生数据存储的读地址信号data_store_raddr。源代码如下图所示 
第276行到302行主要例化了一个RAMB36SDP用来存储写事务发送过来的数据。其中第276行用来产生数据存储的读使能标志。源代码如下图所示
第307行到第335行是把请求事务的包头（Header）信息存储在RAM中。其中第307行到308行把请求事务中HELLO格式定义的各个字段进行拼接作为RAM的输入，第325行到第335行用来产生RAM的读地址与写地址。
第337行例化了第二个Block RAM，它用来存储请求事务的HELLO格式信息。
第363行到第372行把从RAM中读出来的数据对应的字段剥离出来从而得到响应事务HELLO格式对应的字段。
第378行到第388行用来产生有效时钟的总数number_of_data_beats以及有效时钟计数器current_beat_cnt。这段逻辑与srio_request_gen.v中对应的逻辑完全一致。源代码如下图所示
第390行到400行用来产生tlast信号，发送最后一个数据时，tlast信号拉高。
第402行和第403行用来产生响应事务的包头（Header），第404行到414行用来产生响应事务的数据，其中响应事务的第一个有效时钟用来发送包头（Header），后面的有效时钟用来发送数据，这段逻辑也与srio_request_gen.v中对应的逻辑类似。源代码如下图所示
第459行到第469行用来产生AXI4-Stream中的tvalid信号，源代码如下
至此，整个响应事务的源代码分析完毕，其余未分析到的代码请自行分析。
3.5 模块srio_quick_start.v源码分析
模块srio_quick_start.v的作用是产生维护事务（Maintenance Transaction）访问本地设备和远程设备的配置空间。维护事务采用的接口协议为AXI4-Lite，它是一种轻量级的AXI4协议，有地址总线与数据总线，常用来实现单个寄存器的读写。在分析srio_quick_start.v源码之前首先分析一下maintenance_list.vh头文件。
分析maintenance_list.vh头文件
maintenance_list.vh头文件主要定义了维护事务相关的字段，其中第1列为2-bit的保留位，第2列为1-bit的远程/本地控制位，第3列为24-bit的地址，第4列为读/写控制位，第5列为32-bit的数据，第6列为4-bit的数据掩码（DATA MASK），部分源代码如下图所示
分析srio_quick_start.v源文件
srio_quick_start.v源文件的第68行到第101行是接口定义。log_clk和log_rst分别为逻辑层的时钟和复位。以maintr_*开头的信号为AXI4-Lite通道的信号，以user_*开头的信号是用户自定义的维护事务的相关字段，go变量用来在用户定义和maintenance_list.vh头文件定义的字段中进行选择
第105行到122行对maintenance_list.vh头文件中的参数进行了赋值，并引入了头文件，源代码如下图所示。
第192行到229行主要用来构建请求包，其本质就是产生AXI4-Lite的协议把数据发出去。部分源代码如下图所示
第233行到386行例化了一个RAMB36SDP原语，并用maintenance_list.vh头文件中定义的数据进行初始化。部分源代码如下图所示
第397行到416行主要负责响应侧的检测，通过maint_autocheck_error和maint_done指示检测状态。源代码如下图所示
至此，维护事务的代码分析完毕，它的代码逻辑相对来说比较简单。
另外，例子工程中还有两个模块srio_report.v和srio_statistics.v，它们只在仿真有用，在硬件上实现时最好删掉。这里不再作过多分析。只要理解了srio_request_gen.v与srio_response_gen.v，用RapidIO完成相关应用就足够了。
五、仿真
工程源码分析完毕以后，接下来就可以开始仿真了。例子工程中的代码一行都不要改，直接左键单击Run Simulation，在弹出的菜单中点击Run Behavioral Simulation，如下图所示
接着会出现下面的滚动框，在这个界面需要等待一会，如下图所示
上面的滚动框运行完毕以后就出现了波形界面，如下图所示
然后再点击下图中圈出的小图标把波形复位一下，如下图所示
复位波形以后在Tcl Console中输入指令：log_wave –r /* 。输入完毕以后按回车。这条指令的作用是记录所有中间变量的波形，这样后面要观察任何变量的波形只需要把它拖到波形界面中它的波形就会自动显示出来而不需要重新仿真，大大节约了时间。如下图所示
最后设置一个比较大的时间，我设置为10ms，然后点击它左边的按钮开始仿真，大约20分钟以后仿真会自动结束，如下图所示
仿真的过程中，在相应的时间点上，Tcl Console中会打印出包的收发情况
最后仿真结束以后，重新回到波形界面可以看到波形都正常产生了。这里最重要的两个信号就是link_initialized与port_initialized，当他们为高表示整个链路初始化完毕。至此，整个仿真过程全部结束，下篇文章会详细介绍每种事务的时序图以及需要注意的一些细节。
六、总结
本节主要分析了一下请求事务与响应事务的Verilog源码，事实上，它们的源码就是按照pg007_srio_gen2.pdf把HELLO格式与HELLO时序描述出来而已。当然官方的这套源码为了尽可能保证测试到核的所有功能，写的比较混乱，但在实际项目中可以充分借鉴它的设计思想，然后根据你自己的需求对不需要的地方进行修改来达到你的目标。除此以外，HELLO格式的时序其通过一个状态机来实现可能更加简洁易懂。总而言之，这套代码具有很大的参考价值，但是要想把这个核玩透还是得自己多在项目中理解。
下篇文章将会教大家如何在Vivado抓出每种事务的时序来对各种RapidIO的交互过程有一个更加清晰的理解。
七、附录
顶层模块srio_example_top_srio_gen2_0.v源码
//
// (c) Copyright 2010 - 2014 Xilinx, Inc. All rights reserved.
//
//
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`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *) module srio_example_top_srio_gen2_0 #(
parameter SIM_VERBOSE = , // If set, generates unsynthesizable reporting
parameter VALIDATION_FEATURES = , // If set, uses internal instruction sequences for hw and sim test
parameter QUICK_STARTUP = , // If set, quick-launch configuration access is contained here
parameter STATISTICS_GATHERING = , // If set, I/O can be rerouted to the maint port [0,1]
parameter C_LINK_WIDTH =
)
// port declarations ----------------
(
// Clocks and Resets
input sys_clkp, // MMCM reference clock
input sys_clkn, // MMCM reference clock input sys_rst, // Global reset signal // high-speed IO
input srio_rxn0, // Serial Receive Data
input srio_rxp0, // Serial Receive Data output srio_txn0, // Serial Transmit Data
output srio_txp0, // Serial Transmit Data input sim_train_en, // Set this only when simulating to reduce the size of counters
output [:] led0 );
// ---------------------------------- // wire declarations ----------------
//
// -----------------------------------------------------------------------------
// Note : Below portion of the wire declaration should be commented when
// used in non-shared mode AND the SRIO core 2nd instance is used to share
// common logic like clk, rst and GT Common with another instance of SRIO
// with Shared Logic (in DUT) option if the simulator throws errors.
// -----------------------------------------------------------------------------
wire log_clk;
wire phy_clk;
wire gt_pcs_clk;
wire log_rst;
wire phy_rst;
wire clk_lock; // asserts from the MMCM
// // signals into the DUT wire ireq_tvalid;
wire ireq_tready;
wire ireq_tlast;
wire [:] ireq_tdata;
wire [:] ireq_tkeep;
wire [:] ireq_tuser; wire iresp_tvalid;
wire iresp_tready;
wire iresp_tlast;
wire [:] iresp_tdata;
wire [:] iresp_tkeep;
wire [:] iresp_tuser; wire treq_tvalid;
wire treq_tready;
wire treq_tlast;
wire [:] treq_tdata;
wire [:] treq_tkeep;
wire [:] treq_tuser; wire tresp_tvalid;
wire tresp_tready;
wire tresp_tlast;
wire [:] tresp_tdata;
wire [:] tresp_tkeep;
wire [:] tresp_tuser; wire maintr_rst = 'b0; wire maintr_awvalid;
wire maintr_awready;
wire [:] maintr_awaddr;
wire maintr_wvalid;
wire maintr_wready;
wire [:] maintr_wdata;
wire maintr_bvalid;
wire maintr_bready;
wire [:] maintr_bresp; wire maintr_arvalid;
wire maintr_arready;
wire [:] maintr_araddr;
wire maintr_rvalid;
wire maintr_rready;
wire [:] maintr_rdata;
wire [:] maintr_rresp; // signals from Validation modules
wire val_ireq_tvalid;
wire val_ireq_tready;
wire val_ireq_tlast;
wire [:] val_ireq_tdata;
wire [:] val_ireq_tkeep;
wire [:] val_ireq_tuser; wire val_iresp_tvalid;
wire val_iresp_tready;
wire val_iresp_tlast;
wire [:] val_iresp_tdata;
wire [:] val_iresp_tkeep;
wire [:] val_iresp_tuser; wire val_treq_tvalid;
wire val_treq_tready;
wire val_treq_tlast;
wire [:] val_treq_tdata;
wire [:] val_treq_tkeep;
wire [:] val_treq_tuser; wire val_tresp_tvalid;
wire val_tresp_tready;
wire val_tresp_tlast;
wire [:] val_tresp_tdata;
wire [:] val_tresp_tkeep;
wire [:] val_tresp_tuser; wire val_maintr_awvalid;
wire val_maintr_awready;
wire [:] val_maintr_awaddr;
wire val_maintr_wvalid;
wire val_maintr_wready;
wire [:] val_maintr_wdata;
wire val_maintr_bvalid;
wire val_maintr_bready;
wire [:] val_maintr_bresp; wire val_maintr_arvalid;
wire val_maintr_arready;
wire [:] val_maintr_araddr;
wire val_maintr_rvalid;
wire val_maintr_rready;
wire [:] val_maintr_rdata;
wire [:] val_maintr_rresp; //--
//----------------------------------------------------------------------------// //-- // other core output signals that may be used by the user
wire [:] port_timeout; // Timeout value user can use to detect a lost packet
wire phy_rcvd_mce; // MCE control symbol received
(* mark_debug = "true" *)
wire phy_rcvd_link_reset; // Received 4 consecutive reset symbols
wire port_error; // In Port Error State
//(* mark_debug = "true" *)// this constraint is commented as it is failing due to new MLO flow
wire mode_1x; // Link is trained down to 1x mode
wire srio_host; // Endpoint is the system host
wire [:] phy_debug; // Useful debug signals wire gtrx_disperr_or; // GT disparity error (reduce ORed) wire gtrx_notintable_or; // GT not in table error (reduce ORed)
wire [:] deviceid; // Device ID
wire port_decode_error; // No valid output port for the RX transaction
(* mark_debug = "true" *)
wire idle_selected; // The IDLE sequence has been selected
(* mark_debug = "true" *)
wire idle2_selected; // The PHY is operating in IDLE2 mode
wire autocheck_error; // when set, packet didn't match expected
(* mark_debug = "true" *)
wire port_initialized; // Port is Initialized
(* mark_debug = "true" *)
wire link_initialized; // Link is Initialized
wire exercise_done; // sets when the generator(s) has completed // other core output signals that may be used by the user
wire phy_mce = 'b0; // Send MCE control symbol
wire phy_link_reset = 'b0; // Send link reset control symbols
wire force_reinit = 'b0; // Force reinitialization // convert to ports when not using the pattern generator wire axis_ireq_tvalid;
wire axis_ireq_tready;
wire axis_ireq_tlast;
wire [:] axis_ireq_tdata;
wire [:] axis_ireq_tkeep;
wire [:] axis_ireq_tuser; wire axis_iresp_tvalid;
wire axis_iresp_tready;
wire axis_iresp_tlast;
wire [:] axis_iresp_tdata;
wire [:] axis_iresp_tkeep;
wire [:] axis_iresp_tuser; wire axis_treq_tvalid;
wire axis_treq_tready;
wire axis_treq_tlast;
wire [:] axis_treq_tdata;
wire [:] axis_treq_tkeep;
wire [:] axis_treq_tuser; wire axis_tresp_tvalid;
wire axis_tresp_tready;
wire axis_tresp_tlast;
wire [:] axis_tresp_tdata;
wire [:] axis_tresp_tkeep;
wire [:] axis_tresp_tuser; wire axis_maintr_rst = 'b0;
wire axis_maintr_awvalid = 'b0;
wire axis_maintr_awready;
wire [:] axis_maintr_awaddr = 'b0;
wire axis_maintr_wvalid = 'b0;
wire axis_maintr_wready;
wire [:] axis_maintr_wdata = 'b0;
wire [:] axis_maintr_wstrb = 'b0;
wire axis_maintr_bvalid;
wire axis_maintr_bready = 'b0;
wire [:] axis_maintr_bresp; wire axis_maintr_arvalid = 'b0;
wire axis_maintr_arready;
wire [:] axis_maintr_araddr = 'b0;
wire axis_maintr_rvalid;
wire axis_maintr_rready = 'b0;
wire [:] axis_maintr_rdata;
wire [:] axis_maintr_rresp; wire ireq_autocheck_error;
wire ireq_request_done;
wire maint_autocheck_error;
wire maint_done; // Vivado debug outputs for control of
(* mark_debug = "true" *)
wire peek_poke_go;
(* mark_debug = "true" *)
wire [:] user_addr;
(* mark_debug = "true" *)
wire [:] user_ftype;
(* mark_debug = "true" *)
wire [:] user_ttype;
(* mark_debug = "true" *)
wire [:] user_size;
(* mark_debug = "true" *)
wire [:] user_data;
(* mark_debug = "true" *)
wire [:] user_hop;
(* mark_debug = "true" *)
wire [:] dest_id;
(* mark_debug = "true" *)
wire [:] source_id;
(* mark_debug = "true" *)
wire id_override;
(* mark_debug = "true" *)
wire register_reset;
(* mark_debug = "true" *)
wire reset_all_registers;
(* mark_debug = "true" *)
wire [:] stats_address;
//(* mark_debug = "true" *)
// wire send_pna;
// (* mark_debug = "true" *)
// wire [2:0] sent_pna_cause_lsb;
// (* mark_debug = "true" *)
// wire in_recoverable_detect;
// (* mark_debug = "true" *)
// wire in_retry_detect;
// (* mark_debug = "true" *)
// wire out_recoverable_detect;
// (* mark_debug = "true" *)
// wire out_fatal_detect; wire core_sent_pna; wire core_received_pna; wire core_sent_pr; wire core_received_pr; // Debug signals
wire go_req = peek_poke_go && user_ftype != 'h8;
wire go_maint = peek_poke_go && user_ftype == 'h8;
wire maint_inst = user_ttype == 'h0;
reg [:] captured_data;
(* mark_debug = "true" *)
wire continuous_go;
reg continuous_go_q;
reg ireq_autocheck_error_q;
reg ireq_request_done_q;
reg reset_request_gen;
(* mark_debug = "true" *)
reg continuous_in_process;
reg reset_continuous_set;
(* mark_debug = "true" *)
reg stop_continuous_test;
reg [:] reset_continuous_srl;
wire [:] stats_data;
// }}} End wire declarations ------------ // {{{ Drive LEDs to Development Board -------
assign led0[] = 'b1;
assign led0[] = 'b1;
assign led0[] = !mode_1x;
assign led0[] = port_initialized;
assign led0[] = link_initialized;
assign led0[] = clk_lock;
assign led0[] = sim_train_en ? autocheck_error : 'b0;
assign led0[] = sim_train_en ? exercise_done : 'b0;
// }}} End LEDs to Development Board --------- // assign send_pna = phy_debug[0];
// assign sent_pna_cause_lsb = phy_debug[34:32];
// assign in_recoverable_detect = phy_debug[40];
// assign in_retry_detect = phy_debug[39];
// assign out_recoverable_detect = phy_debug[38];
// assign out_fatal_detect = phy_debug[37];
// assign send_pna = phy_debug[0];
assign core_sent_pna = phy_debug[];
assign core_received_pna = phy_debug[];
assign core_sent_pr = phy_debug[];
assign core_received_pr = phy_debug[]; assign continuous_go = 'b0;
assign peek_poke_go = 'b0;
assign user_addr = 'b0;
assign user_ftype = 'b0;
assign user_ttype = 'b0;
assign user_size = 'b0;
assign user_data = 'b0;
assign user_hop = 'b0;
assign dest_id = 'b0;
assign source_id = 'b0;
assign id_override = 'b0;
assign register_reset = 'b0;
assign reset_all_registers = 'b0;
assign stats_address = 'b0; // feed back the last captured data to VIO
always @(posedge log_clk) begin
if (log_rst) begin
captured_data <= 'h0;
// IO interface
end else if (iresp_tvalid && iresp_tready) begin
captured_data <= axis_iresp_tdata;
// maintenance interface
end else if (maintr_rvalid && maintr_rready) begin
captured_data <= axis_maintr_rdata;
end
end // Continuous data flow
always @(posedge log_clk) begin
continuous_go_q <= continuous_go;
ireq_request_done_q <= ireq_request_done;
ireq_autocheck_error_q <= ireq_autocheck_error;
reset_request_gen <= sim_train_en ? log_rst : |reset_continuous_srl && continuous_in_process;
end always @(posedge log_clk) begin
if (log_rst) begin
continuous_in_process <= 'b0;
end else if (continuous_go && !continuous_go_q) begin
continuous_in_process <= 'b1;
end else if (!continuous_go && continuous_go_q) begin
continuous_in_process <= 'b0;
end
end
always @(posedge log_clk) begin
if (log_rst) begin
reset_continuous_set <= 'b0;
stop_continuous_test <= 'b0;
end else if (continuous_go && !continuous_go_q) begin
reset_continuous_set <= 'b1;
stop_continuous_test <= 'b0;
end else if (!ireq_autocheck_error_q && ireq_autocheck_error && continuous_in_process) begin
stop_continuous_test <= 'b1;
end else if (!stop_continuous_test && !ireq_request_done_q && ireq_request_done &&
continuous_in_process) begin
reset_continuous_set <= 'b1;
end else begin
reset_continuous_set <= 'b0;
end
end
always @(posedge log_clk) begin
if (log_rst) begin
reset_continuous_srl <= 'h0;
end else if (reset_continuous_set) begin
reset_continuous_srl <= 'hFFFF;
end else begin
reset_continuous_srl <= {reset_continuous_srl[:], 'b0};
end
end // SRIO_DUT instantation -----------------
// for production and shared logic in the core
srio_gen2_0 srio_gen2_0_inst
(//---------------------------------------------------------------
.sys_clkp (sys_clkp ),
.sys_clkn (sys_clkn ),
.sys_rst (sys_rst ),
// all clocks as output in shared logic mode
.log_clk_out (log_clk ),
.phy_clk_out (phy_clk ),
.gt_clk_out (gt_clk ),
.gt_pcs_clk_out (gt_pcs_clk), .drpclk_out (drpclk ), .refclk_out (refclk ), .clk_lock_out (clk_lock ),
// all resets as output in shared logic mode
.log_rst_out (log_rst ),
.phy_rst_out (phy_rst ),
.buf_rst_out (buf_rst ),
.cfg_rst_out (cfg_rst ),
.gt_pcs_rst_out (gt_pcs_rst), //--------------------------------------------------------------- .gt0_qpll_clk_out (gt0_qpll_clk_out ),
.gt0_qpll_out_refclk_out (gt0_qpll_out_refclk_out), // //---------------------------------------------------------------
.srio_rxn0 (srio_rxn0),
.srio_rxp0 (srio_rxp0), .srio_txn0 (srio_txn0),
.srio_txp0 (srio_txp0), .s_axis_ireq_tvalid (ireq_tvalid),
.s_axis_ireq_tready (ireq_tready),
.s_axis_ireq_tlast (ireq_tlast),
.s_axis_ireq_tdata (ireq_tdata),
.s_axis_ireq_tkeep (ireq_tkeep),
.s_axis_ireq_tuser (ireq_tuser), .m_axis_iresp_tvalid (iresp_tvalid),
.m_axis_iresp_tready (iresp_tready),
.m_axis_iresp_tlast (iresp_tlast),
.m_axis_iresp_tdata (iresp_tdata),
.m_axis_iresp_tkeep (iresp_tkeep),
.m_axis_iresp_tuser (iresp_tuser), .s_axis_tresp_tvalid (tresp_tvalid),
.s_axis_tresp_tready (tresp_tready),
.s_axis_tresp_tlast (tresp_tlast),
.s_axis_tresp_tdata (tresp_tdata),
.s_axis_tresp_tkeep (tresp_tkeep),
.s_axis_tresp_tuser (tresp_tuser), .m_axis_treq_tvalid (treq_tvalid),
.m_axis_treq_tready (treq_tready),
.m_axis_treq_tlast (treq_tlast),
.m_axis_treq_tdata (treq_tdata),
.m_axis_treq_tkeep (treq_tkeep),
.m_axis_treq_tuser (treq_tuser), .s_axi_maintr_rst (maintr_rst), .s_axi_maintr_awvalid (maintr_awvalid),
.s_axi_maintr_awready (maintr_awready),
.s_axi_maintr_awaddr (maintr_awaddr),
.s_axi_maintr_wvalid (maintr_wvalid),
.s_axi_maintr_wready (maintr_wready),
.s_axi_maintr_wdata (maintr_wdata),
.s_axi_maintr_bvalid (maintr_bvalid),
.s_axi_maintr_bready (maintr_bready),
.s_axi_maintr_bresp (maintr_bresp), .s_axi_maintr_arvalid (maintr_arvalid),
.s_axi_maintr_arready (maintr_arready),
.s_axi_maintr_araddr (maintr_araddr),
.s_axi_maintr_rvalid (maintr_rvalid),
.s_axi_maintr_rready (maintr_rready),
.s_axi_maintr_rdata (maintr_rdata),
.s_axi_maintr_rresp (maintr_rresp), .sim_train_en (sim_train_en),
.phy_mce (phy_mce),
.phy_link_reset (phy_link_reset),
.force_reinit (force_reinit), .phy_rcvd_mce (phy_rcvd_mce ),
.phy_rcvd_link_reset (phy_rcvd_link_reset),
.phy_debug (phy_debug ),
.gtrx_disperr_or (gtrx_disperr_or ),
.gtrx_notintable_or (gtrx_notintable_or ), .port_error (port_error ),
.port_timeout (port_timeout ),
.srio_host (srio_host ),
.port_decode_error (port_decode_error ),
.deviceid (deviceid ),
.idle2_selected (idle2_selected ),
.phy_lcl_master_enable_out (), // these are side band output only signals
.buf_lcl_response_only_out (),
.buf_lcl_tx_flow_control_out (),
.buf_lcl_phy_buf_stat_out (),
.phy_lcl_phy_next_fm_out (),
.phy_lcl_phy_last_ack_out (),
.phy_lcl_phy_rewind_out (),
.phy_lcl_phy_rcvd_buf_stat_out (),
.phy_lcl_maint_only_out (),
//--- //---
.port_initialized (port_initialized ),
.link_initialized (link_initialized ),
.idle_selected (idle_selected ),
.mode_1x (mode_1x )
);
// End of SRIO_DUT instantiation --------- // Initiator-driven side -------------------- // {{{ IREQ Interface ---------------------------
// Select between internally-driven sequences or user sequences
assign ireq_tvalid = (VALIDATION_FEATURES) ? val_ireq_tvalid : axis_ireq_tvalid;
assign ireq_tlast = (VALIDATION_FEATURES) ? val_ireq_tlast : axis_ireq_tlast;
assign ireq_tdata = (VALIDATION_FEATURES) ? val_ireq_tdata : axis_ireq_tdata;
assign ireq_tkeep = (VALIDATION_FEATURES) ? val_ireq_tkeep : axis_ireq_tkeep;
assign ireq_tuser = (VALIDATION_FEATURES) ? val_ireq_tuser : axis_ireq_tuser; assign axis_ireq_tready = (!VALIDATION_FEATURES) && ireq_tready;
assign val_ireq_tready = (VALIDATION_FEATURES) && ireq_tready; // When enabled, report results.
// This is a simulation-only option and cannot be synthesized
generate if (SIM_VERBOSE) begin: ireq_reporting_gen
srio_report
#(.VERBOSITY (),
.DIRECTION (),
.NAME ()) // Data is flowing into the core
srio_ireq_report_inst
(
.log_clk (log_clk),
.log_rst (log_rst), .tvalid (ireq_tvalid),
.tready (ireq_tready),
.tlast (ireq_tlast),
.tdata (ireq_tdata),
.tkeep (ireq_tkeep),
.tuser (ireq_tuser)
);
end
endgenerate
// }}} End of IREQ Interface -------------------- // {{{ Initiator Generator/Checker -------------- // If internally-driven sequences are required
generate if (VALIDATION_FEATURES) begin: ireq_validation_gen
srio_request_gen_srio_gen2_0
#(.SEND_SWRITE (),
.SEND_NWRITER (),
.SEND_NWRITE (),
.SEND_NREAD (),
.SEND_FTYPE9 (),
.SEND_DB (),
.SEND_MSG ())
srio_request_gen_inst (
.log_clk (log_clk),
.log_rst (reset_request_gen), .deviceid (deviceid),
.dest_id (dest_id),
.source_id (source_id),
.id_override (id_override), .val_ireq_tvalid (val_ireq_tvalid),
.val_ireq_tready (val_ireq_tready),
.val_ireq_tlast (val_ireq_tlast),
.val_ireq_tdata (val_ireq_tdata),
.val_ireq_tkeep (val_ireq_tkeep),
.val_ireq_tuser (val_ireq_tuser), .val_iresp_tvalid (val_iresp_tvalid),
.val_iresp_tready (val_iresp_tready),
.val_iresp_tlast (val_iresp_tlast),
.val_iresp_tdata (val_iresp_tdata),
.val_iresp_tkeep (val_iresp_tkeep),
.val_iresp_tuser (val_iresp_tuser), .link_initialized (link_initialized), // use these ports to peek/poke IO transactions
.go (go_req),
.user_addr ({'h000, user_addr}),
.user_ftype (user_ftype),
.user_ttype (user_ttype),
.user_size (user_size),
.user_data (user_data), .request_autocheck_error (ireq_autocheck_error),
.request_done (ireq_request_done)
);
end
endgenerate
// }}} End of Initiator Generator/Checker ------- // {{{ IRESP Interface --------------------------
// Select between internally-driven sequences or user sequences assign iresp_tready = (VALIDATION_FEATURES) ? val_iresp_tready : axis_iresp_tready; assign val_iresp_tvalid = (VALIDATION_FEATURES) && iresp_tvalid;
assign val_iresp_tlast = iresp_tlast;
assign val_iresp_tdata = iresp_tdata;
assign val_iresp_tkeep = iresp_tkeep;
assign val_iresp_tuser = iresp_tuser; assign axis_iresp_tvalid = (!VALIDATION_FEATURES) && iresp_tvalid;
assign axis_iresp_tlast = iresp_tlast;
assign axis_iresp_tdata = iresp_tdata;
assign axis_iresp_tkeep = iresp_tkeep;
assign axis_iresp_tuser = iresp_tuser; // When enabled, report results.
// This is a simulation-only option and cannot be synthesized
generate if (SIM_VERBOSE) begin: iresp_reporting_gen
srio_report
#(.VERBOSITY (),
.DIRECTION (),
.NAME ()) // Data is flowing out of the core
srio_iresp_report_inst
(
.log_clk (log_clk),
.log_rst (log_rst), .tvalid (iresp_tvalid),
.tready (iresp_tready),
.tlast (iresp_tlast),
.tdata (iresp_tdata),
.tkeep (iresp_tkeep),
.tuser (iresp_tuser)
);
end
endgenerate
// }}} End of IRESP Interface ------------------- assign autocheck_error = ireq_autocheck_error || maint_autocheck_error;
assign exercise_done = ireq_request_done && maint_done; // }}} End of Initiator-driven side ------------- // {{{ Target-driven side ----------------------- // {{{ TRESP Interface --------------------------
// Select between internally-driven sequences or user sequences
assign tresp_tvalid = (VALIDATION_FEATURES) ? val_tresp_tvalid : axis_tresp_tvalid;
assign tresp_tlast = (VALIDATION_FEATURES) ? val_tresp_tlast : axis_tresp_tlast;
assign tresp_tdata = (VALIDATION_FEATURES) ? val_tresp_tdata : axis_tresp_tdata;
assign tresp_tkeep = (VALIDATION_FEATURES) ? val_tresp_tkeep : axis_tresp_tkeep;
assign tresp_tuser = (VALIDATION_FEATURES) ? val_tresp_tuser : axis_tresp_tuser; assign axis_tresp_tready = (!VALIDATION_FEATURES) && tresp_tready;
assign val_tresp_tready = (VALIDATION_FEATURES) && tresp_tready; // When enabled, report results.
// This is a simulation-only option and cannot be synthesized
generate if (SIM_VERBOSE) begin: tresp_reporting_gen
srio_report
#(.VERBOSITY (),
.DIRECTION (),
.NAME ()) // Data is flowing into the core
srio_tresp_report_inst
(
.log_clk (log_clk),
.log_rst (log_rst), .tvalid (tresp_tvalid),
.tready (tresp_tready),
.tlast (tresp_tlast),
.tdata (tresp_tdata),
.tkeep (tresp_tkeep),
.tuser (tresp_tuser)
);
end
endgenerate
// }}} End of TRESP Interface ------------------- // {{{ Target Generator/Checker ----------------- // If internally-driven sequences are required
generate if (VALIDATION_FEATURES) begin: tresp_validation_gen
srio_response_gen_srio_gen2_0 srio_response_gen_inst (
.log_clk (log_clk),
.log_rst (log_rst), .deviceid (deviceid),
.source_id (source_id),
.id_override (id_override), .val_tresp_tvalid (val_tresp_tvalid),
.val_tresp_tready (val_tresp_tready),
.val_tresp_tlast (val_tresp_tlast),
.val_tresp_tdata (val_tresp_tdata),
.val_tresp_tkeep (val_tresp_tkeep),
.val_tresp_tuser (val_tresp_tuser), .val_treq_tvalid (val_treq_tvalid),
.val_treq_tready (val_treq_tready),
.val_treq_tlast (val_treq_tlast),
.val_treq_tdata (val_treq_tdata),
.val_treq_tkeep (val_treq_tkeep),
.val_treq_tuser (val_treq_tuser)
);
end
endgenerate
// }}} End of Target Generator/Checker ---------- // {{{ TREQ Interface ---------------------------
// Select between internally-driven sequences or user sequences assign treq_tready = (VALIDATION_FEATURES) ? val_treq_tready : axis_treq_tready; assign val_treq_tvalid = (VALIDATION_FEATURES) && treq_tvalid;
assign val_treq_tlast = treq_tlast;
assign val_treq_tdata = treq_tdata;
assign val_treq_tkeep = treq_tkeep;
assign val_treq_tuser = treq_tuser; assign axis_treq_tvalid = (!VALIDATION_FEATURES) && treq_tvalid;
assign axis_treq_tlast = treq_tlast;
assign axis_treq_tdata = treq_tdata;
assign axis_treq_tkeep = treq_tkeep;
assign axis_treq_tuser = treq_tuser; // When enabled, report results.
// This is a simulation-only option and cannot be synthesized
generate if (SIM_VERBOSE) begin: treq_reporting_gen
srio_report
#(.VERBOSITY (),
.DIRECTION (),
.NAME ()) // Data is flowing out of the core
srio_treq_report_inst
(
.log_clk (log_clk),
.log_rst (log_rst), .tvalid (treq_tvalid),
.tready (treq_tready),
.tlast (treq_tlast),
.tdata (treq_tdata),
.tkeep (treq_tkeep),
.tuser (treq_tuser)
);
end
endgenerate
// }}} End of TREQ Interface -------------------- // }}} End of Target-driven side ---------------- // {{{ Maintenance Interface -------------------- // Select between internally-driven sequences or user sequences
assign maintr_awvalid = (QUICK_STARTUP) ? val_maintr_awvalid : axis_maintr_awvalid;
assign maintr_awaddr = (QUICK_STARTUP) ? val_maintr_awaddr : axis_maintr_awaddr;
assign maintr_wvalid = (QUICK_STARTUP) ? val_maintr_wvalid : axis_maintr_wvalid;
assign maintr_wdata = (QUICK_STARTUP) ? val_maintr_wdata : axis_maintr_wdata;
assign maintr_bready = (QUICK_STARTUP) ? val_maintr_bready : axis_maintr_bready; assign maintr_arvalid = (QUICK_STARTUP) ? val_maintr_arvalid : axis_maintr_arvalid;
assign maintr_araddr = (QUICK_STARTUP) ? val_maintr_araddr : axis_maintr_araddr;
assign maintr_rready = (QUICK_STARTUP) ? val_maintr_rready : axis_maintr_rready; assign axis_maintr_awready = (!QUICK_STARTUP) && maintr_awready;
assign axis_maintr_wready = (!QUICK_STARTUP) && maintr_wready;
assign axis_maintr_bvalid = (!QUICK_STARTUP) && maintr_bvalid;
assign axis_maintr_bresp = maintr_bresp; assign axis_maintr_arready = (!QUICK_STARTUP) && maintr_arready;
assign axis_maintr_rvalid = (!QUICK_STARTUP) && maintr_rvalid;
assign axis_maintr_rdata = maintr_rdata;
assign axis_maintr_rresp = maintr_rresp; assign val_maintr_awready = (QUICK_STARTUP) && maintr_awready;
assign val_maintr_wready = (QUICK_STARTUP) && maintr_wready;
assign val_maintr_bvalid = (QUICK_STARTUP) && maintr_bvalid;
assign val_maintr_bresp = maintr_bresp; assign val_maintr_arready = (QUICK_STARTUP) && maintr_arready;
assign val_maintr_rvalid = (QUICK_STARTUP) && maintr_rvalid;
assign val_maintr_rdata = maintr_rdata;
assign val_maintr_rresp = maintr_rresp; // If internally-driven sequences are required
generate if (QUICK_STARTUP) begin: quick_maint_gen
srio_quick_start_srio_gen2_0 srio_quick_start_inst (
.log_clk (log_clk),
.log_rst (log_rst), .maintr_awvalid (val_maintr_awvalid),
.maintr_awready (val_maintr_awready),
.maintr_awaddr (val_maintr_awaddr),
.maintr_wvalid (val_maintr_wvalid),
.maintr_wready (val_maintr_wready),
.maintr_wdata (val_maintr_wdata),
.maintr_bvalid (val_maintr_bvalid),
.maintr_bready (val_maintr_bready),
.maintr_bresp (val_maintr_bresp), .maintr_arvalid (val_maintr_arvalid),
.maintr_arready (val_maintr_arready),
.maintr_araddr (val_maintr_araddr),
.maintr_rvalid (val_maintr_rvalid),
.maintr_rready (val_maintr_rready),
.maintr_rdata (val_maintr_rdata),
.maintr_rresp (val_maintr_rresp), // use these ports to peek/poke maintenance transactions
.go (go_maint),
.user_hop (user_hop),
.user_inst (maint_inst),
.user_addr (user_addr),
.user_data (user_data[:]), .link_initialized (link_initialized),
.maint_done (maint_done),
.maint_autocheck_error (maint_autocheck_error)
);
end else begin : no_quick_maint_gen
assign maintr_awaddr = 'h0;
assign maintr_wvalid = 'b0;
assign maintr_wdata = 'h0;
assign maintr_bready = 'b0;
assign maintr_arvalid = 'b0;
assign maintr_araddr = 'h0;
assign maintr_rready = 'b0;
assign maint_done = 'b1;
assign maint_autocheck_error = 'b0;
end
endgenerate // }}} End of Maintenance Interface ------------- // {{{ Statistics Gatherer ---------------------- // When enabled, statistics gatherer collects details about performance.
// This module is synthesizable and may be accessed through Chipscope
generate if (STATISTICS_GATHERING) begin: stats_gen
srio_statistics_srio_gen2_0 srio_statistics_inst (
.log_clk (log_clk),
.phy_clk (phy_clk),
.gt_pcs_clk (gt_pcs_clk),
.log_rst (log_rst),
.phy_rst (phy_rst), // outgoing port 1
.tvalid_o1 (ireq_tvalid),
.tready_o1 (ireq_tready),
.tlast_o1 (ireq_tlast),
.tdata_o1 (ireq_tdata), // outgoing port 2
.tvalid_o2 (iresp_tvalid),
.tready_o2 (iresp_tready),
.tlast_o2 (iresp_tlast),
.tdata_o2 (iresp_tdata), // incoming port 1
.tvalid_i1 (treq_tvalid),
.tready_i1 (treq_tready),
.tlast_i1 (treq_tlast),
.tdata_i1 (treq_tdata), // incoming port 2
.tvalid_i2 (tresp_tvalid),
.tready_i2 (tresp_tready),
.tlast_i2 (tresp_tlast),
.tdata_i2 (tresp_tdata), .link_initialized (link_initialized),
.phy_debug (phy_debug),
.gtrx_disperr_or (gtrx_disperr_or),
.gtrx_notintable_or (gtrx_notintable_or), .register_reset (register_reset),
.reset_all_registers (reset_all_registers),
.stats_address (stats_address), .stats_data (stats_data)
);
end
endgenerate // }}} End of Statistics Gatherer --------------- endmodule
srio_request_gen_srio_gen2_0.v源码
//
// (c) Copyright 2010 - 2014 Xilinx, Inc. All rights reserved.
//
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
`timescale 1ps/1ps module srio_request_gen_srio_gen2_0
#(
parameter SEND_SWRITE = ,
parameter SEND_NWRITER = ,
parameter SEND_NWRITE = ,
parameter SEND_NREAD = ,
parameter SEND_DB = ,
parameter SEND_FTYPE9 = ,
parameter SEND_MSG = )
(
input log_clk,
input log_rst, input [:] deviceid,
input [:] dest_id,
input [:] source_id,
input id_override, output reg val_ireq_tvalid,
input val_ireq_tready,
output reg val_ireq_tlast,
output reg [:] val_ireq_tdata,
output [:] val_ireq_tkeep,
output [:] val_ireq_tuser, input val_iresp_tvalid,
output reg val_iresp_tready,
input val_iresp_tlast,
input [:] val_iresp_tdata,
input [:] val_iresp_tkeep,
input [:] val_iresp_tuser, input link_initialized,
input go,
input [:] user_addr,
input [:] user_ftype,
input [:] user_ttype,
input [:] user_size,
input [:] user_data, output reg request_autocheck_error,
output reg request_done
); // {{{ local parameters ----------------- localparam [:] NREAD = 'h2;
localparam [:] NWRITE = 'h5;
localparam [:] SWRITE = 'h6;
localparam [:] DOORB = 'hA;
localparam [:] MESSG = 'hB;
localparam [:] RESP = 'hD;
localparam [:] FTYPE9 = 'h9; localparam [:] TNWR = 'h4;
localparam [:] TNWR_R = 'h5;
localparam [:] TNRD = 'h4; localparam [:] TNDATA = 'h0;
localparam [:] MSGRSP = 'h1;
localparam [:] TWDATA = 'h8; // }}} End local parameters ------------- // {{{ wire declarations ----------------
reg [:] log_rst_shift;
wire log_rst_q = log_rst_shift[]; //synthesis attribute ram_style of instruction is distributed
wire [:] instruction [:];
`include "instruction_list.vh" reg [:] link_initialized_cnt;
wire link_initialized_delay = link_initialized_cnt[]; wire ireq_advance_condition = val_ireq_tready && val_ireq_tvalid;
wire iresp_advance_condition = val_iresp_tready && val_iresp_tvalid; // request side
wire [:] request_data_out;
reg [:] request_data_out_q; // upper 63:48 unused
reg auto_advance_data;
reg [:] request_address; wire [:] src_id;
wire [:] prio;
wire [:] tid;
wire [:] srio_addr;
wire [:] header_beat; wire [:] current_ftype;
wire [:] current_ttype;
wire [:] current_size;
wire [:] current_size_ftype9;
wire [:] number_of_data_beats;
wire [:] number_of_data_beats_ftype9;
reg [:] number_of_data_beats_q;
reg [:] number_of_data_beats_q_ftype9;
reg [:] current_beat_cnt;
reg [:] current_beat_cnt_ftype9; reg last_packet_beat_q, last_packet_beat_qq, last_packet_beat_qqq;
reg [:] data_beat, data_beat_q;
reg [:] instruction_cnt;
reg sent_all_packets; reg go_q; // response check side
reg expecting_a_response;
reg [:] write_queue_addr;
reg [:] read_queue_addr;
wire [:] write_queue_data_d;
reg [:] write_queue_data;
wire [:] read_queue_data;
reg [:] read_queue_data_q;
reg compare_received;
wire [:] expected_ftype;
wire [:] expected_tid;
wire [:] expected_size;
reg delay_assert_tready; // }}} End wire declarations ------------ // {{{ Common-use Signals ---------------
// Initialize instruction list
genvar ii;
generate
for (ii = ; ii < ; ii = ii + ) begin : instruction_gen
// Load SWRITEs
if(ii < NUM_SWRITES) begin
assign instruction[ii] = swrite_instruction[(ii+)*-:ii*];
// Load NWRITE_Rs
end else if(ii < (NUM_SWRITES + NUM_NWRITERS)) begin
assign instruction[ii] = nwriter_instruction[(ii-NUM_SWRITES+)*-:(ii-NUM_SWRITES)*];
// Load NWRITEs
end else if(ii < (NUM_SWRITES + NUM_NWRITERS + NUM_NWRITES)) begin
assign instruction[ii] = nwrite_instruction[(ii-NUM_SWRITES-NUM_NWRITERS+)*-:(ii-NUM_SWRITES-NUM_NWRITERS)*];
// Load NREADs
end else if(ii < (NUM_SWRITES + NUM_NWRITERS + NUM_NWRITES + NUM_NREADS)) begin
assign instruction[ii] = nread_instruction[(ii-NUM_SWRITES-NUM_NWRITERS-NUM_NWRITES+)*-:(ii-NUM_SWRITES-NUM_NWRITERS-NUM_NWRITES)*];
// Load DBs
end else if(ii < (NUM_SWRITES + NUM_NWRITERS + NUM_NWRITES + NUM_NREADS + NUM_DBS)) begin
assign instruction[ii] = db_instruction[(ii-NUM_SWRITES-NUM_NWRITERS-NUM_NWRITES-NUM_NREADS+)*-:(ii-NUM_SWRITES-NUM_NWRITERS-NUM_NWRITES-NUM_NREADS)*];
// Load MSGs
end else if(ii < (NUM_SWRITES + NUM_NWRITERS + NUM_NWRITES + NUM_NREADS + NUM_DBS + NUM_MSGS)) begin
assign instruction[ii] = msg_instruction[(ii-NUM_SWRITES-NUM_NWRITERS-NUM_NWRITES-NUM_NREADS-NUM_DBS+)*-:(ii-NUM_SWRITES-NUM_NWRITERS-NUM_NWRITES-NUM_NREADS-NUM_DBS)*];
end else if(ii < (NUM_SWRITES + NUM_NWRITERS + NUM_NWRITES + NUM_NREADS + NUM_DBS + NUM_MSGS + NUM_FTYPE9)) begin
assign instruction[ii] = ftype9_instruction[(ii-NUM_SWRITES-NUM_NWRITERS-NUM_NWRITES-NUM_NREADS-NUM_DBS-NUM_MSGS+)*-:(ii-NUM_SWRITES-NUM_NWRITERS-NUM_NWRITES-NUM_NREADS-NUM_DBS-NUM_MSGS)*];
end else begin
assign instruction[ii] = 'h0;
end
end
endgenerate // Simple Assignments
assign val_ireq_tkeep = 'hFF;
assign src_id = id_override ? source_id : deviceid;
assign prio = 'h1;
assign val_ireq_tuser = {src_id, dest_id};
assign tid = request_address[:];
assign srio_addr = go ? user_addr : request_data_out_q[:];
assign current_ftype = go ? user_ftype : request_data_out[:];
assign current_ttype = go ? user_ttype : request_data_out_q[:];
assign current_size = go ? user_size : request_data_out_q[:];
assign current_size_ftype9 = go ? {user_size,user_size} : request_data_out_q[:];
// //Fixed CR# 799600, 12/15/2014, Added ftype switch for message in below header in place of plain "tid" field.
assign header_beat = {((current_ftype == MESSG)? request_data_out[:] : tid), current_ftype, current_ttype, 'b0, prio, 1'b0, current_size, srio_addr};
// End Simple Assignments always @(posedge log_clk or posedge log_rst) begin
if (log_rst)
log_rst_shift <= 'hFFFF;
else
log_rst_shift <= {log_rst_shift[:], 'b0};
end always @(posedge log_clk) begin
if (log_rst_q) begin
last_packet_beat_q <= 'b1;
last_packet_beat_qq <= 'b1;
last_packet_beat_qqq <= 'b1;
number_of_data_beats_q <= 'h0;
number_of_data_beats_q_ftype9 <= 'h0;
read_queue_data_q <= 'h0;
go_q <= 'b0;
end else begin
last_packet_beat_q <= ireq_advance_condition && val_ireq_tlast;
last_packet_beat_qq <= last_packet_beat_q;
last_packet_beat_qqq <= last_packet_beat_qq || !link_initialized_delay;
number_of_data_beats_q <= number_of_data_beats;
number_of_data_beats_q_ftype9 <= number_of_data_beats_ftype9;
read_queue_data_q <= read_queue_data;
go_q <= go;
end
end // put a sufficient delay on the initialization to improve simulation time.
// Not needed for actual hardware but does no damage if kept.
always @(posedge log_clk) begin
if (log_rst_q) begin
link_initialized_cnt <= ;
end else if (link_initialized && !link_initialized_delay) begin
link_initialized_cnt <= link_initialized_cnt + 'b1;
end else if (!link_initialized) begin
link_initialized_cnt <= ;
end
end // }}} End Common-use Signals ----------- // {{{ Request Packet Formatter ---------
assign number_of_data_beats = current_beat_cnt == ? current_size[:] : number_of_data_beats_q; assign number_of_data_beats_ftype9 = current_beat_cnt_ftype9 == ? current_size_ftype9[:] : number_of_data_beats_q_ftype9; always @(posedge log_clk) begin
if (log_rst_q) begin
current_beat_cnt <= 'h0;
end else if (ireq_advance_condition && val_ireq_tlast) begin
current_beat_cnt <= 'h0;
end else if (ireq_advance_condition) begin
current_beat_cnt <= current_beat_cnt + 'b1;
end
end always @(posedge log_clk) begin
if (log_rst_q) begin
current_beat_cnt_ftype9 <= 'h000;
end else if (ireq_advance_condition && val_ireq_tlast) begin
current_beat_cnt_ftype9 <= 'h000;
end else if (ireq_advance_condition) begin
current_beat_cnt_ftype9 <= current_beat_cnt_ftype9 + 'b1;
end
end wire [:] extended_number_of_data_beats_ftype9; assign extended_number_of_data_beats_ftype9 = {'b0, number_of_data_beats_ftype9}; always @(posedge log_clk) begin
if (log_rst_q) begin
val_ireq_tlast <= 'b0;
end else if (((current_ftype == NREAD) || (current_ftype == DOORB)) && current_beat_cnt == 'h00) begin
val_ireq_tlast <= !(ireq_advance_condition && val_ireq_tlast);
end else if ((current_beat_cnt == {'b0, number_of_data_beats} && ireq_advance_condition && (current_ftype != FTYPE9)) || ((current_beat_cnt_ftype9 == extended_number_of_data_beats_ftype9) && ireq_advance_condition && (current_ftype == FTYPE9) )) begin
val_ireq_tlast <= !val_ireq_tlast;
end else if (!val_ireq_tready) begin
val_ireq_tlast <= val_ireq_tlast;
end else if (val_ireq_tready || !val_ireq_tvalid) begin
val_ireq_tlast <= 'b0;
end
end
always @(posedge log_clk) begin
if ((current_beat_cnt == && !ireq_advance_condition && (current_ftype != FTYPE9)) || (current_beat_cnt_ftype9 == && !ireq_advance_condition && (current_ftype == FTYPE9))) begin
val_ireq_tdata <= header_beat;
end else if (go) begin
val_ireq_tdata <= user_data;
end else begin
val_ireq_tdata <= {{data_beat}};
end
end
always @* begin
data_beat = data_beat_q;
if (ireq_advance_condition && current_beat_cnt != ) begin
data_beat = data_beat_q + 'b1;
end
end
always @(posedge log_clk) begin
if (log_rst_q) begin
data_beat_q <= 'h00;
end else begin
data_beat_q <= data_beat;
end
end always @(posedge log_clk) begin
if (log_rst_q) begin
val_ireq_tvalid <= 'b0;
instruction_cnt <= 'h0;
sent_all_packets <= 'b0;
end else if (link_initialized_delay && instruction_cnt < NUMBER_OF_INSTRUCTIONS && last_packet_beat_qqq) begin
val_ireq_tvalid <= 'b1;
end else if (ireq_advance_condition && val_ireq_tlast) begin
val_ireq_tvalid <= 'b0;
instruction_cnt <= instruction_cnt + 'b1;
end else if (go && !go_q) begin
val_ireq_tvalid <= 'b1;
end else if (instruction_cnt == NUMBER_OF_INSTRUCTIONS) begin
sent_all_packets <= 'b1;
end
end // }}} End Request Packet Formatter ----- // {{{ Request Data Storage -------------
always @(posedge log_clk) begin
if (log_rst_q) begin
request_address <= 'h0;
end else if ((ireq_advance_condition && current_beat_cnt == && (current_ftype != FTYPE9)) || ((current_beat_cnt_ftype9 == extended_number_of_data_beats_ftype9) && ireq_advance_condition && (current_ftype == FTYPE9))) begin
request_address <= request_address + 'b1;
end
end assign request_data_out = instruction[request_address]; always @ (posedge log_clk) begin
if (ireq_advance_condition || auto_advance_data || last_packet_beat_qq)
request_data_out_q <= request_data_out[:];
end
always @ (posedge log_clk) begin
if (log_rst_q) begin
auto_advance_data <= 'b1;
end else if (ireq_advance_condition) begin
auto_advance_data <= 'b0;
end
end
// }}} End of Request Data Storage ------ // {{{ Response Queue ------------------- assign write_queue_data_d = {'h0, tid, current_ftype, current_size};
always @ (posedge log_clk) begin
write_queue_data <= write_queue_data_d;
end RAMB36SDP #(
.SIM_COLLISION_CHECK("NONE"),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE")
)
response_queue_inst (
.DI (write_queue_data),
.DIP ('h0),
.RDADDR (read_queue_addr),
.RDCLK (log_clk),
.RDEN ('b1),
.REGCE ('b1),
.SSR (log_rst),
.WE ({{expecting_a_response}}),
.WRADDR (write_queue_addr),
.WRCLK (log_clk),
.WREN (expecting_a_response), .DO (read_queue_data),
.DOP (), .ECCPARITY (),
.SBITERR (),
.DBITERR ()
); assign expected_tid = read_queue_data_q[:];
assign expected_ftype = read_queue_data_q[:];
assign expected_size = read_queue_data_q[:];
// }}} End of Response Queue ------------ // {{{ Response Side Check -------------- // collect outgoing requests that require a response, queue them
always @(posedge log_clk) begin
if (log_rst_q) begin
expecting_a_response <= 'b0;
end else if (current_beat_cnt == && ireq_advance_condition) begin
expecting_a_response <= (current_ftype == NREAD) ||
(current_ftype == DOORB) ||
(current_ftype == MESSG) ||
((current_ftype == NWRITE) && (current_ttype == TNWR_R));
end else begin
expecting_a_response <= 'b0;
end
end
always @(posedge log_clk) begin
if (log_rst_q) begin
write_queue_addr <= 'h000;
end else if (expecting_a_response) begin
write_queue_addr <= write_queue_addr + ;
end
end always @(posedge log_clk) begin
if (log_rst_q) begin
read_queue_addr <= 'h000;
request_done <= 'b0;
compare_received <= 'b1;
end else if (iresp_advance_condition && val_iresp_tlast && sent_all_packets &&
(write_queue_addr == read_queue_addr + )) begin
request_done <= 'b1;
compare_received <= 'b0;
end else if (sent_all_packets && (write_queue_addr == read_queue_addr)) begin
request_done <= 'b1;
compare_received <= 'b0;
end else if (iresp_advance_condition && val_iresp_tlast && !request_autocheck_error) begin
read_queue_addr <= read_queue_addr + ;
compare_received <= 'b1;
end else if (iresp_advance_condition) begin
compare_received <= 'b0;
end
end always @ (posedge log_clk) begin
if (log_rst_q) begin
request_autocheck_error <= 'b0;
end else if (compare_received && iresp_advance_condition) begin
if(expected_tid != val_iresp_tdata[:]) begin
// TID mismatch means an error unless it's a message response (MSGs don't use TID)
if (!(expected_ftype == MESSG) || !(val_iresp_tdata[:] == MSGRSP)) begin
request_autocheck_error <= 'b1;
$display ("\t *** TID mismatch Error ***");
end
// expecting a Read response
end else if (expected_ftype == NREAD && !(val_iresp_tdata[:] == TWDATA)) begin
request_autocheck_error <= 'b1;
$display ("\t *** NREAD Read Response Not Received ***");
// expecting a Response without data
end else if (expected_ftype == NWRITE && !(val_iresp_tdata[:] == TNDATA)) begin
request_autocheck_error <= 'b1;
$display ("\t *** NWRITE Response Without Data Error ***");
// expecting a Response without data
end else if (expected_ftype == DOORB && !(val_iresp_tdata[:] == TNDATA)) begin
request_autocheck_error <= 'b1;
$display ("\t *** DOORB Response Without Data Error ***");
end
end
end always @ (posedge log_clk) begin
if (log_rst_q) begin
val_iresp_tready <= 'b0;
delay_assert_tready <= 'b0; end else if (iresp_advance_condition && val_iresp_tlast) begin
val_iresp_tready <= 'b0;
delay_assert_tready <= 'b1;
end else if (delay_assert_tready) begin
val_iresp_tready <= 'b0;
delay_assert_tready <= 'b0;
end else begin
val_iresp_tready <= 'b1;
delay_assert_tready <= 'b0;
end
end // }}} End Response Side Check ---------- endmodule
// {{{ DISCLAIMER OF LIABILITY
// -----------------------------------------------------------------
// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
// }}}
srio_response_gen_srio_gen2_0.v源码
//
// (c) Copyright 2010 - 2014 Xilinx, Inc. All rights reserved.
//
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES. `timescale 1ps/1ps module srio_response_gen_srio_gen2_0 (
input log_clk,
input log_rst, input [:] deviceid,
input [:] source_id,
input id_override, output reg val_tresp_tvalid,
input val_tresp_tready,
output reg val_tresp_tlast,
output reg [:] val_tresp_tdata,
output [:] val_tresp_tkeep,
output [:] val_tresp_tuser, input val_treq_tvalid,
output reg val_treq_tready,
input val_treq_tlast,
input [:] val_treq_tdata,
input [:] val_treq_tkeep,
input [:] val_treq_tuser
); // {{{ local parameters ----------------- localparam [:] NREAD = 'h2;
localparam [:] NWRITE = 'h5;
localparam [:] SWRITE = 'h6;
localparam [:] DOORB = 'hA;
localparam [:] MESSG = 'hB;
localparam [:] RESP = 'hD; localparam [:] TNWR = 'h4;
localparam [:] TNWR_R = 'h5;
localparam [:] TNRD = 'h4; localparam [:] TNDATA = 'h0;
localparam [:] MSGRSP = 'h1;
localparam [:] TWDATA = 'h8; // }}} End local parameters ------------- // {{{ wire declarations ----------------
reg [:] log_rst_shift;
wire log_rst_q = log_rst_shift[]; wire treq_advance_condition = val_treq_tready && val_treq_tvalid;
wire tresp_advance_condition = val_tresp_tready && val_tresp_tvalid; // request side
wire [:] response_data_in_d;
reg [:] response_data_in;
reg [:] response_wr_address; reg generate_a_response;
reg first_beat; // data storage
reg capture_data;
reg [:] data_store_waddr;
reg [:] data_store_raddr;
wire data_store_wen;
wire data_store_ren;
wire [:] data_store_dout; // incoming packet fields
wire [:] current_tid;
wire [:] current_ftype;
wire [:] current_ttype;
wire [:] current_size;
wire [:] current_prio;
wire [:] current_addr;
wire [:] current_srcid;
wire [:] dest_id;
wire [:] src_id;
// outgoing packet fields
wire [:] response_tid;
wire [:] response_ftype;
wire [:] response_ttype;
wire [:] response_size;
wire [:] response_prio;
wire [:] response_data_out_d;
reg [:] response_data_out; // upper 63:47 unused
wire [:] starting_read_addr;
wire pull_from_store;
reg pull_from_store_q;
reg [:] response_rd_address;
reg addresses_differ;
reg out_of_packet;
wire rd_increment;
reg rd_increment_q, rd_increment_qq, rd_increment_qqq, rd_increment_qqqq;
reg before_first_beat;
reg first_packet_transfer;
reg first_packet_transfer_q; wire [:] responding_ttype;
wire [:] header_beat;
wire [:] number_of_data_beats;
reg [:] number_of_data_beats_q;
reg [:] current_beat_cnt;
reg [:] data_beat, data_beat_q; // }}} End wire declarations ------------ // {{{ Common-use Signals --------------- // Simple Assignments
assign val_tresp_tkeep = 'hFF;
assign src_id = id_override ? source_id : deviceid;
assign val_tresp_tuser = {src_id, dest_id};
// End Simple Assignments always @(posedge log_clk or posedge log_rst) begin
if (log_rst)
log_rst_shift <= 'hFFFF;
else
log_rst_shift <= {log_rst_shift[:], 'b0};
end always @(posedge log_clk) begin
if (log_rst_q) begin
number_of_data_beats_q <= 'h0;
rd_increment_q <= 'b0;
rd_increment_qq <= 'b0;
rd_increment_qqq <= 'b0;
rd_increment_qqqq <= 'b0;
end else begin
number_of_data_beats_q <= number_of_data_beats;
rd_increment_q <= rd_increment;
rd_increment_qq <= rd_increment_q;
rd_increment_qqq <= rd_increment_qq;
rd_increment_qqqq <= rd_increment_qqq;
end
end
// }}} End Common-use Signals ----------- // {{{ Request Logic -------------------- always @(posedge log_clk) begin
if (log_rst_q) begin
val_treq_tready <= 'b0;
// buffer full condition
end else if (((response_wr_address + 'h1) == response_rd_address) ||
((response_wr_address + 'h2) == response_rd_address)) begin
val_treq_tready <= 'b0;
end else begin
val_treq_tready <= 'b1;
end
end always @(posedge log_clk) begin
if (log_rst_q) begin
first_beat <= 'b1;
end else if (treq_advance_condition && val_treq_tlast) begin
first_beat <= 'b1;
end else if (treq_advance_condition) begin
first_beat <= 'b0;
end
end
assign current_tid = val_treq_tdata[:];
assign current_ftype = val_treq_tdata[:];
assign current_ttype = val_treq_tdata[:];
assign current_size = val_treq_tdata[:];
assign current_prio = val_treq_tdata[:] + 'b01;
assign current_addr = val_treq_tdata[:];
assign current_srcid = val_treq_tuser[:]; // collect incoming requests that require a response, queue them
always @(posedge log_clk) begin
if (log_rst_q) begin
generate_a_response <= 'b0;
end else if (first_beat && treq_advance_condition) begin
generate_a_response <= (current_ftype == NREAD) ||
(current_ftype == DOORB) ||
(current_ftype == MESSG) ||
((current_ftype == NWRITE) && (current_ttype == TNWR_R));
end else begin
generate_a_response <= 'b0;
end
end
// }}} End Request Logic ---------------- // {{{ Local Data Storage ---------------
always @(posedge log_clk) begin
if (log_rst_q) begin
capture_data <= 'b0;
end else if (first_beat && treq_advance_condition && current_addr[:] == 'h12) begin
capture_data <= (current_ftype == SWRITE) || (current_ftype == NWRITE);
end else if (treq_advance_condition && val_treq_tlast) begin
capture_data <= 'b0;
end
end assign data_store_wen = capture_data && treq_advance_condition; always @(posedge log_clk) begin
if (log_rst_q) begin
data_store_waddr <= 'h0;
end else if (first_beat && treq_advance_condition) begin
data_store_waddr <= {'b0, current_addr[10:3]};
end else if (treq_advance_condition) begin
data_store_waddr <= data_store_waddr + ;
end
end always @(posedge log_clk) begin
if (log_rst_q) begin
data_store_raddr <= 'h0;
pull_from_store_q <= 'b0;
end else if (pull_from_store && current_beat_cnt == && !tresp_advance_condition &&
(rd_increment_qqq || first_packet_transfer)) begin
data_store_raddr <= starting_read_addr;
pull_from_store_q <= 'b1;
end else if ((pull_from_store_q && tresp_advance_condition) || first_packet_transfer_q || rd_increment_qqqq) begin
data_store_raddr <= data_store_raddr + ;
pull_from_store_q <= !(val_tresp_tlast && !rd_increment_qqqq);
end
end assign data_store_ren = val_tresp_tready || !val_tresp_tvalid; RAMB36SDP #(
.SIM_COLLISION_CHECK("NONE"),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE")
)
local_data_store (
.DI (val_treq_tdata),
.DIP ('h0),
.RDADDR (data_store_raddr),
.RDCLK (log_clk),
.RDEN (data_store_ren),
.REGCE ('b1),
.SSR (log_rst),
.WE ({{data_store_wen}}),
.WRADDR (data_store_waddr),
.WRCLK (log_clk),
.WREN (data_store_wen), .DO (data_store_dout),
.DOP (), .ECCPARITY (),
.SBITERR (),
.DBITERR ()
);
// }}} End Local Data Storage ----------- // {{{ Request Queue --------------------
assign response_data_in_d = {'h0, current_srcid, current_addr[23:16] == 8'h12, current_addr[:],
current_prio, current_tid, current_ftype, current_size};
always @ (posedge log_clk) begin
response_data_in <= response_data_in_d;
end always @(posedge log_clk) begin
if (log_rst_q) begin
out_of_packet <= 'b0;
end else if (rd_increment) begin
out_of_packet <= 'b0;
end else if (tresp_advance_condition && val_tresp_tlast) begin
out_of_packet <= 'b1;
end
end
assign rd_increment = ((tresp_advance_condition && val_tresp_tlast) || (out_of_packet)) &&
(response_rd_address != response_wr_address) &&
(response_rd_address + != response_wr_address);
always @(posedge log_clk) begin
if (log_rst_q) begin
response_wr_address <= 'h0;
response_rd_address <= 'h0;
end else begin
if (generate_a_response)
response_wr_address <= response_wr_address + ;
if (rd_increment)
response_rd_address <= response_rd_address + ;
end
end RAMB36SDP #(
.SIM_COLLISION_CHECK("NONE"),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE")
)
response_queue_inst (
.DI (response_data_in),
.DIP ('h0),
.RDADDR (response_rd_address),
.RDCLK (log_clk),
.RDEN ('b1),
.REGCE ('b1),
.SSR (log_rst),
.WE ({{generate_a_response}}),
.WRADDR (response_wr_address),
.WRCLK (log_clk),
.WREN (generate_a_response), .DO (response_data_out_d),
.DOP (), .ECCPARITY (),
.SBITERR (),
.DBITERR ()
); always @ (posedge log_clk) begin
response_data_out <= response_data_out_d[:];
end
assign response_tid = response_data_out[:];
assign response_ftype = response_data_out[:];
assign response_size = response_data_out[:];
assign response_prio = response_data_out[:];
assign dest_id = response_data_out[:];
assign starting_read_addr = {'b0, response_data_out[29:22]};
assign pull_from_store = response_data_out[]; // }}} End of Request Queue ------------- // {{{ Response Logic -------------------
assign number_of_data_beats = current_beat_cnt == ? response_size[:] : number_of_data_beats_q; always @(posedge log_clk) begin
if (log_rst_q) begin
current_beat_cnt <= 'h0;
end else if (tresp_advance_condition && val_tresp_tlast) begin
current_beat_cnt <= 'h0;
end else if (tresp_advance_condition) begin
current_beat_cnt <= current_beat_cnt + ;
end
end always @(posedge log_clk) begin
if (log_rst_q) begin
val_tresp_tlast <= 'b0;
end else if (responding_ttype == TNDATA || responding_ttype == MSGRSP) begin
val_tresp_tlast <= !(tresp_advance_condition && val_tresp_tlast);
end else if (current_beat_cnt == {'b0, number_of_data_beats} && tresp_advance_condition) begin
val_tresp_tlast <= !val_tresp_tlast;
end else if (val_tresp_tready || !val_tresp_tvalid) begin
val_tresp_tlast <= 'b0;
end
end assign responding_ttype = (response_ftype == NREAD) ? TWDATA : (response_ftype == MESSG) ? MSGRSP : TNDATA;
assign header_beat = {response_tid, RESP, responding_ttype, 'b0, response_prio, 45'h0};
always @(posedge log_clk) begin
if (current_beat_cnt == && !tresp_advance_condition) begin
val_tresp_tdata <= header_beat;
end else if (pull_from_store || pull_from_store_q) begin
if (tresp_advance_condition) begin
val_tresp_tdata <= data_store_dout;
end
end else begin
val_tresp_tdata <= {{data_beat}};
end
end
always @* begin
data_beat = data_beat_q;
if (tresp_advance_condition && current_beat_cnt != ) begin
data_beat = data_beat_q + ;
end
end
always @(posedge log_clk) begin
if (log_rst_q) begin
data_beat_q <= 'h00;
end else begin
data_beat_q <= data_beat;
end
end always @(posedge log_clk) begin
if (log_rst_q) begin
before_first_beat <= 'b1;
end else if (addresses_differ) begin
before_first_beat <= 'b0;
end
end
always @(posedge log_clk) begin
if (log_rst_q) begin
addresses_differ <= 'b0;
end else if (response_rd_address != response_wr_address) begin
addresses_differ <= 'b1;
end
end
always @(posedge log_clk) begin
if (log_rst_q) begin
first_packet_transfer <= 'b0;
end else if (before_first_beat && addresses_differ) begin
first_packet_transfer <= 'b1;
end else begin
first_packet_transfer <= 'b0;
end
end
always @(posedge log_clk) begin
if (log_rst_q) begin
first_packet_transfer_q <= 'b0;
end else begin
first_packet_transfer_q <= first_packet_transfer;
end
end
always @(posedge log_clk) begin
if (log_rst_q) begin
val_tresp_tvalid <= 'b0;
end else if (first_packet_transfer_q) begin
val_tresp_tvalid <= 'b1;
end else if (rd_increment_qqqq) begin
val_tresp_tvalid <= 'b1;
end else if (tresp_advance_condition && val_tresp_tlast) begin
val_tresp_tvalid <= 'b0;
end
end // }}} End Response Logic --------------- endmodule
// {{{ DISCLAIMER OF LIABILITY
// -----------------------------------------------------------------
// (c) Copyright 2010 - 2014 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
// }}}
srio_quick_start_srio_gen2_0.v源码
//
// (c) Copyright 2010 - 2014 Xilinx, Inc. All rights reserved.
//
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//----------------------------------------------------------------------
//
// SRIO_QUICK_START
// Description:
// This module sends a fixed set of instructions to the configuration
// register space, both local and remote.
//
// Hierarchy:
// SRIO_EXAMPLE_TOP
// |____> SRIO_DUT
// |____> SRIO_STATISTICS
// |____> SRIO_REPORT
// |____> SRIO_REQUEST_GEN
// |____> SRIO_RESPONSE_GEN
// |____> SRIO_QUICK_START
//
// --------------------------------------------------------------------- `timescale 1ps/1ps module srio_quick_start_srio_gen2_0 (
input log_clk,
input log_rst, output reg maintr_awvalid,
input maintr_awready,
output [:] maintr_awaddr, output reg maintr_wvalid,
input maintr_wready,
output [:] maintr_wdata,
input maintr_bvalid,
output maintr_bready,
input [:] maintr_bresp, output reg maintr_arvalid,
input maintr_arready,
output [:] maintr_araddr, input maintr_rvalid,
output maintr_rready,
input [:] maintr_rdata,
input [:] maintr_rresp, input go,
input [:] user_hop,
input user_inst,
input [:] user_addr,
input [:] user_data, input link_initialized,
output reg maint_done,
output reg maint_autocheck_error
); // {{{ local parameters -----------------
localparam [:] STARTING_ADDRESS = 'h0;
localparam NUMBER_OF_INSTRUCTIONS = ; localparam READ = 'b1;
localparam WRITE = 'b0;
localparam LOCAL = 'b0;
localparam REMTE = 'b1; localparam [:] MAINT = 'h8; localparam [:] RDREQ = 'h0;
localparam [:] WRREQ = 'h1; localparam [:] HOP_LOCAL = 'h00;
localparam [:] HOP_REMTE = 'hFF; `include "maintenance_list.vh"
// }}} End local parameters ------------- // {{{ wire declarations ----------------
reg [:] log_rst_shift;
wire log_rst_q = log_rst_shift[]; reg [:] link_initialized_cnt;
wire link_initialized_delay = link_initialized_cnt[]; wire [:] maint_data_out_d;
reg [:] maint_data_out; // upper 63:62 bits unused
reg [:] maint_address;
reg go_q;
wire go_rose; wire maint_req_advance_condition = (maintr_awready && maintr_awvalid) ||
(maintr_arready && maintr_arvalid);
wire maint_bresp_advance_condition = (maintr_bready && maintr_bvalid);
wire maint_resp_advance_condition = (maintr_rready && maintr_rvalid); reg last_packet_beat_q, last_packet_beat_qq, last_packet_beat_qqq;
reg [:] instruction_cnt;
wire [:] data_mask = { {{maint_data_out[]}}, {{maint_data_out[]}},
{{maint_data_out[]}}, {{maint_data_out[]}} };
// }}} End wire declarations ------------ // {{{ Common-use Signals --------------- always @(posedge log_clk or posedge log_rst) begin
if (log_rst)
log_rst_shift <= 'hFFFF;
else
log_rst_shift <= {log_rst_shift[:], 'b0};
end always @(posedge log_clk) begin
if (log_rst_q) begin
last_packet_beat_q <= 'b1;
last_packet_beat_qq <= 'b1;
last_packet_beat_qqq <= 'b1;
go_q <= 'b0;
end else begin
last_packet_beat_q <= maint_resp_advance_condition || maint_bresp_advance_condition;
last_packet_beat_qq <= last_packet_beat_q;
last_packet_beat_qqq <= last_packet_beat_qq || !link_initialized_delay;
go_q <= go;
end
end // put a sufficient delay on the initialization to improve simulation time.
// Not needed for actual hardware but does no damage if kept.
always @(posedge log_clk) begin
if (log_rst_q) begin
link_initialized_cnt <= ;
end else if (link_initialized && !link_initialized_delay) begin
link_initialized_cnt <= link_initialized_cnt + ;
end else if (!link_initialized) begin
link_initialized_cnt <= ;
end
end assign go_rose = go && !go_q;
// }}} End Common-use Signals ----------- // {{{ Request Packet Formatter ---------
always @(posedge log_clk) begin
if (log_rst_q) begin
maint_address <= STARTING_ADDRESS;
end else if (maint_resp_advance_condition || maint_bresp_advance_condition) begin
maint_address <= maint_address + ;
end
end assign maintr_wdata = go ? user_data : maint_data_out[:]; assign maintr_bready = 'b1;
assign maintr_rready = 'b1; assign maintr_araddr = go ? { 'h0, user_hop, user_addr} : maint_data_out[61:37];
assign maintr_awaddr = go ? { 'h0, user_hop, user_addr} : maint_data_out[61:37]; always @(posedge log_clk) begin
if (log_rst_q) begin
maintr_awvalid <= 'b0;
maintr_wvalid <= 'b0;
maintr_arvalid <= 'b0;
instruction_cnt <= 'h0;
end else if (link_initialized_delay &&
(instruction_cnt < NUMBER_OF_INSTRUCTIONS && last_packet_beat_qqq) || go_rose) begin
maintr_awvalid <= go ? user_inst == WRITE : maint_data_out[] == WRITE;
maintr_wvalid <= go ? user_inst == WRITE : maint_data_out[] == WRITE;
maintr_arvalid <= go ? user_inst == READ : maint_data_out[] == READ;
end else if (maint_req_advance_condition) begin
maintr_awvalid <= 'b0;
maintr_wvalid <= 'b0;
maintr_arvalid <= 'b0;
instruction_cnt <= instruction_cnt + ;
end else if (instruction_cnt == NUMBER_OF_INSTRUCTIONS) begin
maintr_awvalid <= 'b0;
maintr_wvalid <= 'b0;
maintr_arvalid <= 'b0;
end
end
// }}} End Request Packet Formatter ----- // {{{ Request generation ---------------
RAMB36SDP #(
.SIM_COLLISION_CHECK("NONE"),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"), .INIT_00({MAINTENANCE3 , MAINTENANCE2 , MAINTENANCE1 , MAINTENANCE0} ),
.INIT_01({MAINTENANCE7 , MAINTENANCE6 , MAINTENANCE5 , MAINTENANCE4} ),
.INIT_02({MAINTENANCE11 , MAINTENANCE10 , MAINTENANCE9 , MAINTENANCE8} ),
.INIT_03({MAINTENANCE15 , MAINTENANCE14 , MAINTENANCE13 , MAINTENANCE12} ),
.INIT_04({MAINTENANCE19 , MAINTENANCE18 , MAINTENANCE17 , MAINTENANCE16} ),
.INIT_05({MAINTENANCE23 , MAINTENANCE22 , MAINTENANCE21 , MAINTENANCE20} ),
.INIT_06({MAINTENANCE27 , MAINTENANCE26 , MAINTENANCE25 , MAINTENANCE24} ),
.INIT_07({MAINTENANCE31 , MAINTENANCE30 , MAINTENANCE29 , MAINTENANCE28} ),
.INIT_08({MAINTENANCE35 , MAINTENANCE34 , MAINTENANCE33 , MAINTENANCE32} ),
.INIT_09({MAINTENANCE39 , MAINTENANCE38 , MAINTENANCE37 , MAINTENANCE36} ),
.INIT_0A({MAINTENANCE43 , MAINTENANCE42 , MAINTENANCE41 , MAINTENANCE40} ),
.INIT_0B({MAINTENANCE47 , MAINTENANCE46 , MAINTENANCE45 , MAINTENANCE44} ),
.INIT_0C({MAINTENANCE51 , MAINTENANCE50 , MAINTENANCE49 , MAINTENANCE48} ),
.INIT_0D({MAINTENANCE55 , MAINTENANCE54 , MAINTENANCE53 , MAINTENANCE52} ),
.INIT_0E({MAINTENANCE59 , MAINTENANCE58 , MAINTENANCE57 , MAINTENANCE56} ),
.INIT_0F({MAINTENANCE63 , MAINTENANCE62 , MAINTENANCE61 , MAINTENANCE60} ),
.INIT_10({MAINTENANCE67 , MAINTENANCE66 , MAINTENANCE65 , MAINTENANCE64} ),
.INIT_11({MAINTENANCE71 , MAINTENANCE70 , MAINTENANCE69 , MAINTENANCE68} ),
.INIT_12({MAINTENANCE75 , MAINTENANCE74 , MAINTENANCE73 , MAINTENANCE72} ),
.INIT_13({MAINTENANCE79 , MAINTENANCE78 , MAINTENANCE77 , MAINTENANCE76} ),
.INIT_14({MAINTENANCE83 , MAINTENANCE82 , MAINTENANCE81 , MAINTENANCE80} ),
.INIT_15({MAINTENANCE87 , MAINTENANCE86 , MAINTENANCE85 , MAINTENANCE84} ),
.INIT_16({MAINTENANCE91 , MAINTENANCE90 , MAINTENANCE89 , MAINTENANCE88} ),
.INIT_17({MAINTENANCE95 , MAINTENANCE94 , MAINTENANCE93 , MAINTENANCE92} ),
.INIT_18({MAINTENANCE99 , MAINTENANCE98 , MAINTENANCE97 , MAINTENANCE96} ),
.INIT_19({MAINTENANCE103, MAINTENANCE102, MAINTENANCE101, MAINTENANCE100}),
.INIT_1A({MAINTENANCE107, MAINTENANCE106, MAINTENANCE105, MAINTENANCE104}),
.INIT_1B({MAINTENANCE111, MAINTENANCE110, MAINTENANCE109, MAINTENANCE108}),
.INIT_1C({MAINTENANCE115, MAINTENANCE114, MAINTENANCE113, MAINTENANCE112}),
.INIT_1D({MAINTENANCE119, MAINTENANCE118, MAINTENANCE117, MAINTENANCE116}),
.INIT_1E({MAINTENANCE123, MAINTENANCE122, MAINTENANCE121, MAINTENANCE120}),
.INIT_1F({MAINTENANCE127, MAINTENANCE126, MAINTENANCE125, MAINTENANCE124}),
.INIT_20({MAINTENANCE131, MAINTENANCE130, MAINTENANCE129, MAINTENANCE128}),
.INIT_21({MAINTENANCE135, MAINTENANCE134, MAINTENANCE133, MAINTENANCE132}),
.INIT_22({MAINTENANCE139, MAINTENANCE138, MAINTENANCE137, MAINTENANCE136}),
.INIT_23({MAINTENANCE143, MAINTENANCE142, MAINTENANCE141, MAINTENANCE140}),
.INIT_24({MAINTENANCE147, MAINTENANCE146, MAINTENANCE145, MAINTENANCE144}),
.INIT_25({MAINTENANCE151, MAINTENANCE150, MAINTENANCE149, MAINTENANCE148}),
.INIT_26({MAINTENANCE155, MAINTENANCE154, MAINTENANCE153, MAINTENANCE152}),
.INIT_27({MAINTENANCE159, MAINTENANCE158, MAINTENANCE157, MAINTENANCE156}),
.INIT_28({MAINTENANCE163, MAINTENANCE162, MAINTENANCE161, MAINTENANCE160}),
.INIT_29({MAINTENANCE167, MAINTENANCE166, MAINTENANCE165, MAINTENANCE164}),
.INIT_2A({MAINTENANCE171, MAINTENANCE170, MAINTENANCE169, MAINTENANCE168}),
.INIT_2B({MAINTENANCE175, MAINTENANCE174, MAINTENANCE173, MAINTENANCE172}),
.INIT_2C({MAINTENANCE179, MAINTENANCE178, MAINTENANCE177, MAINTENANCE176}),
.INIT_2D({MAINTENANCE183, MAINTENANCE182, MAINTENANCE181, MAINTENANCE180}),
.INIT_2E({MAINTENANCE187, MAINTENANCE186, MAINTENANCE185, MAINTENANCE184}),
.INIT_2F({MAINTENANCE191, MAINTENANCE190, MAINTENANCE189, MAINTENANCE188}),
.INIT_30({MAINTENANCE195, MAINTENANCE194, MAINTENANCE193, MAINTENANCE192}),
.INIT_31({MAINTENANCE199, MAINTENANCE198, MAINTENANCE197, MAINTENANCE196}),
.INIT_32({MAINTENANCE203, MAINTENANCE202, MAINTENANCE201, MAINTENANCE200}),
.INIT_33({MAINTENANCE207, MAINTENANCE206, MAINTENANCE205, MAINTENANCE204}),
.INIT_34({MAINTENANCE211, MAINTENANCE210, MAINTENANCE209, MAINTENANCE208}),
.INIT_35({MAINTENANCE215, MAINTENANCE214, MAINTENANCE213, MAINTENANCE212}),
.INIT_36({MAINTENANCE219, MAINTENANCE218, MAINTENANCE217, MAINTENANCE216}),
.INIT_37({MAINTENANCE223, MAINTENANCE222, MAINTENANCE221, MAINTENANCE220}),
.INIT_38({MAINTENANCE227, MAINTENANCE226, MAINTENANCE225, MAINTENANCE224}),
.INIT_39({MAINTENANCE231, MAINTENANCE230, MAINTENANCE229, MAINTENANCE228}),
.INIT_3A({MAINTENANCE235, MAINTENANCE234, MAINTENANCE233, MAINTENANCE232}),
.INIT_3B({MAINTENANCE239, MAINTENANCE238, MAINTENANCE237, MAINTENANCE236}),
.INIT_3C({MAINTENANCE243, MAINTENANCE242, MAINTENANCE241, MAINTENANCE240}),
.INIT_3D({MAINTENANCE247, MAINTENANCE246, MAINTENANCE245, MAINTENANCE244}),
.INIT_3E({MAINTENANCE251, MAINTENANCE250, MAINTENANCE249, MAINTENANCE248}),
.INIT_3F({MAINTENANCE255, MAINTENANCE254, MAINTENANCE253, MAINTENANCE252}),
.INIT_40({MAINTENANCE259, MAINTENANCE258, MAINTENANCE257, MAINTENANCE256}),
.INIT_41({MAINTENANCE263, MAINTENANCE262, MAINTENANCE261, MAINTENANCE260}),
.INIT_42({MAINTENANCE267, MAINTENANCE266, MAINTENANCE265, MAINTENANCE264}),
.INIT_43({MAINTENANCE271, MAINTENANCE270, MAINTENANCE269, MAINTENANCE268}),
.INIT_44({MAINTENANCE275, MAINTENANCE274, MAINTENANCE273, MAINTENANCE272}),
.INIT_45({MAINTENANCE279, MAINTENANCE278, MAINTENANCE277, MAINTENANCE276}),
.INIT_46({MAINTENANCE283, MAINTENANCE282, MAINTENANCE281, MAINTENANCE280}),
.INIT_47({MAINTENANCE287, MAINTENANCE286, MAINTENANCE285, MAINTENANCE284}),
.INIT_48({MAINTENANCE291, MAINTENANCE290, MAINTENANCE289, MAINTENANCE288}),
.INIT_49({MAINTENANCE295, MAINTENANCE294, MAINTENANCE293, MAINTENANCE292}),
.INIT_4A({MAINTENANCE299, MAINTENANCE298, MAINTENANCE297, MAINTENANCE296}),
.INIT_4B({MAINTENANCE303, MAINTENANCE302, MAINTENANCE301, MAINTENANCE300}),
.INIT_4C({MAINTENANCE307, MAINTENANCE306, MAINTENANCE305, MAINTENANCE304}),
.INIT_4D({MAINTENANCE311, MAINTENANCE310, MAINTENANCE309, MAINTENANCE308}),
.INIT_4E({MAINTENANCE315, MAINTENANCE314, MAINTENANCE313, MAINTENANCE312}),
.INIT_4F({MAINTENANCE319, MAINTENANCE318, MAINTENANCE317, MAINTENANCE316}),
.INIT_50({MAINTENANCE323, MAINTENANCE322, MAINTENANCE321, MAINTENANCE320}),
.INIT_51({MAINTENANCE327, MAINTENANCE326, MAINTENANCE325, MAINTENANCE324}),
.INIT_52({MAINTENANCE331, MAINTENANCE330, MAINTENANCE329, MAINTENANCE328}),
.INIT_53({MAINTENANCE335, MAINTENANCE334, MAINTENANCE333, MAINTENANCE332}),
.INIT_54({MAINTENANCE339, MAINTENANCE338, MAINTENANCE337, MAINTENANCE336}),
.INIT_55({MAINTENANCE343, MAINTENANCE342, MAINTENANCE341, MAINTENANCE340}),
.INIT_56({MAINTENANCE347, MAINTENANCE346, MAINTENANCE345, MAINTENANCE344}),
.INIT_57({MAINTENANCE351, MAINTENANCE350, MAINTENANCE349, MAINTENANCE348}),
.INIT_58({MAINTENANCE355, MAINTENANCE354, MAINTENANCE353, MAINTENANCE352}),
.INIT_59({MAINTENANCE359, MAINTENANCE358, MAINTENANCE357, MAINTENANCE356}),
.INIT_5A({MAINTENANCE363, MAINTENANCE362, MAINTENANCE361, MAINTENANCE360}),
.INIT_5B({MAINTENANCE367, MAINTENANCE366, MAINTENANCE365, MAINTENANCE364}),
.INIT_5C({MAINTENANCE371, MAINTENANCE370, MAINTENANCE369, MAINTENANCE368}),
.INIT_5D({MAINTENANCE375, MAINTENANCE374, MAINTENANCE373, MAINTENANCE372}),
.INIT_5E({MAINTENANCE379, MAINTENANCE378, MAINTENANCE377, MAINTENANCE376}),
.INIT_5F({MAINTENANCE383, MAINTENANCE382, MAINTENANCE381, MAINTENANCE380}),
.INIT_60({MAINTENANCE387, MAINTENANCE386, MAINTENANCE385, MAINTENANCE384}),
.INIT_61({MAINTENANCE391, MAINTENANCE390, MAINTENANCE389, MAINTENANCE388}),
.INIT_62({MAINTENANCE395, MAINTENANCE394, MAINTENANCE393, MAINTENANCE392}),
.INIT_63({MAINTENANCE399, MAINTENANCE398, MAINTENANCE397, MAINTENANCE396}),
.INIT_64({MAINTENANCE403, MAINTENANCE402, MAINTENANCE401, MAINTENANCE400}),
.INIT_65({MAINTENANCE407, MAINTENANCE406, MAINTENANCE405, MAINTENANCE404}),
.INIT_66({MAINTENANCE411, MAINTENANCE410, MAINTENANCE409, MAINTENANCE408}),
.INIT_67({MAINTENANCE415, MAINTENANCE414, MAINTENANCE413, MAINTENANCE412}),
.INIT_68({MAINTENANCE419, MAINTENANCE418, MAINTENANCE417, MAINTENANCE416}),
.INIT_69({MAINTENANCE423, MAINTENANCE422, MAINTENANCE421, MAINTENANCE420}),
.INIT_6A({MAINTENANCE427, MAINTENANCE426, MAINTENANCE425, MAINTENANCE424}),
.INIT_6B({MAINTENANCE431, MAINTENANCE430, MAINTENANCE429, MAINTENANCE428}),
.INIT_6C({MAINTENANCE435, MAINTENANCE434, MAINTENANCE433, MAINTENANCE432}),
.INIT_6D({MAINTENANCE439, MAINTENANCE438, MAINTENANCE437, MAINTENANCE436}),
.INIT_6E({MAINTENANCE443, MAINTENANCE442, MAINTENANCE441, MAINTENANCE440}),
.INIT_6F({MAINTENANCE447, MAINTENANCE446, MAINTENANCE445, MAINTENANCE444}),
.INIT_70({MAINTENANCE451, MAINTENANCE450, MAINTENANCE449, MAINTENANCE448}),
.INIT_71({MAINTENANCE455, MAINTENANCE454, MAINTENANCE453, MAINTENANCE452}),
.INIT_72({MAINTENANCE459, MAINTENANCE458, MAINTENANCE457, MAINTENANCE456}),
.INIT_73({MAINTENANCE463, MAINTENANCE462, MAINTENANCE461, MAINTENANCE460}),
.INIT_74({MAINTENANCE467, MAINTENANCE466, MAINTENANCE465, MAINTENANCE464}),
.INIT_75({MAINTENANCE471, MAINTENANCE470, MAINTENANCE469, MAINTENANCE468}),
.INIT_76({MAINTENANCE475, MAINTENANCE474, MAINTENANCE473, MAINTENANCE472}),
.INIT_77({MAINTENANCE479, MAINTENANCE478, MAINTENANCE477, MAINTENANCE476}),
.INIT_78({MAINTENANCE483, MAINTENANCE482, MAINTENANCE481, MAINTENANCE480}),
.INIT_79({MAINTENANCE487, MAINTENANCE486, MAINTENANCE485, MAINTENANCE484}),
.INIT_7A({MAINTENANCE491, MAINTENANCE490, MAINTENANCE489, MAINTENANCE488}),
.INIT_7B({MAINTENANCE495, MAINTENANCE494, MAINTENANCE493, MAINTENANCE492}),
.INIT_7C({MAINTENANCE499, MAINTENANCE498, MAINTENANCE497, MAINTENANCE496}),
.INIT_7D({MAINTENANCE503, MAINTENANCE502, MAINTENANCE501, MAINTENANCE500}),
.INIT_7E({MAINTENANCE507, MAINTENANCE506, MAINTENANCE505, MAINTENANCE504}),
.INIT_7F({MAINTENANCE511, MAINTENANCE510, MAINTENANCE509, MAINTENANCE508})
)
maintenance_data_inst (
.DI ('h0),
.DIP ('h0),
.RDADDR (maint_address),
.RDCLK (log_clk),
.RDEN ('b1),
.REGCE ('b1),
.SSR (log_rst),
.WE ('h0),
.WRADDR ('h0),
.WRCLK (log_clk),
.WREN ('b0), .DO (maint_data_out_d),
.DOP (), .ECCPARITY (),
.SBITERR (),
.DBITERR ()
);
always @ (posedge log_clk) begin
maint_data_out <= maint_data_out_d[:];
end // }}} End of Request Generation -------- // {{{ Response Side Check -------------- always @ (posedge log_clk) begin
if (log_rst_q) begin
maint_autocheck_error <= 'b0;
end else if (maint_resp_advance_condition && maint_data_out[] == READ) begin
if ((maintr_wdata & data_mask) != (maintr_rdata & data_mask)) begin
maint_autocheck_error <= 'b1;
end else begin
maint_autocheck_error <= 'b0;
end
end
end always @ (posedge log_clk) begin
if (log_rst_q) begin
maint_done <= 'b0;
end else if ((instruction_cnt == NUMBER_OF_INSTRUCTIONS) &&
(maint_bresp_advance_condition || maint_resp_advance_condition)) begin
maint_done <= 'b1;
end
end // }}} End Response Side Check ---------- endmodule
// {{{ DISCLAIMER OF LIABILITY
// -----------------------------------------------------------------
// (c) Copyright 2010 - 2014 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
// }}}
maintenance_list.vh源码
//-----------------------------------------------------------------------------
//
// (c) Copyright 2012 - 2014 Xilinx, Inc. All rights reserved.
//
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//----------------------------------------------------------------------------- // RSVD, LOCAL/REMTE, ADDRESS, RD/WR, DATA, DATA MASK
localparam [:] MAINTENANCE0 = {'b0, REMTE, 24'h000000, READ, 'h0480000E, 4'hF};
localparam [:] MAINTENANCE1 = {'b0, LOCAL, 24'h000000, READ, 'h0480000E, 4'hF};
localparam [:] MAINTENANCE2 = {'b0, REMTE, 24'h000060, WRITE, 'hDEADBEEF, 4'h0};
localparam [:] MAINTENANCE3 = {'b0, REMTE, 24'h000060, READ, 'h00ADBEEF, 4'hF}; localparam [:] MAINTENANCE4 = {'b0, LOCAL, 24'h00005C, WRITE, 'hFFFFFFFF, 4'h0};
localparam [:] MAINTENANCE5 = {'b0, LOCAL, 24'h00005C, READ, 'h7FE00000, 4'hF};
localparam [:] MAINTENANCE6 = {'b0, REMTE, 24'h00005C, WRITE, 'hFFFFFFFF, 4'h0};
localparam [:] MAINTENANCE7 = {'b0, REMTE, 24'h00005C, READ, 'h7FE00000, 4'hF}; localparam [:] MAINTENANCE8 = {'b0, REMTE, 24'h010000, WRITE, 'hFF020304, 4'h0};
localparam [:] MAINTENANCE9 = {'b0, LOCAL, 24'h010000, READ, 'h00020304, 4'h0};
localparam [:] MAINTENANCE10 = {'b0, LOCAL, 24'h010000, WRITE, 'h00030405, 4'h0};
localparam [:] MAINTENANCE11 = {'b0, REMTE, 24'h010000, READ, 'h00030405, 4'h0}; localparam [:] MAINTENANCE12 = {'b0, REMTE, 24'h000120, WRITE, 'hFFFFFFFF, 4'h0};
localparam [:] MAINTENANCE13 = {'b0, REMTE, 24'h000120, READ, 'hFFFFFF00, 4'h0};
localparam [:] MAINTENANCE14 = {'b0, LOCAL, 24'h000124, WRITE, 'h01020304, 4'h0};
localparam [:] MAINTENANCE15 = {'b0, LOCAL, 24'h000124, READ, 'h01020300, 4'h0}; localparam [:] MAINTENANCE16 = {'b0, LOCAL, 24'h000410, READ, 'h00007FC8, 4'h0};
localparam [:] MAINTENANCE17 = {'b0, LOCAL, 24'h000430, READ, 'h00107FC8, 4'h0};
localparam [:] MAINTENANCE18 = {'b0, REMTE, 24'h000450, READ, 'h00207FC8, 4'h0};
localparam [:] MAINTENANCE19 = {'b0, REMTE, 24'h000470, READ, 'h00307FC8, 4'h0}; localparam [:] MAINTENANCE20 = {'h0000000000000000};
localparam [:] MAINTENANCE21 = {'h0000000000000000}; localparam [:] MAINTENANCE22 = {'h0000000000000000};
localparam [:] MAINTENANCE23 = {'h0000000000000000};
localparam [:] MAINTENANCE24 = {'h0000000000000000};
localparam [:] MAINTENANCE25 = {'h0000000000000000};
localparam [:] MAINTENANCE26 = {'h0000000000000000};
localparam [:] MAINTENANCE27 = {'h0000000000000000};
localparam [:] MAINTENANCE28 = {'h0000000000000000};
localparam [:] MAINTENANCE29 = {'h0000000000000000};
localparam [:] MAINTENANCE30 = {'h0000000000000000};
localparam [:] MAINTENANCE31 = {'h0000000000000000};
localparam [:] MAINTENANCE32 = {'h0000000000000000};
localparam [:] MAINTENANCE33 = {'h0000000000000000};
localparam [:] MAINTENANCE34 = {'h0000000000000000};
localparam [:] MAINTENANCE35 = {'h0000000000000000};
localparam [:] MAINTENANCE36 = {'h0000000000000000};
localparam [:] MAINTENANCE37 = {'h0000000000000000};
localparam [:] MAINTENANCE38 = {'h0000000000000000};
localparam [:] MAINTENANCE39 = {'h0000000000000000};
localparam [:] MAINTENANCE40 = {'h0000000000000000};
localparam [:] MAINTENANCE41 = {'h0000000000000000};
localparam [:] MAINTENANCE42 = {'h0000000000000000};
localparam [:] MAINTENANCE43 = {'h0000000000000000};
localparam [:] MAINTENANCE44 = {'h0000000000000000};
localparam [:] MAINTENANCE45 = {'h0000000000000000};
localparam [:] MAINTENANCE46 = {'h0000000000000000};
localparam [:] MAINTENANCE47 = {'h0000000000000000};
localparam [:] MAINTENANCE48 = {'h0000000000000000};
localparam [:] MAINTENANCE49 = {'h0000000000000000};
localparam [:] MAINTENANCE50 = {'h0000000000000000};
localparam [:] MAINTENANCE51 = {'h0000000000000000};
localparam [:] MAINTENANCE52 = {'h0000000000000000};
localparam [:] MAINTENANCE53 = {'h0000000000000000};
localparam [:] MAINTENANCE54 = {'h0000000000000000};
localparam [:] MAINTENANCE55 = {'h0000000000000000};
localparam [:] MAINTENANCE56 = {'h0000000000000000};
localparam [:] MAINTENANCE57 = {'h0000000000000000};
localparam [:] MAINTENANCE58 = {'h0000000000000000};
localparam [:] MAINTENANCE59 = {'h0000000000000000};
localparam [:] MAINTENANCE60 = {'h0000000000000000};
localparam [:] MAINTENANCE61 = {'h0000000000000000};
localparam [:] MAINTENANCE62 = {'h0000000000000000};
localparam [:] MAINTENANCE63 = {'h0000000000000000};
localparam [:] MAINTENANCE64 = {'h0000000000000000};
localparam [:] MAINTENANCE65 = {'h0000000000000000};
localparam [:] MAINTENANCE66 = {'h0000000000000000};
localparam [:] MAINTENANCE67 = {'h0000000000000000};
localparam [:] MAINTENANCE68 = {'h0000000000000000};
localparam [:] MAINTENANCE69 = {'h0000000000000000};
localparam [:] MAINTENANCE70 = {'h0000000000000000};
localparam [:] MAINTENANCE71 = {'h0000000000000000};
localparam [:] MAINTENANCE72 = {'h0000000000000000};
localparam [:] MAINTENANCE73 = {'h0000000000000000};
localparam [:] MAINTENANCE74 = {'h0000000000000000};
localparam [:] MAINTENANCE75 = {'h0000000000000000};
localparam [:] MAINTENANCE76 = {'h0000000000000000};
localparam [:] MAINTENANCE77 = {'h0000000000000000};
localparam [:] MAINTENANCE78 = {'h0000000000000000};
localparam [:] MAINTENANCE79 = {'h0000000000000000};
localparam [:] MAINTENANCE80 = {'h0000000000000000};
localparam [:] MAINTENANCE81 = {'h0000000000000000};
localparam [:] MAINTENANCE82 = {'h0000000000000000};
localparam [:] MAINTENANCE83 = {'h0000000000000000};
localparam [:] MAINTENANCE84 = {'h0000000000000000};
localparam [:] MAINTENANCE85 = {'h0000000000000000};
localparam [:] MAINTENANCE86 = {'h0000000000000000};
localparam [:] MAINTENANCE87 = {'h0000000000000000};
localparam [:] MAINTENANCE88 = {'h0000000000000000};
localparam [:] MAINTENANCE89 = {'h0000000000000000};
localparam [:] MAINTENANCE90 = {'h0000000000000000};
localparam [:] MAINTENANCE91 = {'h0000000000000000};
localparam [:] MAINTENANCE92 = {'h0000000000000000};
localparam [:] MAINTENANCE93 = {'h0000000000000000};
localparam [:] MAINTENANCE94 = {'h0000000000000000};
localparam [:] MAINTENANCE95 = {'h0000000000000000};
localparam [:] MAINTENANCE96 = {'h0000000000000000};
localparam [:] MAINTENANCE97 = {'h0000000000000000};
localparam [:] MAINTENANCE98 = {'h0000000000000000};
localparam [:] MAINTENANCE99 = {'h0000000000000000};
localparam [:] MAINTENANCE100 = {'h0000000000000000};
localparam [:] MAINTENANCE101 = {'h0000000000000000};
localparam [:] MAINTENANCE102 = {'h0000000000000000};
localparam [:] MAINTENANCE103 = {'h0000000000000000};
localparam [:] MAINTENANCE104 = {'h0000000000000000};
localparam [:] MAINTENANCE105 = {'h0000000000000000};
localparam [:] MAINTENANCE106 = {'h0000000000000000};
localparam [:] MAINTENANCE107 = {'h0000000000000000};
localparam [:] MAINTENANCE108 = {'h0000000000000000};
localparam [:] MAINTENANCE109 = {'h0000000000000000};
localparam [:] MAINTENANCE110 = {'h0000000000000000};
localparam [:] MAINTENANCE111 = {'h0000000000000000};
localparam [:] MAINTENANCE112 = {'h0000000000000000};
localparam [:] MAINTENANCE113 = {'h0000000000000000};
localparam [:] MAINTENANCE114 = {'h0000000000000000};
localparam [:] MAINTENANCE115 = {'h0000000000000000};
localparam [:] MAINTENANCE116 = {'h0000000000000000};
localparam [:] MAINTENANCE117 = {'h0000000000000000};
localparam [:] MAINTENANCE118 = {'h0000000000000000};
localparam [:] MAINTENANCE119 = {'h0000000000000000};
localparam [:] MAINTENANCE120 = {'h0000000000000000};
localparam [:] MAINTENANCE121 = {'h0000000000000000};
localparam [:] MAINTENANCE122 = {'h0000000000000000};
localparam [:] MAINTENANCE123 = {'h0000000000000000};
localparam [:] MAINTENANCE124 = {'h0000000000000000};
localparam [:] MAINTENANCE125 = {'h0000000000000000};
localparam [:] MAINTENANCE126 = {'h0000000000000000};
localparam [:] MAINTENANCE127 = {'h0000000000000000};
localparam [:] MAINTENANCE128 = {'h0000000000000000};
localparam [:] MAINTENANCE129 = {'h0000000000000000};
localparam [:] MAINTENANCE130 = {'h0000000000000000};
localparam [:] MAINTENANCE131 = {'h0000000000000000};
localparam [:] MAINTENANCE132 = {'h0000000000000000};
localparam [:] MAINTENANCE133 = {'h0000000000000000};
localparam [:] MAINTENANCE134 = {'h0000000000000000};
localparam [:] MAINTENANCE135 = {'h0000000000000000};
localparam [:] MAINTENANCE136 = {'h0000000000000000};
localparam [:] MAINTENANCE137 = {'h0000000000000000};
localparam [:] MAINTENANCE138 = {'h0000000000000000};
localparam [:] MAINTENANCE139 = {'h0000000000000000};
localparam [:] MAINTENANCE140 = {'h0000000000000000};
localparam [:] MAINTENANCE141 = {'h0000000000000000};
localparam [:] MAINTENANCE142 = {'h0000000000000000};
localparam [:] MAINTENANCE143 = {'h0000000000000000};
localparam [:] MAINTENANCE144 = {'h0000000000000000};
localparam [:] MAINTENANCE145 = {'h0000000000000000};
localparam [:] MAINTENANCE146 = {'h0000000000000000};
localparam [:] MAINTENANCE147 = {'h0000000000000000};
localparam [:] MAINTENANCE148 = {'h0000000000000000};
localparam [:] MAINTENANCE149 = {'h0000000000000000};
localparam [:] MAINTENANCE150 = {'h0000000000000000};
localparam [:] MAINTENANCE151 = {'h0000000000000000};
localparam [:] MAINTENANCE152 = {'h0000000000000000};
localparam [:] MAINTENANCE153 = {'h0000000000000000};
localparam [:] MAINTENANCE154 = {'h0000000000000000};
localparam [:] MAINTENANCE155 = {'h0000000000000000};
localparam [:] MAINTENANCE156 = {'h0000000000000000};
localparam [:] MAINTENANCE157 = {'h0000000000000000};
localparam [:] MAINTENANCE158 = {'h0000000000000000};
localparam [:] MAINTENANCE159 = {'h0000000000000000};
localparam [:] MAINTENANCE160 = {'h0000000000000000};
localparam [:] MAINTENANCE161 = {'h0000000000000000};
localparam [:] MAINTENANCE162 = {'h0000000000000000};
localparam [:] MAINTENANCE163 = {'h0000000000000000};
localparam [:] MAINTENANCE164 = {'h0000000000000000};
localparam [:] MAINTENANCE165 = {'h0000000000000000};
localparam [:] MAINTENANCE166 = {'h0000000000000000};
localparam [:] MAINTENANCE167 = {'h0000000000000000};
localparam [:] MAINTENANCE168 = {'h0000000000000000};
localparam [:] MAINTENANCE169 = {'h0000000000000000};
localparam [:] MAINTENANCE170 = {'h0000000000000000};
localparam [:] MAINTENANCE171 = {'h0000000000000000};
localparam [:] MAINTENANCE172 = {'h0000000000000000};
localparam [:] MAINTENANCE173 = {'h0000000000000000};
localparam [:] MAINTENANCE174 = {'h0000000000000000};
localparam [:] MAINTENANCE175 = {'h0000000000000000};
localparam [:] MAINTENANCE176 = {'h0000000000000000};
localparam [:] MAINTENANCE177 = {'h0000000000000000};
localparam [:] MAINTENANCE178 = {'h0000000000000000};
localparam [:] MAINTENANCE179 = {'h0000000000000000};
localparam [:] MAINTENANCE180 = {'h0000000000000000};
localparam [:] MAINTENANCE181 = {'h0000000000000000};
localparam [:] MAINTENANCE182 = {'h0000000000000000};
localparam [:] MAINTENANCE183 = {'h0000000000000000};
localparam [:] MAINTENANCE184 = {'h0000000000000000};
localparam [:] MAINTENANCE185 = {'h0000000000000000};
localparam [:] MAINTENANCE186 = {'h0000000000000000};
localparam [:] MAINTENANCE187 = {'h0000000000000000};
localparam [:] MAINTENANCE188 = {'h0000000000000000};
localparam [:] MAINTENANCE189 = {'h0000000000000000};
localparam [:] MAINTENANCE190 = {'h0000000000000000};
localparam [:] MAINTENANCE191 = {'h0000000000000000};
localparam [:] MAINTENANCE192 = {'h0000000000000000};
localparam [:] MAINTENANCE193 = {'h0000000000000000};
localparam [:] MAINTENANCE194 = {'h0000000000000000};
localparam [:] MAINTENANCE195 = {'h0000000000000000};
localparam [:] MAINTENANCE196 = {'h0000000000000000};
localparam [:] MAINTENANCE197 = {'h0000000000000000};
localparam [:] MAINTENANCE198 = {'h0000000000000000};
localparam [:] MAINTENANCE199 = {'h0000000000000000};
localparam [:] MAINTENANCE200 = {'h0000000000000000};
localparam [:] MAINTENANCE201 = {'h0000000000000000};
localparam [:] MAINTENANCE202 = {'h0000000000000000};
localparam [:] MAINTENANCE203 = {'h0000000000000000};
localparam [:] MAINTENANCE204 = {'h0000000000000000};
localparam [:] MAINTENANCE205 = {'h0000000000000000};
localparam [:] MAINTENANCE206 = {'h0000000000000000};
localparam [:] MAINTENANCE207 = {'h0000000000000000};
localparam [:] MAINTENANCE208 = {'h0000000000000000};
localparam [:] MAINTENANCE209 = {'h0000000000000000};
localparam [:] MAINTENANCE210 = {'h0000000000000000};
localparam [:] MAINTENANCE211 = {'h0000000000000000};
localparam [:] MAINTENANCE212 = {'h0000000000000000};
localparam [:] MAINTENANCE213 = {'h0000000000000000};
localparam [:] MAINTENANCE214 = {'h0000000000000000};
localparam [:] MAINTENANCE215 = {'h0000000000000000};
localparam [:] MAINTENANCE216 = {'h0000000000000000};
localparam [:] MAINTENANCE217 = {'h0000000000000000};
localparam [:] MAINTENANCE218 = {'h0000000000000000};
localparam [:] MAINTENANCE219 = {'h0000000000000000};
localparam [:] MAINTENANCE220 = {'h0000000000000000};
localparam [:] MAINTENANCE221 = {'h0000000000000000};
localparam [:] MAINTENANCE222 = {'h0000000000000000};
localparam [:] MAINTENANCE223 = {'h0000000000000000};
localparam [:] MAINTENANCE224 = {'h0000000000000000};
localparam [:] MAINTENANCE225 = {'h0000000000000000};
localparam [:] MAINTENANCE226 = {'h0000000000000000};
localparam [:] MAINTENANCE227 = {'h0000000000000000};
localparam [:] MAINTENANCE228 = {'h0000000000000000};
localparam [:] MAINTENANCE229 = {'h0000000000000000};
localparam [:] MAINTENANCE230 = {'h0000000000000000};
localparam [:] MAINTENANCE231 = {'h0000000000000000};
localparam [:] MAINTENANCE232 = {'h0000000000000000};
localparam [:] MAINTENANCE233 = {'h0000000000000000};
localparam [:] MAINTENANCE234 = {'h0000000000000000};
localparam [:] MAINTENANCE235 = {'h0000000000000000};
localparam [:] MAINTENANCE236 = {'h0000000000000000};
localparam [:] MAINTENANCE237 = {'h0000000000000000};
localparam [:] MAINTENANCE238 = {'h0000000000000000};
localparam [:] MAINTENANCE239 = {'h0000000000000000};
localparam [:] MAINTENANCE240 = {'h0000000000000000};
localparam [:] MAINTENANCE241 = {'h0000000000000000};
localparam [:] MAINTENANCE242 = {'h0000000000000000};
localparam [:] MAINTENANCE243 = {'h0000000000000000};
localparam [:] MAINTENANCE244 = {'h0000000000000000};
localparam [:] MAINTENANCE245 = {'h0000000000000000};
localparam [:] MAINTENANCE246 = {'h0000000000000000};
localparam [:] MAINTENANCE247 = {'h0000000000000000};
localparam [:] MAINTENANCE248 = {'h0000000000000000};
localparam [:] MAINTENANCE249 = {'h0000000000000000};
localparam [:] MAINTENANCE250 = {'h0000000000000000};
localparam [:] MAINTENANCE251 = {'h0000000000000000};
localparam [:] MAINTENANCE252 = {'h0000000000000000};
localparam [:] MAINTENANCE253 = {'h0000000000000000};
localparam [:] MAINTENANCE254 = {'h0000000000000000};
localparam [:] MAINTENANCE255 = {'h0000000000000000};
localparam [:] MAINTENANCE256 = {'h0000000000000000};
localparam [:] MAINTENANCE257 = {'h0000000000000000};
localparam [:] MAINTENANCE258 = {'h0000000000000000};
localparam [:] MAINTENANCE259 = {'h0000000000000000};
localparam [:] MAINTENANCE260 = {'h0000000000000000};
localparam [:] MAINTENANCE261 = {'h0000000000000000};
localparam [:] MAINTENANCE262 = {'h0000000000000000};
localparam [:] MAINTENANCE263 = {'h0000000000000000};
localparam [:] MAINTENANCE264 = {'h0000000000000000};
localparam [:] MAINTENANCE265 = {'h0000000000000000};
localparam [:] MAINTENANCE266 = {'h0000000000000000};
localparam [:] MAINTENANCE267 = {'h0000000000000000};
localparam [:] MAINTENANCE268 = {'h0000000000000000};
localparam [:] MAINTENANCE269 = {'h0000000000000000};
localparam [:] MAINTENANCE270 = {'h0000000000000000};
localparam [:] MAINTENANCE271 = {'h0000000000000000};
localparam [:] MAINTENANCE272 = {'h0000000000000000};
localparam [:] MAINTENANCE273 = {'h0000000000000000};
localparam [:] MAINTENANCE274 = {'h0000000000000000};
localparam [:] MAINTENANCE275 = {'h0000000000000000};
localparam [:] MAINTENANCE276 = {'h0000000000000000};
localparam [:] MAINTENANCE277 = {'h0000000000000000};
localparam [:] MAINTENANCE278 = {'h0000000000000000};
localparam [:] MAINTENANCE279 = {'h0000000000000000};
localparam [:] MAINTENANCE280 = {'h0000000000000000};
localparam [:] MAINTENANCE281 = {'h0000000000000000};
localparam [:] MAINTENANCE282 = {'h0000000000000000};
localparam [:] MAINTENANCE283 = {'h0000000000000000};
localparam [:] MAINTENANCE284 = {'h0000000000000000};
localparam [:] MAINTENANCE285 = {'h0000000000000000};
localparam [:] MAINTENANCE286 = {'h0000000000000000};
localparam [:] MAINTENANCE287 = {'h0000000000000000};
localparam [:] MAINTENANCE288 = {'h0000000000000000};
localparam [:] MAINTENANCE289 = {'h0000000000000000};
localparam [:] MAINTENANCE290 = {'h0000000000000000};
localparam [:] MAINTENANCE291 = {'h0000000000000000};
localparam [:] MAINTENANCE292 = {'h0000000000000000};
localparam [:] MAINTENANCE293 = {'h0000000000000000};
localparam [:] MAINTENANCE294 = {'h0000000000000000};
localparam [:] MAINTENANCE295 = {'h0000000000000000};
localparam [:] MAINTENANCE296 = {'h0000000000000000};
localparam [:] MAINTENANCE297 = {'h0000000000000000};
localparam [:] MAINTENANCE298 = {'h0000000000000000};
localparam [:] MAINTENANCE299 = {'h0000000000000000};
localparam [:] MAINTENANCE300 = {'h0000000000000000};
localparam [:] MAINTENANCE301 = {'h0000000000000000};
localparam [:] MAINTENANCE302 = {'h0000000000000000};
localparam [:] MAINTENANCE303 = {'h0000000000000000};
localparam [:] MAINTENANCE304 = {'h0000000000000000};
localparam [:] MAINTENANCE305 = {'h0000000000000000};
localparam [:] MAINTENANCE306 = {'h0000000000000000};
localparam [:] MAINTENANCE307 = {'h0000000000000000};
localparam [:] MAINTENANCE308 = {'h0000000000000000};
localparam [:] MAINTENANCE309 = {'h0000000000000000};
localparam [:] MAINTENANCE310 = {'h0000000000000000};
localparam [:] MAINTENANCE311 = {'h0000000000000000};
localparam [:] MAINTENANCE312 = {'h0000000000000000};
localparam [:] MAINTENANCE313 = {'h0000000000000000};
localparam [:] MAINTENANCE314 = {'h0000000000000000};
localparam [:] MAINTENANCE315 = {'h0000000000000000};
localparam [:] MAINTENANCE316 = {'h0000000000000000};
localparam [:] MAINTENANCE317 = {'h0000000000000000};
localparam [:] MAINTENANCE318 = {'h0000000000000000};
localparam [:] MAINTENANCE319 = {'h0000000000000000};
localparam [:] MAINTENANCE320 = {'h0000000000000000};
localparam [:] MAINTENANCE321 = {'h0000000000000000};
localparam [:] MAINTENANCE322 = {'h0000000000000000};
localparam [:] MAINTENANCE323 = {'h0000000000000000};
localparam [:] MAINTENANCE324 = {'h0000000000000000};
localparam [:] MAINTENANCE325 = {'h0000000000000000};
localparam [:] MAINTENANCE326 = {'h0000000000000000};
localparam [:] MAINTENANCE327 = {'h0000000000000000};
localparam [:] MAINTENANCE328 = {'h0000000000000000};
localparam [:] MAINTENANCE329 = {'h0000000000000000};
localparam [:] MAINTENANCE330 = {'h0000000000000000};
localparam [:] MAINTENANCE331 = {'h0000000000000000};
localparam [:] MAINTENANCE332 = {'h0000000000000000};
localparam [:] MAINTENANCE333 = {'h0000000000000000};
localparam [:] MAINTENANCE334 = {'h0000000000000000};
localparam [:] MAINTENANCE335 = {'h0000000000000000};
localparam [:] MAINTENANCE336 = {'h0000000000000000};
localparam [:] MAINTENANCE337 = {'h0000000000000000};
localparam [:] MAINTENANCE338 = {'h0000000000000000};
localparam [:] MAINTENANCE339 = {'h0000000000000000};
localparam [:] MAINTENANCE340 = {'h0000000000000000};
localparam [:] MAINTENANCE341 = {'h0000000000000000};
localparam [:] MAINTENANCE342 = {'h0000000000000000};
localparam [:] MAINTENANCE343 = {'h0000000000000000};
localparam [:] MAINTENANCE344 = {'h0000000000000000};
localparam [:] MAINTENANCE345 = {'h0000000000000000};
localparam [:] MAINTENANCE346 = {'h0000000000000000};
localparam [:] MAINTENANCE347 = {'h0000000000000000};
localparam [:] MAINTENANCE348 = {'h0000000000000000};
localparam [:] MAINTENANCE349 = {'h0000000000000000};
localparam [:] MAINTENANCE350 = {'h0000000000000000};
localparam [:] MAINTENANCE351 = {'h0000000000000000};
localparam [:] MAINTENANCE352 = {'h0000000000000000};
localparam [:] MAINTENANCE353 = {'h0000000000000000};
localparam [:] MAINTENANCE354 = {'h0000000000000000};
localparam [:] MAINTENANCE355 = {'h0000000000000000};
localparam [:] MAINTENANCE356 = {'h0000000000000000};
localparam [:] MAINTENANCE357 = {'h0000000000000000};
localparam [:] MAINTENANCE358 = {'h0000000000000000};
localparam [:] MAINTENANCE359 = {'h0000000000000000};
localparam [:] MAINTENANCE360 = {'h0000000000000000};
localparam [:] MAINTENANCE361 = {'h0000000000000000};
localparam [:] MAINTENANCE362 = {'h0000000000000000};
localparam [:] MAINTENANCE363 = {'h0000000000000000};
localparam [:] MAINTENANCE364 = {'h0000000000000000};
localparam [:] MAINTENANCE365 = {'h0000000000000000};
localparam [:] MAINTENANCE366 = {'h0000000000000000};
localparam [:] MAINTENANCE367 = {'h0000000000000000};
localparam [:] MAINTENANCE368 = {'h0000000000000000};
localparam [:] MAINTENANCE369 = {'h0000000000000000};
localparam [:] MAINTENANCE370 = {'h0000000000000000};
localparam [:] MAINTENANCE371 = {'h0000000000000000};
localparam [:] MAINTENANCE372 = {'h0000000000000000};
localparam [:] MAINTENANCE373 = {'h0000000000000000};
localparam [:] MAINTENANCE374 = {'h0000000000000000};
localparam [:] MAINTENANCE375 = {'h0000000000000000};
localparam [:] MAINTENANCE376 = {'h0000000000000000};
localparam [:] MAINTENANCE377 = {'h0000000000000000};
localparam [:] MAINTENANCE378 = {'h0000000000000000};
localparam [:] MAINTENANCE379 = {'h0000000000000000};
localparam [:] MAINTENANCE380 = {'h0000000000000000};
localparam [:] MAINTENANCE381 = {'h0000000000000000};
localparam [:] MAINTENANCE382 = {'h0000000000000000};
localparam [:] MAINTENANCE383 = {'h0000000000000000};
localparam [:] MAINTENANCE384 = {'h0000000000000000};
localparam [:] MAINTENANCE385 = {'h0000000000000000};
localparam [:] MAINTENANCE386 = {'h0000000000000000};
localparam [:] MAINTENANCE387 = {'h0000000000000000};
localparam [:] MAINTENANCE388 = {'h0000000000000000};
localparam [:] MAINTENANCE389 = {'h0000000000000000};
localparam [:] MAINTENANCE390 = {'h0000000000000000};
localparam [:] MAINTENANCE391 = {'h0000000000000000};
localparam [:] MAINTENANCE392 = {'h0000000000000000};
localparam [:] MAINTENANCE393 = {'h0000000000000000};
localparam [:] MAINTENANCE394 = {'h0000000000000000};
localparam [:] MAINTENANCE395 = {'h0000000000000000};
localparam [:] MAINTENANCE396 = {'h0000000000000000};
localparam [:] MAINTENANCE397 = {'h0000000000000000};
localparam [:] MAINTENANCE398 = {'h0000000000000000};
localparam [:] MAINTENANCE399 = {'h0000000000000000};
localparam [:] MAINTENANCE400 = {'h0000000000000000};
localparam [:] MAINTENANCE401 = {'h0000000000000000};
localparam [:] MAINTENANCE402 = {'h0000000000000000};
localparam [:] MAINTENANCE403 = {'h0000000000000000};
localparam [:] MAINTENANCE404 = {'h0000000000000000};
localparam [:] MAINTENANCE405 = {'h0000000000000000};
localparam [:] MAINTENANCE406 = {'h0000000000000000};
localparam [:] MAINTENANCE407 = {'h0000000000000000};
localparam [:] MAINTENANCE408 = {'h0000000000000000};
localparam [:] MAINTENANCE409 = {'h0000000000000000};
localparam [:] MAINTENANCE410 = {'h0000000000000000};
localparam [:] MAINTENANCE411 = {'h0000000000000000};
localparam [:] MAINTENANCE412 = {'h0000000000000000};
localparam [:] MAINTENANCE413 = {'h0000000000000000};
localparam [:] MAINTENANCE414 = {'h0000000000000000};
localparam [:] MAINTENANCE415 = {'h0000000000000000};
localparam [:] MAINTENANCE416 = {'h0000000000000000};
localparam [:] MAINTENANCE417 = {'h0000000000000000};
localparam [:] MAINTENANCE418 = {'h0000000000000000};
localparam [:] MAINTENANCE419 = {'h0000000000000000};
localparam [:] MAINTENANCE420 = {'h0000000000000000};
localparam [:] MAINTENANCE421 = {'h0000000000000000};
localparam [:] MAINTENANCE422 = {'h0000000000000000};
localparam [:] MAINTENANCE423 = {'h0000000000000000};
localparam [:] MAINTENANCE424 = {'h0000000000000000};
localparam [:] MAINTENANCE425 = {'h0000000000000000};
localparam [:] MAINTENANCE426 = {'h0000000000000000};
localparam [:] MAINTENANCE427 = {'h0000000000000000};
localparam [:] MAINTENANCE428 = {'h0000000000000000};
localparam [:] MAINTENANCE429 = {'h0000000000000000};
localparam [:] MAINTENANCE430 = {'h0000000000000000};
localparam [:] MAINTENANCE431 = {'h0000000000000000};
localparam [:] MAINTENANCE432 = {'h0000000000000000};
localparam [:] MAINTENANCE433 = {'h0000000000000000};
localparam [:] MAINTENANCE434 = {'h0000000000000000};
localparam [:] MAINTENANCE435 = {'h0000000000000000};
localparam [:] MAINTENANCE436 = {'h0000000000000000};
localparam [:] MAINTENANCE437 = {'h0000000000000000};
localparam [:] MAINTENANCE438 = {'h0000000000000000};
localparam [:] MAINTENANCE439 = {'h0000000000000000};
localparam [:] MAINTENANCE440 = {'h0000000000000000};
localparam [:] MAINTENANCE441 = {'h0000000000000000};
localparam [:] MAINTENANCE442 = {'h0000000000000000};
localparam [:] MAINTENANCE443 = {'h0000000000000000};
localparam [:] MAINTENANCE444 = {'h0000000000000000};
localparam [:] MAINTENANCE445 = {'h0000000000000000};
localparam [:] MAINTENANCE446 = {'h0000000000000000};
localparam [:] MAINTENANCE447 = {'h0000000000000000};
localparam [:] MAINTENANCE448 = {'h0000000000000000};
localparam [:] MAINTENANCE449 = {'h0000000000000000};
localparam [:] MAINTENANCE450 = {'h0000000000000000};
localparam [:] MAINTENANCE451 = {'h0000000000000000};
localparam [:] MAINTENANCE452 = {'h0000000000000000};
localparam [:] MAINTENANCE453 = {'h0000000000000000};
localparam [:] MAINTENANCE454 = {'h0000000000000000};
localparam [:] MAINTENANCE455 = {'h0000000000000000};
localparam [:] MAINTENANCE456 = {'h0000000000000000};
localparam [:] MAINTENANCE457 = {'h0000000000000000};
localparam [:] MAINTENANCE458 = {'h0000000000000000};
localparam [:] MAINTENANCE459 = {'h0000000000000000};
localparam [:] MAINTENANCE460 = {'h0000000000000000};
localparam [:] MAINTENANCE461 = {'h0000000000000000};
localparam [:] MAINTENANCE462 = {'h0000000000000000};
localparam [:] MAINTENANCE463 = {'h0000000000000000};
localparam [:] MAINTENANCE464 = {'h0000000000000000};
localparam [:] MAINTENANCE465 = {'h0000000000000000};
localparam [:] MAINTENANCE466 = {'h0000000000000000};
localparam [:] MAINTENANCE467 = {'h0000000000000000};
localparam [:] MAINTENANCE468 = {'h0000000000000000};
localparam [:] MAINTENANCE469 = {'h0000000000000000};
localparam [:] MAINTENANCE470 = {'h0000000000000000};
localparam [:] MAINTENANCE471 = {'h0000000000000000};
localparam [:] MAINTENANCE472 = {'h0000000000000000};
localparam [:] MAINTENANCE473 = {'h0000000000000000};
localparam [:] MAINTENANCE474 = {'h0000000000000000};
localparam [:] MAINTENANCE475 = {'h0000000000000000};
localparam [:] MAINTENANCE476 = {'h0000000000000000};
localparam [:] MAINTENANCE477 = {'h0000000000000000};
localparam [:] MAINTENANCE478 = {'h0000000000000000};
localparam [:] MAINTENANCE479 = {'h0000000000000000};
localparam [:] MAINTENANCE480 = {'h0000000000000000};
localparam [:] MAINTENANCE481 = {'h0000000000000000};
localparam [:] MAINTENANCE482 = {'h0000000000000000};
localparam [:] MAINTENANCE483 = {'h0000000000000000};
localparam [:] MAINTENANCE484 = {'h0000000000000000};
localparam [:] MAINTENANCE485 = {'h0000000000000000};
localparam [:] MAINTENANCE486 = {'h0000000000000000};
localparam [:] MAINTENANCE487 = {'h0000000000000000};
localparam [:] MAINTENANCE488 = {'h0000000000000000};
localparam [:] MAINTENANCE489 = {'h0000000000000000};
localparam [:] MAINTENANCE490 = {'h0000000000000000};
localparam [:] MAINTENANCE491 = {'h0000000000000000};
localparam [:] MAINTENANCE492 = {'h0000000000000000};
localparam [:] MAINTENANCE493 = {'h0000000000000000};
localparam [:] MAINTENANCE494 = {'h0000000000000000};
localparam [:] MAINTENANCE495 = {'h0000000000000000};
localparam [:] MAINTENANCE496 = {'h0000000000000000};
localparam [:] MAINTENANCE497 = {'h0000000000000000};
localparam [:] MAINTENANCE498 = {'h0000000000000000};
localparam [:] MAINTENANCE499 = {'h0000000000000000};
localparam [:] MAINTENANCE500 = {'h0000000000000000};
localparam [:] MAINTENANCE501 = {'h0000000000000000};
localparam [:] MAINTENANCE502 = {'h0000000000000000};
localparam [:] MAINTENANCE503 = {'h0000000000000000};
localparam [:] MAINTENANCE504 = {'h0000000000000000};
localparam [:] MAINTENANCE505 = {'h0000000000000000};
localparam [:] MAINTENANCE506 = {'h0000000000000000};
localparam [:] MAINTENANCE507 = {'h0000000000000000};
localparam [:] MAINTENANCE508 = {'h0000000000000000};
localparam [:] MAINTENANCE509 = {'h0000000000000000};
localparam [:] MAINTENANCE510 = {'h0000000000000000};
localparam [:] MAINTENANCE511 = {'h0000000000000000}; // }}} End local parameters -------------
instruction_list.vh源码
localparam NUM_SWRITES = SEND_SWRITE ? : ;
localparam NUM_NWRITERS = SEND_NWRITER ? : ;
localparam NUM_NWRITES = SEND_NWRITE ? : ;
localparam NUM_NREADS = SEND_NREAD ? : ;
localparam NUM_DBS = SEND_DB ? : ;
localparam NUM_MSGS = SEND_MSG ? : ;
localparam NUM_FTYPE9 = SEND_FTYPE9 ? : ; localparam NUMBER_OF_INSTRUCTIONS = NUM_SWRITES + NUM_NWRITERS + NUM_NWRITES + NUM_NREADS + NUM_DBS + NUM_MSGS + NUM_FTYPE9; localparam [*-:] swrite_instruction = {
// RSVD, FTYPE, TTYPE, ADDRESS, SIZE
// SWRITEs
{'h000, SWRITE, 4'h0, 'h000000777, 8'd0},
{'h000, SWRITE, 4'h0, 'h000008806, 8'd0},
{'h000, SWRITE, 4'h0, 'h000000125, 8'd0},
{'h000, SWRITE, 4'h0, 'h000000124, 8'd0},
{'h000, SWRITE, 4'h0, 'h000000123, 8'd0},
{'h000, SWRITE, 4'h0, 'h000000122, 8'd0},
{'h000, SWRITE, 4'h0, 'h000000121, 8'd0},
{'h000, SWRITE, 4'h0, 'h000000120, 8'd0},
{'h000, SWRITE, 4'h0, 'h000000126, 8'd1},
{'h000, SWRITE, 4'h0, 'h000000124, 8'd1},
{'h000, SWRITE, 4'h0, 'h000000122, 8'd1},
{'h000, SWRITE, 4'h0, 'h000004350, 8'd1},
{'h000, SWRITE, 4'h0, 'h000004355, 8'd2},
{'h000, SWRITE, 4'h0, 'h000012300, 8'd2},
{'h000, SWRITE, 4'h0, 'h000012304, 8'd3},
{'h000, SWRITE, 4'h0, 'h000345000, 8'd3},
{'h000, SWRITE, 4'h0, 'h000345003, 8'd4},
{'h000, SWRITE, 4'h0, 'h004550000, 8'd4},
{'h000, SWRITE, 4'h0, 'h004550002, 8'd5},
{'h000, SWRITE, 4'h0, 'h198877600, 8'd5},
{'h000, SWRITE, 4'h0, 'h198877601, 8'd6},
{'h000, SWRITE, 4'h0, 'h2ABBCCDD8, 8'd6},
{'h000, SWRITE, 4'h0, 'h2ABBCCDD8, 8'd7},
{'h000, SWRITE, 4'h0, 'h2ABBCCDD8, 8'd15},
{'h000, SWRITE, 4'h0, 'h2ABBCCDD8, 8'd31},
{'h000, SWRITE, 4'h0, 'h120000600, 8'd63},
{'h000, SWRITE, 4'h0, 'h230000600, 8'd95},
{'h000, SWRITE, 4'h0, 'h340000600, 8'd127},
{'h000, SWRITE, 4'h0, 'h450000600, 8'd255},
{'h000, SWRITE, 4'h0, 'h560000600, 8'd15},
{'h000, SWRITE, 4'h0, 'h670000600, 8'd31},
{'h000, SWRITE, 4'h0, 'h780000600, 8'd63},
{'h000, SWRITE, 4'h0, 'h780000600, 8'd95},
{'h000, SWRITE, 4'h0, 'h890000600, 8'd127},
{'h000, SWRITE, 4'h0, 'h9A0000600, 8'd255},
{'h000, SWRITE, 4'h0, 'hAB0000600, 8'd15},
{'h000, SWRITE, 4'h0, 'hCD0000600, 8'd15}}; localparam [*-:] nwriter_instruction = {
// NWRITERs
{'h000, NWRITE, TNWR_R, 36'h000000777, 'd0},
{'h000, NWRITE, TNWR_R, 36'h000008806, 'd0},
{'h000, NWRITE, TNWR_R, 36'h000000125, 'd0},
{'h000, NWRITE, TNWR_R, 36'h000000124, 'd0},
{'h000, NWRITE, TNWR_R, 36'h000000123, 'd0},
{'h000, NWRITE, TNWR_R, 36'h000000122, 'd0},
{'h000, NWRITE, TNWR_R, 36'h000000121, 'd0},
{'h000, NWRITE, TNWR_R, 36'h000000120, 'd0},
{'h000, NWRITE, TNWR_R, 36'h000000126, 'd1},
{'h000, NWRITE, TNWR_R, 36'h000000124, 'd1},
{'h000, NWRITE, TNWR_R, 36'h000000122, 'd1},
{'h000, NWRITE, TNWR_R, 36'h000004350, 'd1},
{'h000, NWRITE, TNWR_R, 36'h000004355, 'd2},
{'h000, NWRITE, TNWR_R, 36'h000012300, 'd2},
{'h000, NWRITE, TNWR_R, 36'h000012304, 'd3},
{'h000, NWRITE, TNWR_R, 36'h000345000, 'd3},
{'h000, NWRITE, TNWR_R, 36'h000345003, 'd4},
{'h000, NWRITE, TNWR_R, 36'h004550000, 'd4},
{'h000, NWRITE, TNWR_R, 36'h004550002, 'd5}}; localparam [*-:] nwrite_instruction = {
// NWRITEs
{'h000, NWRITE, TNWR, 36'h198877600, 'd5},
{'h000, NWRITE, TNWR, 36'h198877601, 'd6},
{'h000, NWRITE, TNWR, 36'h2ABBCCDD8, 'd6},
{'h000, NWRITE, TNWR, 36'h2ABBCCDD8, 'd7},
{'h000, NWRITE, TNWR, 36'h2ABBCCDD8, 'd15},
{'h000, NWRITE, TNWR, 36'h2ABBCCDD8, 'd31},
{'h000, NWRITE, TNWR, 36'h120000600, 'd63},
{'h000, NWRITE, TNWR, 36'h230000600, 'd95},
{'h000, NWRITE, TNWR, 36'h340000600, 'd127},
{'h000, NWRITE, TNWR, 36'h450000600, 'd255},
{'h000, NWRITE, TNWR, 36'h560000600, 'd15},
{'h000, NWRITE, TNWR, 36'h670000600, 'd31},
{'h000, NWRITE, TNWR, 36'h780000600, 'd63},
{'h000, NWRITE, TNWR, 36'h890000600, 'd95},
{'h000, NWRITE, TNWR, 36'h9A0000600, 'd127},
{'h000, NWRITE, TNWR, 36'hAB0000600, 'd255},
{'h000, NWRITE, TNWR, 36'hBC0000600, 'd15},
{'h000, NWRITE, TNWR, 36'hCD0000600, 'd15},
{'h000, NWRITE, TNWR, 36'hDE0000600, 'd15}}; localparam [*-:] nread_instruction = {
// NREADs
{'h000, NREAD, TNRD, 36'h000002307, 'd00},
{'h000, NREAD, TNRD, 36'h000002406, 'd00},
{'h000, NREAD, TNRD, 36'h000002505, 'd00},
{'h000, NREAD, TNRD, 36'h000002604, 'd00},
{'h000, NREAD, TNRD, 36'h000002703, 'd00},
{'h000, NREAD, TNRD, 36'h000002802, 'd00},
{'h000, NREAD, TNRD, 36'h000002301, 'd00},
{'h000, NREAD, TNRD, 36'h000002400, 'd00},
{'h000, NREAD, TNRD, 36'h000002506, 'd01},
{'h000, NREAD, TNRD, 36'h000002604, 'd01},
{'h000, NREAD, TNRD, 36'h000002702, 'd01},
{'h000, NREAD, TNRD, 36'h000002800, 'd01},
{'h000, NREAD, TNRD, 36'h000002305, 'd02},
{'h000, NREAD, TNRD, 36'h000002400, 'd02},
{'h000, NREAD, TNRD, 36'h000002504, 'd03},
{'h000, NREAD, TNRD, 36'h000002600, 'd03},
{'h000, NREAD, TNRD, 36'h000002703, 'd04},
{'h000, NREAD, TNRD, 36'h000002800, 'd04},
{'h000, NREAD, TNRD, 36'h000002502, 'd05},
{'h000, NREAD, TNRD, 36'h000002600, 'd05},
{'h000, NREAD, TNRD, 36'h000002701, 'd06},
{'h000, NREAD, TNRD, 36'h000002800, 'd06},
{'h000, NREAD, TNRD, 36'h0000023F0, 'd07},
{'h000, NREAD, TNRD, 36'h000002400, 'd15},
{'h000, NREAD, TNRD, 36'h000002500, 'd31},
{'h000, NREAD, TNRD, 36'h000002600, 'd63}}; localparam [*-:] db_instruction = {
// DOORBELLs
{'h000, DOORB, 4'b0, 'h0DBDB0000, 8'd01},
{'h000, DOORB, 4'b0, 'h044440000, 8'd01}}; localparam [*-:] msg_instruction = {
// MESSAGEs
{'h000, MESSG, 4'b0, 'h000000002, 8'd07},
{'h000, MESSG, 4'b0, 'h000000012, 8'd07},
{'h000, MESSG, 4'b0, 'h000000022, 8'd07},
{'h000, MESSG, 4'b0, 'h000000002, 8'd07},
{'h000, MESSG, 4'b0, 'h000000012, 8'd07},
{'h000, MESSG, 4'b0, 'h000000022, 8'd07},
{'h000, MESSG, 4'b0, 'h000000002, 8'd07},
{'h000, MESSG, 4'b0, 'h000000012, 8'd07},
{'h000, MESSG, 4'b0, 'h000000022, 8'd07},
{'h000, MESSG, 4'b0, 'h000000002, 8'd07},
{'h000, MESSG, 4'b0, 'h000000012, 8'd07},
{'h000, MESSG, 4'b0, 'h000000022, 8'd07},
{'h000, MESSG, 4'b0, 'h000000002, 8'd07},
{'h000, MESSG, 4'b0, 'h000000012, 8'd07},
{'h000, MESSG, 4'b0, 'h000000022, 8'd07},
{'h000, MESSG, 4'b0, 'h000000002, 8'd07},
{'h000, MESSG, 4'b0, 'h000000012, 8'd07}}; localparam [*-:] ftype9_instruction = {
// FTYPE9
{'h000, FTYPE9, 4'b0, 'h0DBDB1000, 8'd7}};
// {{{ DISCLAIMER OF LIABILITY
// -----------------------------------------------------------------
// (c) Copyright 2012 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
// }}}
八、参考资料
1、pg007_srio_gen2，下载地址： https://china.xilinx.com/support/documentation/ip_documentation/srio_gen2/v4_0/pg007_srio_gen2.pdf
2、ug190 ，下载地址：https://www.xilinx.com/support/documentation/user_guides/ug190.pdf
3、pg058-blk-mem-gen ， 下载地址：https://www.xilinx.com/support/documentation/ip_documentation/blk_mem_gen/v8_3/pg058-blk-mem-gen.pdf
4、Vivado2015.4.2 SRIO例子工程源码
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