`timescale 1ns/1ps module adc_dis( clk , rst_n , sm_seg , sm_bit ); input clk;//50HZ input rst_n; :] sm_seg;//段选 :] sm_bit;//位选 :] sm_seg; :] sm_bit; :] count; :] count2; :] i;//数码管位数 reg clk1, clk2; :]ge,shi,bai,qian,wan,swan; :] ge_reg,shi_reg,bai_…