A delta cycle is a VHDL construct used to makeVHDL, a concurrent language, executable on asequential computer. For RTL design, you can adopt some simple rules andforget about delta cycles. For testbenches, often you must have a good understandingof w…

使用Verdi理解RTL design 接触到一些RTL代码,在阅读与深入理解的过程中的一些思考记录 协议与设计框图 认真反复阅读理解相关协议与设计框图,一个design的设计文档中,设计框图展示了这个设计的核心框架,包括协议的整体框架.作者的设计思路和design的组成结构等. 1.根据协议理解设计框图 2.根据设计框图理解module 3.根据设计框图初步追踪输入输出关键信号 理解Schematic及module间的关系 结合设计框图,使用Verdi的Schematic功能,整体理清各个mo…

"Delta cycles are an HDL concept used to order events that occur in zero physical time."sigasi.com Taking the definition for Sigasi, what VHDL calls delay cycles, Verilog calls a scheduler. How VHDL and Verilog determine the order of zero time e…

In digital logic simulation, a delta cycles are evaluation of expressions, followed by value updates, causing more evaluations, and more value updates, and so on. Each time through the loop is one delta cycle. Different languages have specific defini…

2013-06-25 16:40:45 下面是xilinx官网上的问答贴: http://china.xilinx.com/support/answers/41500.htm#solution The difference between RTL and technology schematic Description After XST synthesis is completed, I am able to view both RTL and technology schematic.I f…

2013-06-23 20:15:47 ISE综合后可以看到RTL Schematic,但我们知道在RTL编码时,要经常问自己一个问题“我写的这段代码会综合成什么样的电路呢”.对于一个简单的设计,比如一个触发器,综合后的RTL电路可能只有一个instance,就是触发器,很直观.但对于一个比较大的设计,RTL Schematic就比较复杂,包含了很多instance,怎么知道RTL Schematic中的instance与哪段代码对应呢,也就是如何找到感兴趣的instance在RTL代码中的de…

Verilog Interiew Quetions Collection :  What is the difference between $display and $monitor and $write and $strobe? What is the difference between code-compiled simulator and normal simulator? What is the difference between wire and reg? What is the…

2015-05-26   628   Code-Tuning Techniques    ——Even though a particular technique generally represents poor coding practice, specific circumstances might make it the best one to use.    ——One key to writing effective loops is to minimize the work don…

与uvm_tlm_if_base 一样,这个类也没有派生自任何类,定义了如下几个接口:get_next_item, try_next_item, item_done, get, peek, put, put_response. `define UVM_SEQ_ITEM_TASK_ERROR "Sequencer interface task not implemented" `define UVM_SEQ_ITEM_FUNCTION_ERROR "Sequencer inte…

uvm_globals.svh 存放全局的变量和方法.当UVM平台启动时,便在uvm_globals查找相应的方法,uvm_globals 的方法实现也比较简单,就是调用uvm_root对应的方法.其简略源代码如下: // Title: Globals //------------------------------------------------------------------------------ // // Group: Simulation Control // //-----…