BACKGROUND A single physical platform may be segregated into a plurality of virtual networks. Here, the physical platform incorporates at least one virtual machine monitor (VMM). A conventional VMM typically runs on a computer and presents to other s…

BACKGROUND INFORMATION An embodiment of the present invention relates generally to virtualization platforms and, more specifically, to a system and method to run components of a virtual machine monitor at a reduced privilege level. Various mechanisms…

BACKGROUND Standard computer interconnects, particularly for personal computers or workstations, may employ a bus such as Peripheral Component Interconnect ("PCI"), Industry Standard Architecture ("ISA"), or Extended ISA ("EISA&qu…

An OpenFlow switch in an OpenFlow environment includes an attack determination module to collect statistical information on packet processing with respect to incoming packets to be processed in the OpenFlow switch at a predetermined period interval t…

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BACKGROUND OF THE INVENTION A virtual machine (VM) may be or include a framework or environment created by for example a virtual machine monitor (VMM) on a host system. A VMM may provide facilities or resources on a host environment for an applicatio…

An apparatus and method is described herein for providing robust speculative code section abort control mechanisms. Hardware is able to track speculative code region abort events, conditions, and/or scenarios, such as an explicit abort instruction, a…

A method and apparatus for verification of coherence for shared cache components in a system verification environment are provided. With the method and apparatus, stores to the cache are applied to a cache functional simulator in the order that they…

A method and apparatus for executing lock instructions speculatively in an out-of-order processor are disclosed. In one embodiment, a prediction is made whether a given lock instruction will actually be contended. If not, then the lock instruction ma…

A method and apparatus for a atomic operation is described. A method comprises receiving a first program unit in a parallel computing environment, the first program unit including a memory update operation to be performed atomically, the memory updat…

BACKGROUND Many computing systems include a network interface card (NIC) to provide for communications with other systems and devices over a network. In a computing system running multiple operating systems (OSs) on multiple virtual machines, each OS…

BACKGROUND INFORMATION Various mechanisms exist for managing memory in a virtual machine environment. A virtual machine platform typically executes an underlying layer of software called a virtual machine monitor (VMM) which hosts one to many operati…

Described herein is a method and an apparatus for training a memory signal via an error signal of a memory. The method comprises transmitting from a memory controller a command-address (C/A) signal to a memory module; determining by the memory contro…

BACKGROUND A graphics processing unit (GPU) is a specialized electronic device that is specifically designed to perform operations related to graphics processing. GPUs are often built with a highly parallel structure that provides more efficient proc…

BACKGROUND As processing resources have increased, demands to run multiple software programs and operating systems on a single microprocessor have also increased. To meet these demands virtual environments have been developed to allocate a single com…

BACKGROUND Generally, the concept of virtualization in information processing systems allows multiple instances of one or more operating systems (each, an "OS") to run on a single information processing system, even though each OS is designed to…

BACKGROUND The present disclosure relates to the resource management of virtual machine(s) using hardware address mapping, and, more specifically, to facilitate direct access to devices from virtual machines, utilizing control of hardware address tra…

BACKGROUND OF THE INVENTION Various storage protocols for communicating with storage devices are known in the art. One example storage protocol is the Serial Advanced Technology Attachment (SATA) protocol. A protocol called Advanced Host Controller I…

BACKGROUND OF THE INVENTION The present invention relates generally to single-instruction, multiple-data (SIMD) processing and, more specifically, to a technique for saving and restoring thread group operating state. In a conventional SIMD architectu…

BACKGROUND OF THE INVENTION This relates to Input/Output (I/O) performance in a host system having multiple processors, and more particularly, to efficient usage of multiple processors in handling I/O completions by using interrupt affinity schemes t…

BACKGROUND The present subject matter relates, in general, to a computing system having multi-host processors and, in particular, to a serial ATA (SATA) controller for the multi-host processors. Processing speeds of central processing units (CPUs) of…

BACKGROUND OF THE INVENTION  1. Field of the Invention  The present invention relates generally to heterogeneous computer systems.  2. Background Art  Computers and other such data processing devices have at least one control processor that is genera…

ZZ:Solaris 10 软件包分析 http://blog.chinaunix.net/uid-22759617-id-276756.html # Last updated: 2006-02-14 #                     an analysis of Solaris 10 packages#                     ++++++++++++++++++++++++++++++++++#               SUNWCuser on SunBlade…

A system and method for providing dynamic device virtualization is herein disclosed. According to one embodiment, the computer-implemented method includes providing a hypervisor and one or more guest virtual machines (VMs). Each guest VM is disposed…

A method and apparatus for preserving memory ordering in a cache coherent link based interconnect in light of partial and non-coherent memory accesses is herein described. In one embodiment, partial memory accesses, such as a partial read, is impleme…

Methods, apparatus, and systems, including computer programs encoded on a computer storage medium, manage an address space. In some implementations, a method includes managing an allocation data structure for a memory, wherein the allocation data str…

A code sequence made up multiple instructions and specifying an offset from a base address is identified in an object file. The offset from the base address corresponds to an offset location in a memory configured for storing an address of a variable…

Apparatus and methods are provided for utilizing a plurality of processing units. A method comprises selecting a pending job from a plurality of unassigned jobs based on a plurality of assigned jobs for the plurality of processing units and assigning…

A multi-core processor includes logical partitions that have respective processor cores, memory areas, and Ethernet controllers. At least one of the Ethernet controllers is disabled for external communication and is assigned as an inter-partition Eth…

In particular embodiments, a method includes, from an indexer in a sensor network, accessing a set of sensor data that includes sensor data aggregated together from sensors in the sensor network, one or more time stamps for the sensor data, and metad…