A non-inclusive cache system includes an external cache and a plurality of on-chip caches each having a set of tags associated therewith, with at least one of the on-chip caches including data which is absent from the external cache. A pipelined snoo…
A multi-processor, multi-cache system has filter pipes that store entries for request messages sent to a central coherency controller. The central coherency controller orders requests from filter pipes using coherency rules but does not track complet…
A method and apparatus for verification of coherence for shared cache components in a system verification environment are provided. With the method and apparatus, stores to the cache are applied to a cache functional simulator in the order that they…
Aspects of the invention relate to improvements to the Least Recently Used (LRU) cache replacement method. Weighted LRU (WLRU) and Compact Weighted LRU (CWLRU) are CPU cache replacement methods that have superior hit rates to LRU replacement for prog…
cache是系统中的一块快速SRAM,价格高,但是访问速度快,可以减少CPU到main memory的latency. cache中的术语有: 1) Cache hits,表示可以在cache中,查找到相应地址的entry. 2) Cache Miss,表示在cache中,找不到相应地址的entry. 3) Snoop,cache不断监视transaction的地址线,来不间断的检查地址地址是否在cache中. 4) Snarf,从main memory中读出数据,同时更新cache中的旧值,称…
[前沿]研究生阶段从事于DSP和FPGA技术的相关研究工作,学习并整理了大量的技术资料,包括TI公司的官方文档和网络上的详细笔记,花费了大量的时间和精力总结了前人的工作成果.无奈工作却从事于嵌入式技术开发工作,与通信领域关系不大,它们来源于网络,自己亦觉得应该将它们共享于网络,以便于知识的传承和再生,做出自己应有的贡献. Cache是一种特殊的存储器,它由Cache 存储部件和Cache控制部件组成.Cache 存储部件一般采用与CPU同类型的半导体存储器件,存取速度比内存快几倍甚至十几倍.而C…
A processor employing a post-cache (LS2) buffer. Loads are stored into the LS2buffer after probing the data cache. The load/store unit snoops the loads in the LS2 buffer against snoop requests received from an external bus. If a snoop invalidate requ…
A data processing system includes a global promotion facility and a plurality of processors coupled by an interconnect. In response to execution of an acquisition instruction by a first processor among the plurality of processors, the first processor…
A pending tag system and method to maintain data coherence in a processing node during pending transactions in a transaction pipeline. A pending tag storage unit may be coupled to a cache controller and configured to store pending tags each indicativ…
A method of handling processor to processor interrupt requests in a multiprocessing computer bus environment is described. This method allows a multiple-tiered, increasing priority, interrupt request scheme. This method also allows processor to proce…