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verilog behavioral modeling ---Block statements

block statements : 1. sequential block  : begin-end block 2.parallel block       :  fork - join block block name : 如果block有自己的label, 1.可以disable 此block. 2.可以穿层次应用 block中的变量. 变量都是静态存储. PS:  when an assignement is to be made after two separate events h…

verilog behavioral modeling --procedural assignments

1.procedural assignments are used for updating reg ,integer , time ,real,realtime and memory data types. 2.difference between procedural assignments and continuous assignments    (1)continuous assignments drive nets and are evaluated and updated when…

verilog behavioral modeling --loop statement

1.forever 2.repeat 3.while 4.for The for statement accomplishes the same results as the following pseudo-code that is based on the while loop:   begin       initial_assignment;       while(condition)begin           statement;           step_assignmen…

verilog behavioral modeling--overview

1.verilog behavioral models contain procedural statements that control the simulation and manipulate variables of the data types.These statements are concurrent to model the inherent concurrence of hardware. 2.all of the flows defined by the initial…

verilog behavioral modeling--sequential and parallel statements

1.Sequential statement groups the begin-end keywords: .group several statements togethor .cause the statements to be evaluated sequentially(one at a time) *any timing within the sequential groups is relative to the previous statement *delays in the s…

verilog behavioral modeling--blocking and nonblocking

                                                                                             BLOCKING ASSIGNMENTS 1.A blocking procedural assignment statement shall be exectuted before the execution of the statements that follow it in a sequential bl…

verilog behaviral modeling -- procedural timing contronls

1.delay control : an expression specifies the time duration between initially encountering the statement and when the statement actually executes. the delay expressiong can be dynamic function of the state of the circuit,but it can be a simple number…

verilog behavioral modeling--branch statement

conditional statement case statement 1. conditional statement     if(expression)         statement_or_null[else statement_or_null]     | if_else_if_statement If the expression evaluates to true(that is ,has a nonzero know value),the first statement s…

verilog behavioral modeling--procedural continous assignment(不用)

assign / deassgin force /release the procedural continuous assignments(using keywords assign and force) are procedural statements that allow expressions to be driven continously onto variables or nets. 1. net_lvalue = expression  in force statement n…

verilog FAQ(zz)

1. What is the race condition in verilog? Ans :The situation when two expressions are allowed to execute at same instance of time without mentioning the order of execution. 2. List the levels of abstraction in verilog? Ans : 1. Behavioral level 2. Re…